CN106935555A - 晶片封装体及其制造方法 - Google Patents

晶片封装体及其制造方法 Download PDF

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Publication number
CN106935555A
CN106935555A CN201611236042.0A CN201611236042A CN106935555A CN 106935555 A CN106935555 A CN 106935555A CN 201611236042 A CN201611236042 A CN 201611236042A CN 106935555 A CN106935555 A CN 106935555A
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China
Prior art keywords
cover plate
wafer encapsulation
protective layer
layer
recess
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CN201611236042.0A
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English (en)
Inventor
沈佳伦
林柏伸
詹昂
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XinTec Inc
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XinTec Inc
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Publication of CN106935555A publication Critical patent/CN106935555A/zh
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Abstract

本发明提供一种晶片封装体及其制造方法。该晶片封装体包括：一基底，具有一前表面、一背表面及一侧表面；一重布线层，位于背表面上，且与基底内的一感测或元件区电性连接；一保护层，覆盖重布线层，且延伸到侧表面上；一盖板，位于前表面上，且横向地突出于侧表面上的保护层，盖板具有面向前表面的一第一表面及背向前表面的一第二表面，且盖板的一底部自第一表面朝第二表面变宽。本发明能够提升晶片封装体的品质及可靠度。

Description

晶片封装体及其制造方法
技术领域
本发明有关于一种晶片封装技术，特别为有关于采用晶圆级封装技术的一种晶片封装体及其制造方法。
背景技术
一般而言，晶圆级封装制程包括在晶圆阶段完成封装步骤，再予以切割成独立的晶片封装体。晶片封装体除了将晶片保护于其中，使其免受外界环境污染外，还提供晶片内部电子元件与外界的电性连接通路。
然而，在进行切割制程期间，晶圆内及/或晶圆上的膜层容易因切割偏移而破裂受损，且经切割处可能出现不均匀的凹陷或凸起，导致切割出的晶片封装体的品质及可靠度不佳。再者，晶圆的切割道的尺寸取决于切割刀具的尺寸，故单一晶圆能切割出的晶片封装体的数量有所限制，且切割刀具的切割速度慢，故切割制程所需的制程时间长，因此难以进一步降低制造成本及制造时间。
因此，有必要寻求一种新颖的晶片封装体及其制造方法，其能够解决或改善上述的问题。
发明内容
本发明提供一种晶片封装体，包括一基底、一重布线层、一保护层及一盖板。基底具有一前表面、一背表面及一侧表面。重布线层位于背表面上，且与基底内的一感测或元件区电性连接。保护层覆盖重布线层，且延伸到侧表面上。盖板位于前表面上，且横向地突出于侧表面上的保护层。盖板具有面向前表面的一第一表面及背向前表面的一第二表面，且盖板的一底部自第一表面朝第二表面变宽。
本发明还提供一种晶片封装体的制造方法，包括：提供一基底，基底具有一前表面、一背表面及一侧表面；在背表面上形成一重布线层，重布线层与基底内的一感测或元件区电性连接；形成一保护层，保护层覆盖重布线层，且延伸到侧表面上：以及在前表面上提供一盖板，盖板横向地突出于侧表面上的保护层，且具有面向前表面的一第一表面及背向前表面的一第二表面，且盖板的一底部自第一表面朝第二表面变宽。
本发明能够提升晶片封装体的品质及可靠度。
附图说明
图1A至1H是绘示出根据本发明一实施例的晶片封装体的制造方法的剖面示意图。
图2是绘示出根据本发明一实施例的晶片封装体的局部剖面示意图。
图3是绘示出根据本发明一实施例的晶片封装体的平面示意图。
图4A至4E是绘示出根据本发明另一实施例的晶片封装体的制造方法的剖面示意图。
其中，附图中符号的简单说明如下：100：基底；100a：前表面；100b：背表面；100c：侧表面；110：感测或元件区；120：晶片区；130：绝缘层；140：导电垫；150：光学部件；160：间隔层；165：粘着层；170：盖板；170a：第一表面；170b：第二表面；170c：侧表面；170d：侧表面；170e：侧表面；180：空腔；190：第一开口；200：第二开口；210：绝缘层；220：重布线层；230：保护层；230c：侧表面；240：孔洞；250：导电结构；260：凹口；270：凹口；280：刻痕；P：部分；SC：切割道。
具体实施方式
以下将详细说明本发明实施例的制作与使用方式。然而应注意的是，本发明提供许多可供应用的发明概念，其可以多种特定型式实施。文中所举例讨论的特定实施例仅为制造与使用本发明的特定方式，非用以限制本发明的范围。此外，在不同实施例中可能使用重复的标号或标示。这些重复仅为了简单清楚地叙述本发明，不代表所讨论的不同实施例及/或结构之间具有任何关连性。再者，当述及一第一材料层位于一第二材料层上或之上时，包括第一材料层与第二材料层直接接触或间隔有一或更多其他材料层的情形。
本发明一实施例的晶片封装体可用以封装微机电***晶片。然其应用不限于此，例如在本发明的晶片封装体的实施例中，其可应用于各种包含有源元件或无源元件(active or passive elements)、数字电路或模拟电路(digital or analog circuits)等集成电路的电子元件(electronic components)，例如是有关于光电元件(optoelectronic devices)、微机电***(Micro Electro Mechanical System，MEMS)、生物辨识元件(biometric device)、微流体***(micro fluidic systems)、或利用热、光线、电容及压力等物理量变化来测量的物理感测器(Physical Sensor)。特别是可选择使用晶圆级封装(wafer scale package，WSP)制程对影像感测元件、发光二极管(light-emittingdiodes，LEDs)、太阳能电池(solar cells)、射频元件(RF circuits)、加速计(accelerators)、陀螺仪(gyroscopes)、指纹辨识器(fingerprint recognition device)、微制动器(micro actuators)、表面声波元件(surface acoustic wave devices)、压力感测器(process sensors)或喷墨头(ink printer heads)等半导体晶片进行封装。
其中上述晶圆级封装制程主要指在晶圆阶段完成封装步骤后，再予以切割成独立的封装体，然而，在一特定实施例中，例如将已分离的半导体晶片重新分布在一承载晶圆上，再进行封装制程，亦可称之为晶圆级封装制程。另外，上述晶圆级封装制程亦适用于通过堆迭(stack)方式安排具有集成电路的多片晶圆，以形成多层集成电路(multi-layerintegrated circuit devices)的晶片封装体。
以下配合图1A至1H说明本发明一实施例的晶片封装体的制造方法，其中图1A至1H是绘示出根据本发明一实施例的晶片封装体的制造方法的剖面示意图。
请参照图1A，提供一基底100，其具有一前表面100a及一背表面100b，且包括多个晶片区120。为简化图式，此处仅绘示出一完整的晶片区120及与其相邻的晶片区120的一部分。在一些实施例中，基底100可为一硅基底或其他半导体基底。在一些实施例中，基底100为一硅晶圆，以利于进行晶圆级封装制程。
基底100的前表面100a上具有一绝缘层130。一般而言，绝缘层130可由层间介电层(interlayer dielectric，ILD)、金属间介电层(inter-metal dielectric，IMD)及覆盖的钝化层(passivation)组成。为简化图式，此处仅绘示出单层绝缘层130。在一些实施例中，绝缘层130可包括无机材料，例如氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合或其他适合的绝缘材料。
在一些实施例中，每一晶片区120的绝缘层130内具有一个或一个以上的导电垫140。在一些实施例中，导电垫140可为单层导电层或具有多层的导电层结构。为简化图式，此处仅以单层导电层作为范例说明。在一些实施例中，每一晶片区120的绝缘层130内包括一个或一个以上的开口，露出对应的导电垫140。
在一些实施例中，每一晶片区120内具有一感测或元件区110。感测或元件区110可邻近于绝缘层130及基底100的前表面100a，且可通过内连线结构(未绘示)与导电垫140电性连接。感测或元件区110内包括一感测元件。在一些实施例中，感测或元件区110内包括感光元件或其他适合的光电元件。在其他实施例中，感测或元件区110内可包括感测生物特征的元件(例如，一指纹辨识元件)、感测环境特征的元件(例如，一温度感测元件、一湿度感测元件、一压力感测元件、一电容感测元件)或其他适合的感测元件。
在一些实施例中，可依序进行半导体装置的前段(front end)制程(例如，在基底100内制作感测或元件区110)及后段(back end)制程(例如，在基底100上制作绝缘层130、内连线结构及导电垫140)来提供前述结构。换句话说，以下晶片封装体的制造方法用于对完成后段制程的基底进行后续的封装制程。
在一些实施例中，每一晶片区120内具有一光学部件150设置于基底100的前表面100a上，且对应于感测或元件区110。在一些实施例中，光学部件150可为微透镜阵列、滤光层、其组合或其他适合的光学部件。
接着，在一盖板170上形成一间隔层(或称作围堰(dam))160，通过间隔层160将盖板170接合至基底100的前表面100a上，且间隔层160在每一晶片区120内的基底100与盖板170之间形成一空腔180，使得光学部件150位于空腔180内，并通过盖板170保护空腔180内的光学部件150。在其他实施例中，可先在基底100的前表面100a上形成间隔层160，之后将盖板170接合至基底100上。在一些实施例中，盖板170可包括玻璃、氮化铝(AlN)、或其他适合的透明材料。在一些实施例中，盖板170的厚度可大约为700μm或其他适合的厚度。
在一些实施例中，间隔层160大致上不吸收水气。在一些实施例中，间隔层160不具有粘性，因此可通过额外的粘着胶将盖板170贴附于基底100上。在一些其他实施例中，间隔层160可具有粘性，因此可通过间隔层160将盖板170贴附于基底100上，如此一来间隔层160可不与任何的粘着胶接触，以确保间隔层160的位置不因粘着胶而移动。同时，由于不需使用粘着胶，可避免粘着胶溢流而污染光学部件150。
在一些实施例中，可通过沉积制程(例如，涂布制程、物理气相沉积制程、化学气相沉积制程或其他适合的制程)形成间隔层160。在一些实施例中，间隔层160可包括环氧树脂、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂(polyimide)、苯环丁烯(butylcyclobutene，BCB)、聚对二甲苯(parylene)、萘聚合物(polynaphthalenes)、氟碳化物(fluorocarbons)、丙烯酸酯(acrylates))或其他适合的绝缘材料。或者，间隔层160可包括光阻材料，且可通过曝光及显影制程而图案化，以露出光学部件150。
请参照图1B，以盖板170作为承载基板，对基底100的背表面100b进行薄化制程(例如，蚀刻制程、铣削(milling)制程、磨削(grinding)制程或研磨(polishing)制程)，以减少基底100的厚度。
接着，通过微影制程及蚀刻制程(例如，干蚀刻制程、湿蚀刻制程、等离子蚀刻制程、反应性离子蚀刻制程或其他适合的制程)，在每一晶片区120的基底100内同时形成多个第一开口190及第二开口200，第一开口190及第二开口200自基底100的背表面100b露出绝缘层130。在其他实施例中，可分别通过刻痕(notching)制程以及微影及蚀刻制程形成第二开口200以及第一开口190。
在一些实施例中，第一开口190对应于导电垫140而贯穿基底100，且第一开口190邻近于前表面100a的口径小于其邻近于背表面100b的口径，因此第一开口190具有倾斜的侧表面，进而降低后续形成于第一开口190内的膜层的制程难度，并提高可靠度。举例来说，由于第一开口190邻近于前表面100a的口径小于其邻近于背表面100b的口径，因此后续形成于第一开口190内的膜层(例如，后续形成的绝缘层210及重布线层220)能够较轻易地沉积于第一开口190与绝缘层130之间的转角，以避免影响电性连接路径或产生漏电流的问题。
在一些实施例中，第二开口200沿着相邻晶片区120之间的切割道SC延伸且贯穿基底100，使得每一晶片区120内的基底100彼此分离。第二开口200邻近于前表面100a的口径小于其邻近于背表面100b的口径，因此第二开口200具有倾斜的侧表面，亦即每一晶片区120内的基底100具有倾斜的一侧表面100c。
在一些实施例中，相邻两晶片区120内的多个第一开口190沿着第二开口200间隔排列，且第一开口190与第二开口200通过基底100的一部分(例如，侧壁部分)互相间隔且完全隔离。在一些实施例中，第二开口200可沿着晶片区120延伸而环绕第一开口190。在某些其他实施例中，第一开口190与第二开口200连通。例如，第一开口190邻近于背表面100b的部分与第二开口200邻近于背表面100b的部分彼此连通，使得基底100具有一侧壁部分低于背表面100b。换句话说，上述侧壁部分的厚度小于基底100的厚度。由于第一开口190与第二开口200彼此连通，而并非通过基底100的一部分完全隔离，因此能够防止应力累积于第一开口190与第二开口200之间的基底100，且可藉由第二开口200缓和及释放应力，进而避免基底100的侧壁部分出现破裂。
请参照图1C，可通过沉积制程(例如，涂布制程、物理气相沉积制程、化学气相沉积制程或其他适合的制程)，在基底100的背表面100b上形成一绝缘层210，绝缘层210顺应性沉积于第一开口190及第二开口200的侧壁及底部上。在一些实施例中，绝缘层210可包括环氧树脂、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他适合的绝缘材料。
接着，可通过微影制程及蚀刻制程，去除第一开口190底部的绝缘层210及其下方的绝缘层130，使得第一开口190延伸至绝缘层130内而露出对应的导电垫140。
之后，可通过沉积制程(例如，涂布制程、物理气相沉积制程、化学气相沉积制程、电镀制程、无电镀制程或其他适合的制程)、微影制程及蚀刻制程，在绝缘层210上形成图案化的重布线层220。重布线层220顺应性延伸至第一开口190及第二开口200的侧壁及底部，亦即重布线层220顺应性延伸至基底100的侧表面100c。
在本实施例中，重布线层220可通过绝缘层210与基底100电性隔离，且可经由第一开口190直接电性接触或间接电性连接露出的导电垫140。因此，第一开口190内的重布线层220也称为硅通孔电极(through silicon via，TSV)。在一些实施例中，重布线层220可包括铝、铜、金、铂、镍、锡、前述的组合、导电高分子材料、导电陶瓷材料(例如，氧化铟锡或氧化铟锌)或其他适合的导电材料。
请参照图1D，沿着切割道SC形成与第二开口200连通的一凹口260。凹口260穿过第二开口200内的重布线层220及绝缘层210，且穿过绝缘层130，而进一步延伸到间隔层160内。凹口260切断重布线层220，使得相邻晶片区120之间的重布线层220彼此分离。在其他实施例中，凹口260可能贯穿间隔层160。在一些实施例中，可进行切割制程来形成凹口260，但并不限定于此。举例来说，利用切割刀具切割重布线层220、绝缘层210、绝缘层130以及间隔层160，以形成凹口260。
请参照图1E，可通过沉积制程，在基底100的背表面100b及侧表面100c上形成一保护层230，以覆盖重布线层220。在一些实施例中，保护层230填满第二开口200。保护层230更填入凹口260，且覆盖重布线层220的末端。保护层230也覆盖绝缘层210的末端、绝缘层130的侧表面以及间隔层160的局部侧表面。
在一些实施例中，保护层230未填入第一开口190，使得一孔洞240形成于第一开口190内的重布线层220与保护层230之间。由于保护层230部分填充于第一开口190而留下孔洞240，因此后续制程中遭遇热循环(Thermal Cycle)时，孔洞240能够作为保护层230与重布线层220之间的缓冲，以降低保护层230与重布线层220之间由于热膨胀系数不匹配所引发不必要的应力，且防止外界温度或压力剧烈变化时保护层230会过度拉扯重布线层220，进而可避免靠近导电垫结构的重布线层220剥离甚至断路的问题。在一些其他实施例中，保护层230可局部填充第一开口190或完全填满第一开口190。
在一些实施例中，保护层230可包括环氧树脂、绿漆、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他适合的绝缘材料。
接着，可通过微影制程及蚀刻制程，在基底100的背表面100b上的保护层230内形成开口，以露出图案化的重布线层220的一部分。接着，可通过电镀制程、网版印刷制程或其他适合的制程，在保护层230的开口内填入导电结构250(例如，焊球、凸块或导电柱)，以与露出的重布线层220电性连接。在一些实施例中，导电结构250可包括锡、铅、铜、金、镍、或前述的组合。
请参照图1F，沿着切割道SC形成一凹口270。凹口270穿过第二开口200及凹口260内的保护层230，且穿过间隔层160，而进一步延伸到盖板170内。凹口270自盖板170面向前表面100a的一第一表面170a向盖板170内侧延伸。在一些实施例中，从俯视方向来看，凹口270沿着切割道SC环绕保护层230及导电结构250。在一些实施例中，盖板170内的凹口270具有三角形的剖面轮廓，但凹口270可具有其他形状的剖面轮廓，而并不限定于此。在一些实施例中，可进行激光钻孔制程或其他适合的制程来形成凹口270。
在一些实施例中，凹口270的宽度小于凹口260的宽度，且凹口270的深度大于凹口260的深度。在形成凹口270之后，保护层230仍然覆盖重布线层220的末端、绝缘层210的末端、绝缘层130的侧表面以及间隔层160的局部侧表面。
请参照图1G，在盖板170内形成一刻痕(notch)280，其自盖板170背向前表面100a的一第二表面170b延伸。在一些实施例中，刻痕280大致上对准于凹口270。在一些实施例中，刻痕280具有三角形的剖面轮廓，但刻痕280可具有其他形状的剖面轮廓，而并不限定于此。在一些实施例中，可进行利用划线(scribing)技术或其他适合的方法形成刻痕280。举例来说，使用(钻石)刀轮(cutter wheel)或其他适合的划线器(scriber)沿着切割道SC在盖板170的第二表面170b划线而形成刻痕280。
之后，利用断裂(breaking cut)技术，使用劈刀(breaker)或其他适合的方式将盖板170沿着凹口270及刻痕280垂直地断裂，以将每一晶片区120的盖板170彼此分离，进而形成多个独立的晶片封装体，如图1H所示。
根据本发明的上述实施例，在盖板170的第一表面170a形成凹口270且在盖板170的第二表面170b形成刻痕280，之后利用断裂技术将每一晶片区120的盖板170分离，以形成独立的晶片封装体。如此一来，盖板170能够直接沿着凹口270及刻痕280均匀地断裂，因而具有平直的侧表面。凹口270提升了断裂技术的精准度而有利于盖板170的分离，例如可避免盖板170的侧表面出现不均匀的凹陷及/或凸起，也防止盖板170的表面出现崩裂(chipping)的问题。
再者，在形成保护层230之前沿着切割道SC预先形成凹口260，后续形成的保护层230填入凹口260内，接着通过形成凹口270(例如，进行激光钻孔制程)将每一晶片区120的保护层230彼此分离，其中凹口270的尺寸小于凹口260的尺寸。如此一来，能够避免保护层230过度地破裂受损，以确保分离后的晶片封装体的侧表面能够受到保护层230良好地保护，且能够防止晶片封装体内的膜层(例如，重布线层220、绝缘层210、绝缘层130及间隔层160)在上述分离的过程中受到破坏，因此可提升晶片封装体的品质及可靠度。
请参照图1H、2及3，其中图2是绘示出图1H中晶片封装体的一部分P的剖面示意图，且图3是绘示出根据本发明一实施例的晶片封装体的平面示意图。为了说明本发明实施例，此处使用具有前照式(frontside illumination，FSI)感测装置的晶片封装体作为范例。然而，本发明实施例也可适用于具有背照式(backside illumination，BSI)感测装置的晶片封装体，亦不限定于任何特定的应用。
通过上述制造方法所形成的晶片封装体中，与感测或元件区110及导电垫140电性连接的重布线层220位于基底100的背表面100b上，且进一步延伸到侧表面100c。保护层230不仅覆盖背表面100b上的重布线层220，还覆盖侧表面100c上的重布线层220，且更延伸超出基底100的前表面100a。盖板170位于基底100的前表面100a上，且横向地突出于侧表面100c上的保护层230。换句话说，盖板170的宽度大于基底100的宽度，也大于保护层230的宽度，且盖板170的侧表面与保护层230的侧表面非共平面。
如图2所示，盖板170具有面向前表面100a的第一表面170a、背向前表面100a的第二表面170b、及侧表面170c。再者，凹口270的形成使得盖板170的底部具有邻接第一表面170a及侧表面170c的一侧表面170d，且刻痕280的形成使得盖板170的顶部具有邻接第二表面170b及侧表面170c的一侧表面170e。在一些实施例中，侧表面170c邻接盖板170的底部及顶部，且大致上垂直于第一表面170a及/或第二表面170b。再者，侧表面170d倾斜于第一表面170a及/或第二表面170b，侧表面170e倾斜于第一表面170a及/或第二表面170b，且侧表面170d及/或侧表面170e倾斜于侧表面170c。在一些实施例中，侧表面170d的一法向量大致上平行于侧表面170e。
如图1H及2所示，凹口270的形成使得盖板170的底部自第一表面170a朝第二表面170b变宽，且刻痕280的形成使得盖板170的顶部自第二表面170b朝第一表面170a变宽。在一些实施例中，盖板170的底部自第一表面170a朝第二表面170b渐进地变宽。再者，盖板170的顶部自第二表面170b朝第一表面170a渐进地变宽。在一些实施例中，盖板170的底部变宽的程度(gradient)大致上等同于盖板170的顶部变宽的程度。再者，盖板170夹设于底部与顶部的中间部分大致上具有均匀且一致的厚度，也就是说，中间部分的侧表面170c为平坦的表面。
如图1H及2所示，在一些实施例中，侧表面100c上的保护层230具有平坦的一侧表面230c。在一些实施例中，侧表面230c大致上垂直于第一表面170a及/或第二表面170b，且侧表面230c大致上平行于侧表面170c，如图3所示。在一些实施例中，侧表面170d倾斜于侧表面230c，且侧表面170e倾斜于侧表面230c。再者，在一些实施例中，第一表面170a的一边缘大致上对准于侧表面230c，且第二表面170b的一边缘大致上对准于侧表面230c。换句话说，侧表面170d的一边缘大致上对准于侧表面230c，且侧表面170e的一边缘大致上对准于侧表面230c。在一些实施例中，从俯视方向来看，侧表面170d环绕保护层230，如图3所示。
以下配合图4A至4E说明本发明另一实施例的晶片封装体的制造方法。图4A至4E是绘示出根据本发明另一实施例的晶片封装体的制造方法的剖面示意图，其中相同于图1A至1H中的部件使用相同的标号并省略其说明。
请参照图4A，可通过与图1A相同或相似的步骤提供基底100，其中每一晶片区120内的基底100的前表面100a上具有绝缘层130，且绝缘层130上具有光学部件150。接着，可通过一粘着层165将盖板170接合至基底100。在一些实施例中，形成于盖板170与基底100之间的粘着层165完全覆盖基底100的前表面100a，因此光学部件150、绝缘层130、导电垫140及感测或元件区110也被粘着层165所覆盖。在一些实施例中，黏着层165为双面胶材或其他适合的粘着材料。
请参照图4B，可通过与图1B相同或相似的步骤，对基底100进行薄化制程，且在基底100内形成第一开口190及第二开口200。接着，可通过与图1C相同或相似的步骤，在基底100的背表面100b上形成绝缘层210及重布线层220。
请参照图4C，可通过与图1D相同或相似的步骤，形成凹口260。凹口260穿过第二开口200内的重布线层220及绝缘层210，且穿过绝缘层130，而进一步延伸到粘着层165内。在其他实施例中，凹口260可能贯穿粘着层165，且使得后续形成的保护层230直接接触盖板170。接着，可通过与图1E相同或相似的步骤，在基底100的背表面100b上、第二开口200内及凹口260内形成保护层230。在一些实施例中，保护层230远离基底100的表面为平坦的。在一些其他实施例中，保护层230远离基底100的表面为不平坦的，例如保护层230覆盖第一开口190及/或第二开口200的表面可能为凹陷的表面。
请参照图4D，可通过与图1F及1G相同或相似的步骤，形成凹口270及刻痕280。凹口270穿过第二开口200及凹口260内的保护层230，且贯穿粘着层165，而进一步延伸到盖板170内。在一些实施例中，在形成凹口270之后形成刻痕280。在一些其他实施例中，可能在刻痕280之后形成凹口270。
通过激光钻孔制程而非使用切割刀具的切割制程来形成凹口270，可增加形成凹口270的精准度，避免凹口270的位置偏移而破坏其他膜层(例如，重布线层220、绝缘层210、绝缘层130及间隔层160)，也能够防止用于保护上述其他膜层的保护层230被过度移除，以确保上述其他膜层的侧表面能够受到良好的保护。
接着，可通过与图1H相同或相似的步骤，利用断裂技术将每一晶片区120的盖板170彼此分离，进而形成多个独立的晶片封装体，如图4E所示。
根据本发明的一些实施例，采用激光钻孔制程及断裂技术取代使用切割刀具的切割制程，不仅可避免切割偏移的问题，更使得晶圆的切割道的尺寸不会受限于切割刀具的尺寸(切割道的宽度可缩小至80μm以下，例如可为大约60μm或更小)，因此能够大幅增加切割道的设计弹性，且单一晶圆能切割出的晶片封装体的数量也能进一步增加。再者，相较于使用切割刀具，利用激光钻孔制程及断裂技术分离晶圆所需的制程时间短且制程费用也较低，因此能够有效降低制造成本及制造时间。
可以理解的是，上述晶片封装体的制造方法并不限定于具有光学感测装置的晶片封装体，其亦可应用于其他类型的晶片封装体。举例来说，上述形成凹口及刻痕的方法以及分离出多个晶片封装体的方法可应用于具有生物特征感测元件(例如，指纹辨识元件)或环境特征感测元件(例如，温度感测元件、湿度感测元件、压力感测元件、电容感测元件)的晶片封装体、或其他适合的晶片封装体。
以上所述仅为本发明较佳实施例，然其并非用以限定本发明的范围，任何熟悉本项技术的人员，在不脱离本发明的精神和范围内，可在此基础上做进一步的改进和变化，因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。

Claims (20)

1.一种晶片封装体，其特征在于，包括：
基底，具有前表面、背表面及侧表面；
重布线层，位于该背表面上，且与该基底内的感测或元件区电性连接；
保护层，覆盖该重布线层，且延伸到该侧表面上；以及
盖板，位于该前表面上，且横向地突出于该侧表面上的该保护层，其中该盖板具有面向该前表面的第一表面及背向该前表面的第二表面，且该盖板的底部自该第一表面朝该第二表面变宽。
2.根据权利要求1所述的晶片封装体，其特征在于，该盖板的该底部的侧表面邻接且倾斜于该第一表面。
3.根据权利要求1所述的晶片封装体，其特征在于，该盖板的顶部自该第二表面朝该第一表面变宽。
4.根据权利要求3所述的晶片封装体，其特征在于，该盖板的该顶部的侧表面邻接且倾斜于该第二表面。
5.根据权利要求1所述的晶片封装体，其特征在于，该盖板的侧表面邻接该底部且大致上垂直于该第一表面及/或该第二表面。
6.根据权利要求1所述的晶片封装体，其特征在于，该基底的该背表面上的该保护层具有平坦的侧表面，且该盖板的该第一表面的边缘大致上对准于该保护层的该侧表面。
7.根据权利要求1所述的晶片封装体，其特征在于，从俯视方向来看，该盖板的该底部的侧表面环绕该保护层。
8.根据权利要求1所述的晶片封装体，其特征在于，该重布线层进一步延伸到该基底的该侧表面上，且该保护层覆盖位于该侧表面上的该重布线层的末端。
9.根据权利要求1所述的晶片封装体，其特征在于，还包括绝缘层，该绝缘层位于该基底与该盖板之间，其中该绝缘层内具有导电垫与该感测或元件区及该重布线层电性连接，且该保护层覆盖该绝缘层的侧表面。
10.根据权利要求1所述的晶片封装体，其特征在于，还包括间隔层或粘着层，该间隔层或该粘着层位于该基底与该盖板之间，且具有被该保护层所覆盖的侧表面。
11.一种晶片封装体的制造方法，其特征在于，包括：
提供基底，其中该基底具有前表面、背表面及侧表面；
在该背表面上形成重布线层，其中该重布线层与该基底内的感测或元件区电性连接；
形成保护层，其中该保护层覆盖该重布线层，且延伸到该侧表面上；以及
在该前表面上提供盖板，其中该盖板横向地突出于该侧表面上的该保护层，且该盖板具有面向该前表面的第一表面及背向该前表面的第二表面，且该盖板的底部自该第一表面朝该第二表面变宽。
12.根据权利要求11所述的晶片封装体的制造方法，其特征在于，该重布线层进一步延伸到该侧表面上，且该晶片封装体的制造方法还包括在形成该保护层之前切割该重布线层，使得该侧表面上的该重布线层具有末端，且该保护层覆盖该末端。
13.根据权利要求11所述的晶片封装体的制造方法，其特征在于，还包括形成凹口，其中该凹口位于该背表面上的该保护层内且延伸到该盖板内，使得该盖板的该底部自该第一表面朝该第二表面变宽。
14.根据权利要求13所述的晶片封装体的制造方法，其特征在于，形成该凹口的步骤包括进行激光钻孔制程。
15.根据权利要求13所述的晶片封装体的制造方法，其特征在于，还包括在形成该重布线层之前，在该基底与该盖板之间形成间隔层或粘着层，其中该凹口延伸穿过该间隔层或该粘着层。
16.根据权利要求13所述的晶片封装体的制造方法，其特征在于，还包括在该盖板内形成刻痕，使得该盖板的顶部自该第二表面朝该第一表面变宽，其中该刻痕大致上对准于该凹口。
17.根据权利要求16所述的晶片封装体的制造方法，其特征在于，利用划线技术形成该刻痕。
18.根据权利要求16所述的晶片封装体的制造方法，其特征在于，在形成该凹口之后，形成该刻痕。
19.根据权利要求16所述的晶片封装体的制造方法，其特征在于，还包括利用断裂技术使得该盖板沿着该凹口及该刻痕而断裂。
20.根据权利要求19所述的晶片封装体的制造方法，其特征在于，该盖板沿着该凹口及该刻痕大致上垂直地断裂。
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