CN103545295B - 晶片封装体及其形成方法 - Google Patents

晶片封装体及其形成方法 Download PDF

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Publication number
CN103545295B
CN103545295B CN201310298458.5A CN201310298458A CN103545295B CN 103545295 B CN103545295 B CN 103545295B CN 201310298458 A CN201310298458 A CN 201310298458A CN 103545295 B CN103545295 B CN 103545295B
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substrate
wafer encapsulation
conductive pad
wafer
encapsulation body
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CN103545295A (zh
Inventor
何彦仕
陈世锦
张义民
陈键辉
郑家明
孙唯伦
江承翰
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XinTec Inc
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XinTec Inc
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Abstract

本发明提供一种晶片封装体及其形成方法，该晶片封装体包括：一半导体基底，具有一第一表面及相反的一第二表面；一元件区，设置于该半导体基底之中；一介电层，位于该半导体基底的该第一表面上；多个导电垫，位于该介电层中，且电性连接该元件区；至少一对准标记，设置于该半导体基底之中，且自该第二表面朝该第一表面延伸。本发明可提高晶片封装体的可靠度与品质。

Description

晶片封装体及其形成方法
技术领域
本发明有关于晶片封装体，且特别是有关于以晶圆级封装制程所制得的晶片封装体。
背景技术
晶片封装制程是形成电子产品过程中的一重要步骤。晶片封装体除了将晶片保护于其中，使免受外界环境污染外，还提供晶片内部电子元件与外界的电性连接通路。
由于晶片尺寸的缩小与接垫数目的提升，在晶片封装体中形成电性连接至接垫的线路更为困难。此外，晶片的切割制程的精准度会显著影响所形成的晶片封装体的可靠度与效能。因此，业界亟需改良的晶片封装技术。
发明内容
本发明一实施例提供一种晶片封装体，包括：一半导体基底，具有一第一表面及相反的一第二表面；一元件区，设置于该半导体基底之中；一介电层，位于该半导体基底的该第一表面上；多个导电垫，位于该介电层中，且电性连接该元件区；至少一对准标记，设置于该半导体基底之中，且自该第二表面朝该第一表面延伸。
本发明一实施例提供一种晶片封装体的形成方法，包括：提供一基底，该基底由多个预定切割道划分成多个晶粒区域，每一晶粒区域中形成有至少一元件区，其中一介电层形成于该基底的一第一表面上，且多个导电垫形成于该介电层之中，所述导电垫大抵沿着所述预定切割道排列；自该基底的一第二表面部分移除该基底以形成朝该第一表面延伸的多个对准标记，其中该基底的每一所述晶粒区形成有至少一所述对准标记；于该基底的该第二表面上形成一绝缘层；于该绝缘层上形成多个线路层，其中各所述线路层电性接触对应的所述导电垫；以及通过所述对准标记的辅助，沿着所述预定切割道进行一切割制程以形成彼此分离的多个晶片封装体。
本发明可提高晶片封装体的可靠度与品质。
附图说明
图1A显示本案发明人所知的一种晶片封装体的剖面图。
图1B显示本案发明人所知的一种晶片的俯视图。
图2A-2B显示根据本发明一实施例的晶片封装体的制程俯视图。
图3A-3F显示根据本发明一实施例的晶片封装体的制程剖面图。
图4A-4C显示根据本发明一实施例的晶片封装体的制程立体图。
图5A-5B显示根据本发明一实施例的晶片封装体的制程俯视图，用以说明本发明实施例的对准标记的形成。
图6显示本案发明人所知的一晶圆的俯视图。
图7显示根据本发明一实施例的晶片封装体的俯视图。
附图中符号的简单说明如下：
具体实施方式
以下将详细说明本发明实施例的制作与使用方式。然应注意的是，本发明提供许多可供应用的发明概念，其可以以多种特定形式实施。文中所举例讨论的特定实施例仅为制造与使用本发明的特定方式，非用以限制本发明的范围。此外，在不同实施例中可能使用重复的标号或标示。这些重复仅为了简单清楚地叙述本发明，不代表所讨论的不同实施例及/或结构之间必然具有任何关连性。再者，当述及一第一材料层位于一第二材料层上或之上时，包括第一材料层与第二材料层直接接触或间隔有一或更多其他材料层的情形。
本发明一实施例的晶片封装体可用以封装各种晶片。例如，在本发明的晶片封装体的实施例中，其可应用于各种包含有源元件或无源元件(active orpassive elements)、数字电路或模拟电路(digital or analog circuits)等集成电路的电子元件(electronic components)，例如是有关于光电元件(opto electronicdevices)、微机电***(Micro Electro Mechanical System;MEMS)、微流体***(micro fluidic systems)、或利用热、光线及压力等物理量变化来测量的物理感测器(Physical Sensor)。特别是可选择使用晶圆级封装(wafer scale package;WSP)制程对影像感测元件、发光二极管(light-emitting diodes;LEDs)、太阳能电池(solar cells)、射频元件(RF circuits)、加速计(accelerators)、陀螺仪(gyroscopes)、微制动器(micro actuators)、表面声波元件(surface acoustic wavedevices)、压力感测器(process sensors)喷墨头(ink printer heads)、或功率金属氧化物半导体场效应晶体管模组(power MOSFET modules)等半导体晶片进行封装。
其中上述晶圆级封装制程主要是指在晶圆阶段完成封装步骤后，再予以切割成独立的封装体，然而，在一特定实施例中，例如将已分离的半导体晶片重新分布在一承载晶圆上，再进行封装制程，亦可称之为晶圆级封装制程。另外，上述晶圆级封装制程亦适用于通过堆叠(stack)方式安排具有集成电路的多片晶圆，以形成多层集成电路(multi-layer integrated circuit devices)的晶片封装体。在一实施中，上述切割后的封装体为一晶片尺寸封装体(CSP;chipscale package)。晶片尺寸封装体(CSP)的尺寸可仅略大于所封装的晶片。例如，晶片尺寸封装体的尺寸不大于所封装晶片的尺寸的120%。
图1A显示本案发明人所知的一种晶片封装体的剖面图，而图1B显示本案发明人所知的一种晶片10的俯视图，其用以说明发明人所发现的问题。图1A是显示沿着图1B的切线I-I’的剖面图。
如图1B所示，所封装的晶片10包括基底100。基底100中形成有元件区102。基底100的表面100a上设置有多个导电垫106，其分别电性连接元件区102中的元件。导电垫106可设置于基底100的周边区域上。如图1A的剖面图所示，导电垫106可形成于基底100的表面100a上所形成的介电层104之中。此外，基底100中可形成有多个由基底100的表面100b朝表面100a延伸的孔洞108。这些孔洞108可分别露出其下对应的导电垫106。
如图1A所示，可于基底100的表面100b上形成绝缘层110，其可延伸于孔洞108的侧壁上。多个线路层112可形成于绝缘层110之上，并分别延伸进入对应的孔洞108之中而电性接触对应的导电垫106。这些线路层112还可电性连接穿过保护层114的导电凸块116。
然而，随着晶片10中元件区102中的元件越来越密集，所需的导电垫106的数量也随之增加。此外，随着晶片10的尺寸的缩小化，每一导电垫106的面积亦随之缩小，所形成露出导电垫106的孔洞108也需随之缩小。因此，本案发明人认为，当孔洞108缩小至一定程度时，将面临图案化制程上的困难。此外，由于孔洞108的深宽比的提高，于孔洞108中形成材料层(例如，绝缘层110及导电层112)亦会更为困难。
图6显示本案发明人所知的一晶圆的俯视图。如图6所示，为了使沿着基底200(例如，晶圆)的预定切割道SC的切割制程可准确且顺利地进行，可于基底200的位于预定切割道SC的部分形成对准标记602。对准标记602可为形成于基底200中的孔洞或开口。由于对准标记602形成于预定切割道SC之中，对准标记602不会受到晶粒区中的材料层覆盖，且其位置亦不因材料层的堆叠而偏移。因此，基于对准标记602的标示，切割制程可准确地进行，可避免切割刀伤害晶粒区。
然而，在一些实施例中，需于预定切割道SC形成贯穿基底200或贯穿基底200及其下介电层的凹陷，其导致原先形成于预定切割道SC的对准标记602随着基底200的移除而消失，使后续的切割制程难以对准。
因此，为了解决及/或改善上述可能将发生的问题，发明人提出改良的晶片封装技术。以下，将配合图式说明本发明实施例以介绍本发明的晶片封装技术。
图2A-2B显示根据本发明一实施例的晶片封装体的制程俯视图。图3A-3F显示相应于图2A-2B实施例的制程剖面图。图4A-4C显示相应于图2A-2B实施例的制程立体图。图5A-5B显示根据本发明一实施例的晶片封装体的制程俯视图，用以说明本发明实施例的对准标记的形成。在图2A-图5B的实施例中，相同或相似的标号将用以标示相同或相似的元件。
在一实施例中，晶片封装体的制程包括了前段晶片(晶圆)制程及后段封装制程。通过例如是沉积、蚀刻、显影等前段(front end)半导体制程，可以在晶圆上完成各种形式的集成电路的制作。之后，可对此完成集成电路制作的晶圆进行后段晶圆级封装制程，再进行后续切割步骤以完成多个彼此分离的晶片尺寸的封装体。
如图3A所示，在一实施例中，首先在前段晶片制程中，提供基底200，其具有表面200a及表面200b。基底200例如为半导体基底。在一实施例中，基底200为半导体晶圆(例如是硅晶圆)。基底200可由多个预定切割道SC划分成多个晶粒区域(die regions)。
基底200中可形成有或设置有多个元件区202。在一实施例中，基底200的由预定切割道SC所划分的多个晶粒区域中，皆分别具有至少一元件区202及分别且对应围绕每一元件区202的多个周边区。元件区202可包括各种包含有源元件或无源元件、数字电路或模拟电路等集成电路的电子元件，例如是光电元件、微机电***、微流体***、利用热、光线及压力等物理量变化来测量的物理感测器、或功率金属氧化物半导体场效应晶体管模组等。在图2A-2B实施例中，元件区202可包括光电元件，例如是影像感测元件或发光元件。
如图2A所示，基底200的表面上可形成有至少一介电层以作为绝缘披覆用途，例如其包括介电层204a及介电层204。介电层204与基底200之间可形成有多个导电垫206。这些导电垫206可例如设置于基底200的周边区上，并于周边区上沿着邻近预定切割道SC的位置排列。导电垫206可通过内连线结构(未显示)而电性连接元件区202中的元件。在一实施例中，每一导电垫206可包括形成于介电层204中的多个导电层的堆叠。这些堆叠的导电层可例如通过金属内连线结构(未显示)而彼此电性连接。
在一实施例中，导电垫206于前段晶片制程中形成于介电层204内的既有导电垫，其与切割道SC边缘可相隔一既定距离。亦即，在本例中，不需额外形成延伸至预定切割道SC边缘或之上的延伸导电垫。由于导电垫206皆不延伸进入预定切割道SC，因此可避免接触预定切割道SC上所设置的测试结构。
在一实施例中，介电层204中还可形成有多个连续的密封环结构207或多个不连续的密封环结构207，其可分别设置于基底200的晶粒区域的***上(或周边区的***)，并围绕内部的部分的周边区与元件区202。在一实施例中，密封环结构207可与导电垫206同时定义形成。因此，密封环结构207可与导电垫206为大抵相同的导电结构。此外，密封环结构207可设置于导电垫206的***或介于两相邻导电垫206与切割道SC边缘所围绕的区域中。因此，当后续沿着预定切割道进行切割制程时，密封环结构207可保护晶粒内部免受切割制程所造成的应力自切割道传入而破坏所围绕的元件或电路结构。
在完成前段晶片制程后，接续可对已形成有集成电路的晶圆进行后段封装制程。对于光学晶片而言，可选择性先行设置若干辅助光学元件。如图3A所示，在一实施例中，可于这些元件区202上分别设置微透镜205。微透镜205可包括微透镜阵列。微透镜205可用以辅助光线传入元件区202之中或将来自元件区202所发出的光线导出。在一实施例中，可选择性于微透镜205上设置彩色滤光片(未显示)。彩色滤光片例如可设置于微透镜205与元件区202之间。
接着，可选择性于基底200的表面200a上设置盖层220。盖层220可为一基底，如玻璃基底、石英基底、透明高分子基底、或前述的组合。在一实施例中，可于盖层220与基底200之间设置间隔层218。间隔层218可选择性设置为部分或完全覆盖导电垫206，进而可横跨于预定切割道SC上。间隔层218的材质例如为可感光的高分子材料，并可通过曝光显影步骤定义形成。间隔层218、盖层220及基底200可于元件区202上定义出大抵密闭的空腔222。空腔222可容纳微透镜205。在一实施例中，可先将间隔层218形成于盖层220之上，接着接合于基底200上的介电层204之上。在一实施例中，间隔层218于曝光显影后仍具有粘性而可直接接合于基底200之上。在一实施例中，在将间隔层218接合至基底200之后，可对间隔层218进行固化制程，例如可对间隔层218加热。或者，可通过粘着胶(未显示)将间隔层218接合于基底200之上。在另一实施例中，亦可先将间隔层218形成于基底200之上，接着接合间隔层218与盖层220。
接着，可选择性薄化基底200。例如，可以盖层220为支撑基底，并自基底200的表面200b进行薄化制程以将基底200薄化至适当厚度。适合的薄化制程例如包括机械研磨制程、化学机械研磨制程、蚀刻制程、或前述的组合。
接着，如图3B所示，可例如通过微影及蚀刻制程移除部分的基底200以形成自基底200的表面200b朝表面200a延伸的多个开口208。接着，还可进一步移除部分的介电层204a而露出导电垫206。开口208可朝对应的预定切割道SC延伸，并超出对应的导电垫206。在一实施例中，开口208可分别露出对应的导电垫206及密封环结构207。
在一实施例中，可选择性例如通过微影及蚀刻制程移除部分的基底200以形成自基底200的表面200b朝表面200a延伸的多个凹陷208’(其例如为沟槽)。凹陷208’可位于预定切割道SC中。或者，凹陷208’可与预定切割道SC重叠。在一实施例中，凹陷208’可与上述开口208相连通。在一实施例中，开口208与凹陷208’可于相同的图案化制程中形成。
图2A及图4A分别显示相应于图3B的结构的俯视图及立体图。如图2A及图4A所示，在一实施例中，这些开口208分别由对应的导电垫206延伸进入对应的预定切割道SC之中而与所形成的凹陷208’相连通，并可进一步朝预定切割道SC另一侧的导电垫206延伸以露出另一侧的导电垫206。即，开口208可横跨预定切割道SC而与凹陷208’相连通，并延伸至另一晶粒区域中的导电垫206以露出相邻两晶粒区域的导电垫206。在一实施例中，开口208的一宽度小于或等于导电垫206的宽度。由于开口208自导电垫206延伸进入预定切割道SC而与凹陷208’连通，且延伸至另一侧的导电垫206，开口(包含开口208及凹陷208’)的深宽比可因而降低，有助于后续将形成于开口中沉积各种材料层。
如图5A所示，在一实施例中，可选择性例如通过微影及蚀刻制程移除部分的基底200以形成自基底200的表面200b朝表面200a延伸的多个对准标记502。对准标记502可为形成于基底200中的孔洞或开口。对准标记502的开口形状可为圆形、矩形、多边形、椭圆形、或其他适合的形状。
对准标记502有别于图6所示的对准标记602。对准标记502不设置于预定切割道SC之中，而是位于晶粒区中的边缘角落区域。因此，即使如图2A、图3B及图4A所示，预定切割道SC上的基底200已被移除而形成凹陷208’，对准标记502仍可保留，如图5A所示。此外，虽然图5A于交叉的预定切割道SC附近设置了四个对准标记502，但本发明实施例不限于此。在其他实施例中，于交叉的预定切割道SC附近可仅设置三个或更少的对准标记502。举凡可辅助后续切割制程顺利进行的对准标记502设置方式，皆在本发明实施例涵盖范围之内。
在一实施例中，对准标记502可于形成了开口208及凹陷208’之后才形成。在另一实施例中，对准标记502可与开口208及凹陷208’于相同的图案化制程(例如，微影制程及蚀刻制程)中同时形成。在一实施例中，对准标记502的口径小于开口208。在此情形下，对准标记502的深度会小于开口208的深度或凹陷208’的深度。例如，开口208可贯穿基底200而露出正下方的导电垫206。对准标记502则可不贯穿基底200而具有较浅的深度。此外，在一实施例中，对准标记502的正下方不具有导电垫206。一般而言，对准标记502可设置于晶粒区的四个角落。在一实施例中，对准标记502可彼此对称。例如，预定切割道SC的中心线可为对准标记502的对称中心线。即，预定切割道SC的其中之一为晶粒区的两相邻晶粒区中的两相邻的对准标记502的对称中心线。
接着，如图3C所示，可于基底200的表面200b上形成绝缘层210，其可延伸至开口208之内。绝缘层210可例如包括氧化物、氮化物、氮氧化物、高分子材料、或前述的组合。绝缘层210可通过化学气相沉积制程、物理气相沉积制程、热氧化制程、或涂布制程而形成。接着，可通过微影及蚀刻制程移除开口208底部上的部分的绝缘层210而露出导电垫206。在另一实施例中，绝缘层210采用光阻材料。因此，可对绝缘层210进行曝光及显影制程而将绝缘层210图案化以露出导电垫206。在一实施例中，绝缘层210较佳仍完全覆盖密封环结构207以避免后续形成的线路层接触密封环结构207而造成短路。
在一实施例中，可不于对准标记502之中形成任何的绝缘层。例如，在形成绝缘层210的过程中，绝缘材料可能会沉积于对准标记502的侧壁及/或底部上。接着，可于绝缘层210的图案化制程中，亦移除对准标记502之中的绝缘材料。
如图3D所示，接着于基底200的表面200b上的绝缘层210之上形成多个线路层212。每一线路层212可自基底200的表面200b延伸进入对应的开口208而电性接触对应的导电垫206。线路层212的材质可为导电材料，例如是金属材料或其他适合的导电材料。在一实施例中，线路层212的材质可例如是铜、铝、金、铂、或前述的组合。线路层212的形成方法可包括物理气相沉积、化学气相沉积、涂布、电镀、无电镀、或前述的组合。
在一实施例中，可先于基底200的表面200b上的绝缘层210之上形成导电层，接着通过微影及蚀刻制程将导电层图案化为多个线路层212。在另一实施例中，可先于基底200的表面200b上的绝缘层210之上形成晶种层(未显示)。接着，可于晶种层上形成图案化遮罩层(未显示)。图案化遮罩层可具有多个露出部分晶种层的开口。接着，可通过电镀制程于图案化遮罩层的开口所露出的晶种层上电镀导电材料。接着，可移除图案化遮罩层，并可通过蚀刻制程移除原由图案化遮罩层所覆盖的晶种层以完成线路层212的制作。
图4B显示对应于图3D的结构的立体图。如图3D与图4B所示，多个线路层212自基底200的表面200b上的绝缘层210之上分别延伸进入对应的开口208而电性接触对应的开口208下方的对应的导电垫206。在一实施例中，每一线路层212皆不延伸进入预定切割道SC之中或是与预定切割道SC相隔有一距离。如此，在后续沿着这些预定切割道SC进行切割制程时，切割刀片将不会碰触到线路层212而造成线路层212受损或脱层。此外，线路层212与密封环结构207之间隔有绝缘层210线路层212与密封环结构207之间隔有绝缘层210，因而这些线路层212彼此之间不会发生短路。在此实施例中，由于开口208横跨预定切割道SC并与沟槽208’连通而具有较大的口径，因此于开口208中形成绝缘层及/或线路层将更为容易。
相似地，在一实施例中，可不于对准标记502之中形成任何的线路层。例如，在形成线路层212的过程中，导电材料可能会沉积于对准标记502的侧壁及/或底部上。接着，可于线路层212的图案化制程中，亦移除对准标记502之中的导电材料。因此，在一实施例中，对准标记502之中可不包含金属材料。
接着，如图3E所示，于基底200的表面200b上形成保护层214。保护层214可包括防焊材料、绿漆、聚酰亚胺(polyimide)、或其他适合的绝缘材料。保护层214可例如通过涂布制程或喷涂制程而形成。保护层214可覆盖基底200、线路层212、开口208及凹陷208’。接着，可将保护层214图案化使的具有露出部分线路层212的开口。在一实施例中，亦可通过保护层214的图案化制程而使保护层214不延伸进入预定切割道SC中(未显示)。在一实施例中，保护层214可不覆盖对准标记502。在另一实施例中，由于保护层214的厚度不会太厚，因此保护层214可覆盖对准标记502。在此情形下，观察者仍可辨识保护层214下方的对准标记502。在一实施例中，保护层214可部分填充对准标记502。在另一实施例中，保护层214完全不填入对准标记502。
接着，可于露出的线路层212上形成导电凸块216，其例如可为焊球。在一实施例中，可先于露出的线路层212上形成凸块下金属层(未显示)以利导电凸块216的形成。
接着，通过对准标记502的辅助，可精准地沿着预定切割道SC进行切割制程以形成彼此分离的多个晶片封装体。图3F显示其中一晶片封装体的剖面图，而图2B及图4C分别显示相应于图3F的结构的俯视图及立体图。在切割制程之后，开口208的一部分成为晶片封装体的基底的侧面200c上的开口208c，如图2B或4C所示。
在一实施例中，开口208c露出对应的导电垫206，且沿着与基底200的侧面200c交叉的一方向朝基底200的侧面200c延伸而超出导电垫206的范围。在一实施例中，开口208c延伸至基底200的侧面200c，如图4C所示。
图5B显示晶片封装体的俯视图，用以说明对准标记502的位置。为了清楚显示对准标记502，开口208c及其中的绝缘层210与线路层212不显示于图5B之中。如图5B所示，用于对准的对准标记502可位于晶片封装体的基底200的边缘角落区域。一般而言，对准标记502可形成于基底200之中，且位于晶片封装体的基底200的四个边缘角落区域。然而，本发明实施例不限于此。在其他实施例中，对准标记502可仅位于晶片封装体的基底200的二个、三个、或单个边缘角落区域。在一实施例中，晶片封装体具有多个对准标记502，且这些可彼此对称。例如，晶片封装体的基底200的中心点可为这些对准标记502的对称中心。即，这些对准标记502以基底200的一中心点而彼此对称。在一实施例中，晶片封装体的基底200的一侧边附近的两个对准标记502的连线可大抵平行于晶片封装体的基底200的该侧边。
有别于一般晶片中于前段晶片制程所形成的对准标记，其由基底200的表面200a朝表面200b延伸，本发明实施例的对准标记502由于是在后段封装制程中形成，对准标记502由基底200的表面200b朝表面200a延伸。在一实施例中，对准标记502中不具有绝缘材料或金属材料。此外，对准标记502的正下方可不具有导电垫206。再者，保护层214可覆盖对准标记502。在另一实施例中，可通过图案化制程使保护层214不覆盖对准标记502，如图7所示。
本发明实施例所述的对准标记502除了可应用于上述实施例之外，还可应用于如图1A-1B所示的情形(TSV)，端视需求而定。
本发明实施例所述的封装技术可有效减轻在晶片封装体中形成电性连接至导电垫的线路的制程难度。本发明实施例是采用晶圆级封装。通过于晶粒区设置对准标记，可确保后续的切割制程可准确且顺利地进行。再者，随着晶圆中晶粒的密度的提升，预定切割道的预留宽度可能随之缩小。在此情形下，采用本发明实施例所述的对准标记为辅助而进行的晶圆级切割制程可更为准确，可确保所形成的晶片封装体的可靠度与品质。
以上所述仅为本发明较佳实施例，然其并非用以限定本发明的范围，任何熟悉本项技术的人员，在不脱离本发明的精神和范围内，可在此基础上做进一步的改进和变化，因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。

Claims (20)

1.一种晶片封装体，其特征在于，包括：
一半导体基底，具有一第一表面及相反的一第二表面；
一元件区，设置于该半导体基底之中；
一介电层，位于该半导体基底的该第一表面上；
多个导电垫，位于该介电层中，且电性连接该元件区；
多个开口，自该半导体基底的该第二表面朝该第一表面延伸，且分别露出对应的所述导电垫，且朝向该半导体基底的一侧面延伸而分别超出对应的所述导电垫；以及
至少一对准标记，设置于该半导体基底之中，且自该第二表面朝该第一表面延伸。
2.根据权利要求1所述的晶片封装体，其特征在于，该至少一对准标记位于该半导体基底的一边缘角落区域。
3.根据权利要求1所述的晶片封装体，其特征在于，还包括：
多个线路层，位于该半导体基底的该第二表面上，且分别且对应地延伸进入所述开口而电性接触所述导电垫；以及
一绝缘层，设置于该半导体基底与所述线路层之间。
4.根据权利要求3所述的晶片封装体，其特征在于，所述开口分别连通该半导体基底的该侧面。
5.根据权利要求3所述的晶片封装体，其特征在于，该至少一对准标记之中不具有所述线路层及该绝缘层。
6.根据权利要求3所述的晶片封装体，其特征在于，该至少一对准标记的深度小于所述开口的深度。
7.根据权利要求1所述的晶片封装体，其特征在于，还包括一保护层，该保护层覆盖该半导体基底，其中该保护层覆盖该至少一对准标记。
8.根据权利要求7所述的晶片封装体，其特征在于，该保护层部分填充该至少一对准标记。
9.根据权利要求1所述的晶片封装体，其特征在于，还包括一保护层，该保护层覆盖该半导体基底，其中该保护层不覆盖该至少一对准标记。
10.根据权利要求1所述的晶片封装体，其特征在于，该至少一对准标记为多个对准标记。
11.根据权利要求10所述的晶片封装体，其特征在于，该半导体基底的一侧边附近的至少两个所述对准标记的连线平行于该半导体基底的该侧边。
12.根据权利要求10所述的晶片封装体，其特征在于，所述对准标记以该半导体基底的一中心点而彼此对称。
13.根据权利要求1所述的晶片封装体，其特征在于，至少一对准标记的正下方不具有任何的导电垫。
14.一种晶片封装体的形成方法，其特征在于，包括：
提供一基底，该基底由多个预定切割道划分成多个晶粒区域，每一晶粒区域中形成有至少一元件区，其中一介电层形成于该基底的一第一表面上，且多个导电垫形成于该介电层之中，所述导电垫沿着所述预定切割道排列；
自该基底的一第二表面部分移除该基底以形成朝该第一表面延伸的多个对准标记，其中该基底的每一所述晶粒区形成有至少一所述对准标记；
自该基底的该第二表面部分移除该基底以于该基底之中形成朝该第一表面延伸的多个开口，其中所述开口分别对应地露出所述导电垫，且分别由对应的所述导电垫朝对应的所述预定切割道延伸，并超出对应的所述导电垫；
于该基底的该第二表面上形成一绝缘层，该绝缘层延伸进入所述开口之中而覆盖所述导电垫；
于该绝缘层上形成多个线路层，其中各所述线路层电性接触对应的所述导电垫；以及
通过所述对准标记的辅助，沿着所述预定切割道进行一切割制程以形成彼此分离的多个晶片封装体。
15.根据权利要求14所述的晶片封装体的形成方法，其特征在于，还包括：
在形成所述线路层之前，部分移除该绝缘层而露出所述导电垫，其中在形成所述线路层之后，各所述线路层延伸进入对应的所述开口中而电性接触对应的所述导电垫。
16.根据权利要求15所述的晶片封装体的形成方法，其特征在于，还包括自该基底的该第二表面部分移除该基底以于该基底之中形成朝该第一表面延伸的多个凹陷，其中所述凹陷位于所述预定切割道之中，且与所述开口连通。
17.根据权利要求16所述的晶片封装体的形成方法，其特征在于，所述对准标记、所述开口及所述凹陷于一相同的图案化制程中同时形成。
18.根据权利要求14所述的晶片封装体的形成方法，其特征在于，还包括于该基底及所述线路层上形成一保护层，其中该保护层覆盖所述对准标记。
19.根据权利要求14所述的晶片封装体的形成方法，其特征在于，还包括于该基底及所述线路层上形成一保护层，其中该保护层不覆盖所述对准标记。
20.根据权利要求14所述的晶片封装体的形成方法，其特征在于，所述预定切割道的其中之一为所述晶粒区的两相邻晶粒区中的两相邻的所述对准标记的对称中心线。
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