CN104952812A - 晶片封装体及其制造方法 - Google Patents

晶片封装体及其制造方法 Download PDF

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Publication number
CN104952812A
CN104952812A CN201510139996.9A CN201510139996A CN104952812A CN 104952812 A CN104952812 A CN 104952812A CN 201510139996 A CN201510139996 A CN 201510139996A CN 104952812 A CN104952812 A CN 104952812A
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CN
China
Prior art keywords
substrate
opening
wafer encapsulation
adhesion coating
manufacture method
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Pending
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CN201510139996.9A
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English (en)
Inventor
沈佳伦
张义民
刘沧宇
何彦仕
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XinTec Inc
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XinTec Inc
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Publication of CN104952812A publication Critical patent/CN104952812A/zh
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Abstract

本发明提供一种晶片封装体及其制造方法，该晶片封装体的制造方法包括：提供一第一基底及一第二基底；通过一粘着层将第一基底贴附于第二基底上；以及形成多个第一开口，该多个第一开口穿过第一基底及粘着层，且将第一基底及粘着层分离为多个部分。本发明可避免晶片的边缘侧壁形成突出部而造成破裂，因此可提升晶片封装体的可靠度。

Description

晶片封装体及其制造方法
技术领域
本发明有关于一种晶片封装技术，特别为有关于一种晶片封装体及其制造方法。
背景技术
一般而言，晶片封装体的制作过程包括将晶圆贴附于胶带上，且通过切割制程将晶圆分离成多个晶片，接着将晶片与胶带分离，以进行后续制程。
然而，在传统制程中，多次切割制程会造成切割刀的刀口磨损，使得切割出的晶片的边缘侧壁邻近于胶带处易有残留部分，而在晶片的边缘侧壁形成突出部。在后续制程及使用晶片封装体的过程中，上述突出部造成晶片的边缘侧壁易产生破裂，进而降低晶片封装体的可靠度或品质。
因此，有必要寻求一种新颖的晶片封装体及其制造方法，其能够解决或改善上述的问题。
发明内容
本发明提供一种晶片封装体的制造方法，包括：提供一第一基底及一第二基底；通过一粘着层将第一基底贴附于第二基底上；以及形成多个第一开口，多个第一开口穿过第一基底及粘着层，且将第一基底及粘着层分离为多个部分。
本发明还提供一种晶片封装体，包括：一第一基底，第一基底内具有一导电垫；以及一粘着层，位于第一基底上，其中一阶梯状侧壁位于该导电垫外侧，且阶梯状侧壁的一部分与第一基底的一侧壁共平面。
本发明可避免晶片的边缘侧壁形成突出部而造成破裂，因此可提升晶片封装体的可靠度。
附图说明
图1A至1D是绘示出根据本发明一实施例的晶片封装体的制造方法的剖面示意图。
图2至4是绘示出根据本发明各种实施例的晶片封装体的剖面示意图。
图5A至5D是绘示出根据本发明另一实施例的晶片封装体的制造方法的剖面示意图。
图6A至6E是绘示出根据本发明又另一实施例的晶片封装体的制造方法的剖面示意图。
图7是绘示出根据本发明其他实施例的晶片封装体的剖面示意图。
其中，附图中符号的简单说明如下：
100 第一基底；
120、320 导电垫；
140 粘着层；
160 第二基底；
180 缺口；
200 第一开口；
210 顶针；
220 第二开口；
220a 上部；
220b 下部；
240 第三开口；
260 晶片；
300 电路板；
340 重布线层；
360 焊线；
L 切割道。
具体实施方式
以下将详细说明本发明实施例的制作与使用方式。然应注意的是，本发明提供许多可供应用的发明概念，其可以多种特定型式实施。文中所举例讨论的特定实施例仅为制造与使用本发明的特定方式，非用以限制本发明的范围。此外，在不同实施例中可能使用重复的标号或标示。这些重复仅为了简单清楚地叙述本发明，不代表所讨论的不同实施例及/或结构之间具有任何关连性。再者，当述及一第一材料层位于一第二材料层上或之上时，包括第一材料层与第二材料层直接接触或间隔有一或更多其他材料层的情形。
本发明一实施例的晶片封装体可用以封装微机电***晶片。然其应用不限于此，例如在本发明的晶片封装体的实施例中，其可应用于各种包含有源元件或无源元件(active or passive elements)、数字电路或模拟电路(digital oranalog circuits)等集成电路的电子元件(electronic components)，例如是有关于光电元件(opto electronic devices)、微机电***(Micro Electro MechanicalSystem，MEMS)、生物辨识元件(biometric device)、微流体***(micro fluidicsystems)、或利用热、光线、电容及压力等物理量变化来测量的物理感测器(Physical Sensor)。特别是可选择使用晶圆级封装(wafer scale package，WSP)制程对影像感测元件、发光二极管(light-emitting diodes，LEDs)、太阳能电池(solar cells)、射频元件(RF circuits)、加速计(accelerators)、陀螺仪(gyroscopes)、指纹辨识器(fingerprint recognition device)、微制动器(microactuators)、表面声波元件(surface acoustic wave devices)、压力感测器(processsensors)或喷墨头(ink printer heads)等半导体晶片进行封装。
其中上述晶圆级封装制程主要是指在晶圆阶段完成封装步骤后，再予以切割成独立的封装体，然而，在一特定实施例中，例如将已分离的半导体晶片重新分布在一承载晶圆上，再进行封装制程，亦可称之为晶圆级封装制程。另外，上述晶圆级封装制程亦适用于通过堆叠(stack)方式安排具有集成电路的多片晶圆，以形成多层集成电路(multi-layer integrated circuit devices)的晶片封装体。
以下配合图1A至1D说明本发明一实施例的晶片封装体的制造方法，其中图1A至1D绘示出根据本发明一实施例的晶片封装体的制造方法的剖面示意图。
请参照图1A，提供一第一基底100。在一实施例中，第一基底100可为一硅基底或其他半导体基底。在另一实施例中，第一基底100为一硅晶圆，以利于进行晶圆级封装制程。以下第一基底100以硅晶圆作为范例说明。
在本实施例中，第一基底100内具有多个导电垫，对应设置于第一基底100的各个晶片区(未绘示)中，其可邻近于第一基底100的上表面。为简化图式，此处仅绘示出位于第一基底100的单一晶片区中的两个导电垫120。
在一实施例中，导电垫120可为单层导电层或具有多层的导电层结构。此处，仅以单层导电层作为范例说明。
在本实施例中，第一基底100可具有感测装置(未绘示)位于其上表面上。在一实施例中，上述感测装置可通过内连线结构(未绘示)而与导电垫120电性连接，且可包括环境感测元件(例如，温度感测元件、湿度感测元件或压力感测元件)、生物特征感测元件(例如，指纹辨识元件)、影像感测元件或其他适合的感测元件。
可通过一粘着层140将第一基底100贴附于一第二基底160上。在本实施例中，粘着层140可包括胶带(tape)、粘晶层(die attach film，DAF)或其他适合的粘着材料。再者，粘着层140的厚度可为5至20μm的范围。在本实施例中，第二基底160作为暂时性的承载基底/晶圆，且可包括硅、玻璃或其他适合的支撑结构。再者，第二基底160的厚度可大于100μm。
请参照图1B，可通过切割制程，形成第一开口200，其穿过第一基底100及粘着层140，且将第一基底100及粘着层140分离为多个部分。举例来说，可利用第二基底160作为支撑，且沿着用以定义第一基底100的晶片区的切割道L切割第一基底100及粘着层140，以形成第一开口200。在一实施例中，第一开口200延伸至第二基底160内。在另一实施例中，第一开口200可未延伸至第二基底160内，而仅暴露出第二基底160的表面。
请参照图1C，可通过切割制程，形成对应第一开口200的第二开口220，其穿过第一基底100且其底部位于粘着层140内。在本实施例中，第一开口200与对应的第二开口220上下重叠，且第二开口220的直径大于第一开口200的直径，使得粘着层140内的第一开口200与对应的第二开口220构成具有阶梯状侧壁的开口。
在图1A至1C的实施例中，在形成深度较大的第一开口200之后，才形成深度较小的第二开口220，使得第一开口200对准于第二基底160，而后续形成的第二开口220仅需对准于第一开口200。因此，先形成深度较大的第一开口200之后，再形成深度较小的第二开口220，能够有利于提升切割第一基底100及粘着层140的精准度。在其他的实施例中，也可先形成深度较小的第二开口220，再形成深度较大的第一开口200，此时，后续形成的第一开口200需同时对准于第二基底160及第二开口220。
请参照图1D，在形成第一开口200及第二开口220之后，将包括第一基底100及粘着层140的分离部分与第二基底160分离。接着，可通过上述分离部分的粘着层140，将分离的第一基底100(例如，晶片)贴附至一电路板300上。在一实施例中，粘着层140为升温后可产生粘性的材料，因此在将第一基底100与第二基底160分离之后，可通过粘着层140，直接将分离的第一基底100贴附至电路板300上，而无需额外使用粘着胶。在另一实施例中，也可先将第一基底100与粘着层140分离，再通过额外的粘着胶将分离的第一基底100(例如，晶片)贴附至电路板300上。
在本实施例中，电路板300内具有多个导电垫320，其可邻近于电路板300的上表面。在一实施例中，导电垫320可为单层导电层或具有多层的导电层结构。此处，仅以单层导电层作为范例说明。
接着，可通过沉积制程(例如，涂布制程、物理气相沉积制程、化学气相沉积制程、电镀制程、无电镀制程或其他适合的制程)、微影制程及蚀刻制程，在第一基底100的上表面上形成图案化的重布线层(redistribution layer，RDL)340，以电性连接导电垫120。重布线层340沿着第一基底100的侧壁延伸至粘着层140的阶梯状侧壁上，并进一步延伸至电路板300上，以电性连接电路板300内对应的导电垫320。在一实施例中，重布线层340可包括铜、铝、金、铂、镍、锡、前述的组合或其他适合的导电材料。在另一实施例中，重布线层340可包括导电高分子材料或导电陶瓷材料(例如，氧化铟锡或氧化铟锌)。为了简化图式，此处未绘示出第一基底100的上表面及侧壁与重布线层340之间用于电性隔离的绝缘层，亦省略其说明。
在另一实施例中，如图2所示，与导电垫120电性连接的重布线层340仅延伸至粘着层140的阶梯状侧壁上。接着，可通过打线接合(wire bonding)制程，在阶梯状侧壁上的重布线层340上形成一焊线360，并延伸至电路板300上，以电性连接电路板300内对应的导电垫320。
又另一实施例中，如图3所示，可仅通过焊线360，将第一基底100内的导电垫120电性连接至电路板300内对应的导电垫320。
在其他实施例中，如图4所示，可在进行图1A至1B的步骤之后，将包括第一基底100及粘着层140的分离部分与第二基底160分离，并通过粘着层140，将分离的第一基底100贴附至电路板300上。接着，通过适合的导电结构(例如，焊线360)，将第一基底100内的导电垫120电性连接至电路板300内对应的导电垫320。或者，可通过重布线层340(如图1D所示)，将第一基底100内的导电垫120电性连接至电路板300内对应的导电垫320。
以下配合图5A至5D说明本发明另一实施例的晶片封装体的制造方法，其中图5A至5D是绘示出根据本发明另一实施例的晶片封装体的制造方法的剖面示意图，且其中相同于图1A至1D中的部件使用相同的标号并省略其说明。
请参照图5A，可通过相同于图1A的步骤，利用过粘着层140将第一基底100贴附于第二基底160上。接着，可通过蚀刻制程(例如，干蚀刻制程)，在第一基底100内形成对准于切割道L的第三开口240。第三开口240的底部位于第一基底100内。
请参照图5B，可通过类似于图1B的步骤，进行切割制程，形成对应第三开口240的第一开口200。第一开口200穿过第一基底100及粘着层140，且将第一基底100及粘着层140分离为多个部分。
在本实施例中，第一开口200与对应的第三开口240上下重叠，且第三开口240的直径大于第一开口200的直径，使得第一开口200及对应的第三开口240构成具有阶梯状侧壁的开口。
请参照图5C，可通过类似于图1C的步骤，进行切割制程，形成对应第一开口200及第三开口240的第二开口220。第二开口220穿过第一基底100且其底部位于粘着层140内。
在本实施例中，第二开口220与对应的第一开口200及第三开口240互相上下重叠，第二开口220的直径大于第一开口200的直径且小于第三开口240的直径，使得第一基底100内的第二开口220与对应的第三开口240构成具有阶梯状侧壁的开口，且粘着层140内的第二开口220与对应的第一开口200亦构成具有阶梯状侧壁的开口。再者，第一开口200与对应的第二开口220及第三开口240构成具有多阶梯状侧壁的开口。
同样地，在图5A至5C的实施例中，在形成深度较大的第一开口200之后，才形成深度较小的第二开口220，有利于提升切割第一基底100及粘着层140的精准度。在其他的实施例中，也可先形成深度较小的第二开口220，再形成深度较大的第一开口200。
请参照图5D，在形成第一开口200、第二开口220及第三开口240之后，将包括第一基底100及粘着层140的分离部分与第二基底160分离。接着，可通过上述分离部分的粘着层140，直接将分离的第一基底100(例如，晶片)贴附至电路板300上。在另一实施例中，也可先将第一基底100与粘着层140分离，再通过额外的粘着胶将分离的第一基底100贴附至电路板300上。
接着，可通过打线接合制程，在第一基底100内的导电垫120上形成焊线360，延伸至电路板300上，以电性连接电路板300内对应的导电垫320。
在另一实施例中，可通过沉积制程、微影制程及蚀刻制程，在第一基底100的上表面上形成图案化的重布线层，以电性连接导电垫120。重布线层340沿着第一基底100及粘着层140的多阶梯状侧壁延伸至电路板300上，以电性连接电路板300内对应的导电垫320。在其他实施例中，与导电垫120电性连接的重布线层可仅延伸至第一基底100及粘着层140的多阶梯状侧壁上，且通过焊线，将重布线层电性连接至电路板300内对应的导电垫320。
以下配合图6A至6E说明本发明又另一实施例的晶片封装体的制造方法，其中图6A至6E是绘示出根据本发明又另一实施例的晶片封装体的制造方法的剖面示意图，且其中相同于图1A至1D及图5A至5D中的部件使用相同的标号并省略其说明。
请参照图6A，可通过粘着层140将第一基底100贴附于第二基底160上。在本实施例中，第二基底160包括玻璃、氮化铝、蓝宝石或其他适合的基底材料。在一实施例中，第二基底160也可选择性地作为暂时的承载基底/晶圆。
请参照图6B，可使用刀轮(cutting wheel)或其他适合的刻痕装置，沿着用以定义晶片区的切割道L，自第二基底160远离粘着层140及第一基底100的表面形成多个缺口180，使得第二基底160内预先形成对应于切割道L的裂痕，进而有利于后续将第二基底160分离。换句话说，从俯视方向来看，缺口180沿着切割道L环绕晶片区。在其他实施例中，也可采用激光切割(laser cut)装置在第二基底160内形成缺口180。
请参照图6C，可通过切割制程，形成穿过第一基底100及粘着层140的第一开口200，因而将第一基底100及粘着层140分离为对应晶片区的多个部分。举例来说，可在第二基底160具有缺口180的表面下方设置切割胶带(未绘示)，然后利用刀具沿着切割道L切割第一基底100及粘着层140，以形成第一开口200。亦即，从俯视方向来看，第一开口200是沿着切割道L环绕晶片区。在其他实施例中，也可采用激光切割技术形成第一开口200。
在本实施例中，第一开口200对准于缺口180，且与缺口180间隔一距离，而并未与缺口180互相连通。在本实施例中，缺口180的深度远小于第二基底160的厚度，而第一开口200的深度至少等于或大于第一基底100的厚度。在一实施例中，第一开口200自粘着层140延伸至第二基底160内。在另一实施例中，第一开口200可未延伸至第二基底160内，而仅暴露出第二基底160的表面。在其他实施例中，第一开口200可至少贯穿第一基底100，而选择性延伸至粘着层140内。
请同时参照图6D及6E，可利用顶针(pin)210或其他适合的裂片装置来进行裂片切割(breaking cut)制程，以形成第二开口220，进而将第二基底160也分离为对应晶片区的多个部分，如此一来，切割后的第一基底100、粘着层140及第二基底160构成一晶片260。
举例来说，将顶针210自第一开口200的顶部向下施压而在第一基底100内形成第二开口220(如图6D所示)，然后将顶针210继续沿着第一开口200向下施压直至第二开口220与第二基底160内的缺口180互相连通(如图6E所示)。详细而言，所形成的第二开口220由上部220a及下部220b所构成，上部220a的直径大于下部220b的直径，使得第二开口220包括阶梯状侧壁，直径较大的上部220a穿过第一基底100及粘着层140且延伸至第二基底160内，而直径较小的下部220b邻接于上部220a并将上部220a与缺口180互相连通，因此切割后的第一基底100及粘着层140皆具有平直的侧壁，而切割后的第二基底160则具有阶梯状侧壁。换言之，第二基底160上部的尺寸等于第一基底100及粘着层140的尺寸，而第二基底160下部的尺寸大于第一基底100及粘着层140的尺寸，使得晶片260具有T型的剖面形状。
在本实施例中，第二开口220顶部(例如，上部220a)的直径大于第一开口200的直径，如图6D所示。在一实施例中，第二开口220的下部220b的直径小于缺口180的直径，因而切割后的第二基底160的侧壁可能具有缺口180所造成的缺角，如图6E所示。在另一实施例中，第二开口220与缺口180上下重叠，且第二开口220的下部220b的直径等于缺口180的直径，使得切割后的第二基底160的侧壁不具有缺角。在其他实施例中，第二开口220的下部220b的直径大于缺口180的直径且完全穿过缺口180，使得切割后的第二基底160的侧壁可不具有缺角，如图7所示。
接着，将晶片260与前述切割胶带分离。之后，类似于图2的实施例，可将晶片260接合至一电路板300上，并通过重布线层340及焊线360将晶片260内的导电垫120电性连接至电路板300内对应的导电垫320，如图7所示。重布线层340形成于第二开口220的阶梯状侧壁，且位于上部220a而未延伸至下部220b。在其他实施例中，也可采用第1D或3图的实施例，仅通过重布线层340及焊线360的其中一者，将第一基底100内的导电垫120电性连接至电路板300。
在一实施例中，接合至电路板300的晶片260由第一基底100、粘着层140及第二基底160所构成，如图7所示。然而，在其他实施例中，接合至电路板300的晶片260也可仅由第一基底100及粘着层140所构成，或是仅由第一基底100所构成，其取决于设计需求。在此情况下，晶片260具有平直的侧壁而不包括阶梯状侧壁。
可以理解的是，图式所绘示出的各种开口及缺口的尺寸、轮廓及位置仅作为范例说明，而不限定于此。开口及缺口实际的尺寸、轮廓及位置取决于设计需求。
在传统的晶圆切割制程中，磨损的切割刀使得切割出的晶片的边缘侧壁易形成突出部，而造成晶片的边缘侧壁易破裂。根据本发明的上述实施例，通过粘着层140将第一基底100贴附于用以提供支撑的第二基底160上，且通过切割制程形成穿过第一基底100及粘着层140的第一开口200，使得切割后的第一基底100具有平直的侧壁，以避免晶片的边缘侧壁形成突出部而造成破裂，因此可提升晶片封装体的可靠度。
请参照图1D，其绘示出根据本发明一实施例的晶片封装体的剖面示意图。在本实施例中，晶片封装体包括一第一基底100及一粘着层140。在一实施例中，第一基底100可为一硅基底或其他半导体基底。
在本实施例中，第一基底100内具有多个导电垫120，其可邻近于第一基底100的上表面。在一实施例中，导电垫120可为单层导电层或具有多层的导电层结构。此处，仅以单层导电层作为范例说明。
在本实施例中，第一基底100可具有感测装置(未绘示)位于其上表面上。在一实施例中，上述感测装置可通过内连线结构(未绘示)而与导电垫120电性连接，且可包括环境感测元件(例如，温度感测元件、湿度感测元件或压力感测元件)、生物特征感测元件(例如，指纹辨识元件)、影像感测元件或其他适合的感测元件。
粘着层140位于第一基底100上，且具有阶梯状侧壁，其中阶梯状侧壁位于导电垫120的外侧，阶梯状侧壁的一第一部分与第一基底100的一侧壁共平面，且阶梯状侧壁的一第二部分突出于第一基底100的侧壁。在本实施例中，第一基底100具有平直的侧壁，而粘着层140则具有阶梯状侧壁。换言之，粘着层140上部的尺寸等于第一基底100的尺寸，而粘着层140下部的尺寸大于第一基底100的尺寸，如此一来构成T型的剖面形状。在本实施例中，粘着层140可包括胶带、粘晶层或其他适合的粘着材料。再者，粘着层140的厚度可为5至20μm的范围。
在本实施例中，晶片封装体还包括一电路板300及一重布线层340。电路板300通过粘着层140贴附至第一基底100上。重布线层340设置于第一基底100上，且与第一基底100内的导电垫120电性连接。重布线层340沿着第一基底100的侧壁及粘着层140的阶梯状侧壁延伸至电路板300上，以电性连接电路板300内对应的导电垫320。在一实施例中，重布线层340可包括铜、铝、金、铂、镍、锡、前述的组合或其他适合的导电材料。在另一实施例中，重布线层340可包括导电高分子材料或导电陶瓷材料(例如，氧化铟锡或氧化铟锌)。
请参照图2至4及图5D，其绘示出根据本发明各种实施例的晶片封装体的剖面示意图，其中相同于图1D中的部件使用相同的标号并省略其说明。第2及3图中的晶片封装体的结构类似于图1D中的晶片封装体的结构，且图2与图1D的晶片封装体之间的差异在于图2中的重布线层340仅延伸至粘着层140的阶梯状侧壁上，并通过设置于阶梯状侧壁上且延伸至电路板300上的焊线360，而电性连接至对应的导电垫320。再者，图3与图1D的晶片封装体之间的差异在于图3中的晶片封装体以焊线360取代图1D的重布线层340，来将第一基底100内的导电垫120电性连接至电路板300内对应的导电垫320。
图4中的晶片封装体的结构类似于图3中的晶片封装体的结构，且差异在于图4中的粘着层140具有平直的侧壁，而不具有阶梯状侧壁。再者，图5D中的晶片封装体的结构类似于图3中的晶片封装体的结构，且差异在于图5D中的第一基底100也具有阶梯状侧壁，且粘着层140的阶梯状侧壁突出于第一基底的阶梯状侧壁，使得第一基底100及粘着层140的侧壁构成一多阶梯状侧壁。
再者，请参照图7，其绘示出根据本发明其他实施例的晶片封装体的剖面示意图，其中相同于图1D、2至4及5D中的部件使用相同的标号并省略其说明。图7中的晶片封装体的结构类似于图2中的晶片封装体的结构，且图7与图2的晶片封装体之间的差异在于图2中的粘着层140具有阶梯状侧壁，而图7中的粘着层140与电路板300之间还设置有第二基底160且第二基底160具有阶梯状侧壁，因而重布线层340自第一基底100经由粘着层140而延伸至第二基底160的阶梯状侧壁上。
在图7的实施例中，第二基底160的阶梯状侧壁位于导电垫120的外侧，阶梯状侧壁的一第一部分与第一基底100的一侧壁共平面，且阶梯状侧壁的一第二部分突出于第一基底100的侧壁。再者，第二基底160上部的尺寸等于第一基底100及粘着层140的尺寸，而第二基底160下部的尺寸大于第一基底100及粘着层140的尺寸，使得晶片260具有T型的剖面形状。
在上述实施例中，由于粘着层140或第一基底100具有阶梯状侧壁，使得形成于第一基底100上的重布线层340可延伸至阶梯状侧壁上，且焊线360仅需从阶梯状侧壁延伸至电路板300上，因此可降低焊线360的整体高度，进而缩小晶片封装体的尺寸。
以上所述仅为本发明较佳实施例，然其并非用以限定本发明的范围，任何熟悉本项技术的人员，在不脱离本发明的精神和范围内，可在此基础上做进一步的改进和变化，因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。

Claims (26)

1.一种晶片封装体的制造方法，其特征在于，包括：
提供一第一基底及一第二基底；
通过一粘着层将该第一基底贴附于该第二基底上；以及
形成多个第一开口，该多个第一开口穿过该第一基底及该粘着层，且将该第一基底及该粘着层分离为多个部分。
2.根据权利要求1所述的晶片封装体的制造方法，其特征在于，该粘着层包括胶带或粘晶层。
3.根据权利要求1所述的晶片封装体的制造方法，其特征在于，形成该多个第一开口的步骤包括进行切割制程。
4.根据权利要求1所述的晶片封装体的制造方法，其特征在于，还包括在形成该多个第一开口之后，将包括该第一基底及该粘着层的该多个部分与该第二基底分离。
5.根据权利要求1所述的晶片封装体的制造方法，其特征在于，还包括在形成该多个第一开口之前或之后，形成对应该多个第一开口的多个第二开口，该多个第二开口穿过该第一基底，且该多个第二开口的底部位于该粘着层内。
6.根据权利要求5所述的晶片封装体的制造方法，其特征在于，该粘着层内的该多个第一开口与对应的该多个第二开口构成具有阶梯状侧壁的多个开口。
7.根据权利要求5所述的晶片封装体的制造方法，其特征在于，形成该多个第二开口的步骤包括进行切割制程。
8.根据权利要求5所述的晶片封装体的制造方法，其特征在于，还包括在形成该多个第一开口之前，在该第一基底内形成对应该多个第一开口的多个第三开口，其中该多个第三开口的底部位于该第一基底内。
9.根据权利要求8所述的晶片封装体的制造方法，其特征在于，该第一基底内的该多个第一开口与对应的该多个第三开口构成具有阶梯状侧壁的多个开口。
10.根据权利要求8所述的晶片封装体的制造方法，其特征在于，该多个第一开口与对应的该多个第二开口及该多个第三开口构成具有多阶梯状侧壁的多个开口。
11.根据权利要求8所述的晶片封装体的制造方法，其特征在于，形成该多个第三开口的步骤包括进行蚀刻制程。
12.根据权利要求1所述的晶片封装体的制造方法，其特征在于，还包括在形成该多个第一开口之前，在该第二基底内形成多个缺口，其中该多个第一开口对准于该多个缺口。
13.根据权利要求12所述的晶片封装体的制造方法，其特征在于，该多个第一开口与该多个缺口间隔一距离，而未与该多个缺口连通。
14.根据权利要求12所述的晶片封装体的制造方法，其特征在于，还包括在形成该多个第一开口之后，形成多个第二开口，以将该第二基底分离，其中该多个第二开口沿着该多个第一开口自该第一基底穿过该粘着层，并延伸至该第二基底内。
15.根据权利要求14所述的晶片封装体的制造方法，其特征在于，该多个第二开口与该多个缺口连通。
16.根据权利要求14所述的晶片封装体的制造方法，其特征在于，该第二基底具有阶梯状侧壁。
17.一种晶片封装体，其特征在于，包括：
一第一基底，该第一基底内具有一导电垫；以及
一粘着层，位于该第一基底上，其中一阶梯状侧壁位于该导电垫外侧，且该阶梯状侧壁的一第一部分与该第一基底的一侧壁共平面。
18.根据权利要求17所述的晶片封装体，其特征在于，该粘着层包括胶带或粘晶层。
19.根据权利要求17所述的晶片封装体，其特征在于，该阶梯状侧壁的一第二部分突出于该第一基底的该侧壁。
20.根据权利要求19所述的晶片封装体，其特征在于，该第一基底的该侧壁为阶梯状。
21.根据权利要求17所述的晶片封装体，其特征在于，还包括一电路板，该电路板通过该粘着层贴附至该第一基底上。
22.根据权利要求21所述的晶片封装体，其特征在于，还包括一重布线层，该重布线层设置于该第一基底上，且与该导电垫电性连接，其中该重布线层延伸至该阶梯状侧壁上。
23.根据权利要求22所述的晶片封装体，其特征在于，该重布线层进一步延伸至该电路板上。
24.根据权利要求22所述的晶片封装体，其特征在于，还包括一焊线，该焊线设置于该阶梯状侧壁上的该重布线层上，且延伸至该电路板上。
25.根据权利要求17所述的晶片封装体，其特征在于，该粘着层具有该阶梯状侧壁。
26.根据权利要求17所述的晶片封装体，其特征在于，还包括第二基底，其中该粘着层设置于该第二基底与该第一基底之间，且该第二基底具有该阶梯状侧壁。
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