CN106935500A - 绝缘栅双极晶体管的场截止层的低温外延制作方法 - Google Patents
绝缘栅双极晶体管的场截止层的低温外延制作方法 Download PDFInfo
- Publication number
- CN106935500A CN106935500A CN201511031081.2A CN201511031081A CN106935500A CN 106935500 A CN106935500 A CN 106935500A CN 201511031081 A CN201511031081 A CN 201511031081A CN 106935500 A CN106935500 A CN 106935500A
- Authority
- CN
- China
- Prior art keywords
- igbt
- low
- layer
- temperature epitaxy
- field cutoff
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000407 epitaxy Methods 0.000 title claims abstract description 27
- 238000002360 preparation method Methods 0.000 title claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 238000000034 method Methods 0.000 claims abstract description 22
- 229910052751 metal Inorganic materials 0.000 claims abstract description 19
- 239000002184 metal Substances 0.000 claims abstract description 19
- 239000012535 impurity Substances 0.000 claims abstract description 15
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 239000004411 aluminium Substances 0.000 claims description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- 238000005334 plasma enhanced chemical vapour deposition Methods 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 239000010410 layer Substances 0.000 description 52
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 15
- 230000015556 catabolic process Effects 0.000 description 7
- 230000000149 penetrating effect Effects 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000024241 parasitism Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
Abstract
一种绝缘栅双极晶体管的场截止层的低温外延制作方法，首先提供一第一导电型基板，并在该第一导电型基板的一正面制作绝缘栅双极晶体管的正面元件及正面金属层；于第一导电型基板的背面以低温外延工艺制作多层第二导电型杂质层；再于第一导电型基板的背面以低温外延工艺制作一第一导电型杂质层；于第一导电型基板底部表面制作一集极金属层。
Description
技术领域
本发明涉及一种绝缘栅双极晶体管的制作方法，特别是一种绝缘栅双极晶体管的场截止层的低温外延制作方法。
背景技术
绝缘栅双极晶体管(Insulated Gate Bipolar Transistor,IGBT)是一种结合金氧半导体场效晶体管(metal-oxide-semiconductor field effect transistor，MOSFET)和双载子接面晶体管(bipolar junction transistor，BJT)的复合结构。IGBT因为结合了MOSET易于利用栅极控制的特性，以及BJT具低导通电压压降的特性，因此广泛应用于高电压高功率的应用领域。
一般的IGBT(例如一穿透型IGBT)主要包含一P+型半导体基底，于其上形成一N-型缓冲层，然后再于N-型缓冲层上形成一N型外延层，作为IGBT中寄生MOSFET的漏极。接着，于N型外延层内形成栅极结构(gate)及射极结构(emitter)，并于P+型半导体基底的底部形成集极(collector)。在上述的穿透型IGBT中，崩溃电压(breakdown voltage)主要是由P+型半导体基极及N-型缓冲层决定，在此两层间会有最大值电场产生。
另一种IGBT为非穿透型(Non Punch Through,NPT)IGBT则没有N-型缓冲层，因此崩溃电压由N型外延层(N型漂移区)的雪崩现象所决定。为了提高崩溃电压，场截止层(Field Stop)IGBT以场截止离子布植取代在穿透型IGBT中的N型缓冲层，借此以渐变(graded)或是线性渐进(linearly graded)N型剖面取代原有穿透型IGBT的陡峭接面(abrupt junction)，以降低电场最大值，进而提升崩溃电压。
现有技术的场截止层IGBT中，通常是在制作正面电极(大多包含铝材料)之前就必须在元件背面制作场截止层。这是由于铝电极的熔点在摄氏630度左右，而场截止层须在离子布植后再进行高温的热驱入步骤(高温约在摄氏900度以上)，此高温过程会破坏已经在正面形成的正面电极。然而上述的现有技术背面制作场截止层涉及以保护层先保护未制作正面电极的绝缘栅双极晶体管正面，再制作背面的场截止层，这样会增加工艺的复杂度。
发明内容
本发明所要解决的技术问题是针对现有技术的上述缺陷，提供一种可以简化工序的绝缘栅双极晶体管的场截止层的低温外延制作方法。
为了实现上述目的，本发明提供了一种绝缘栅双极晶体管的场截止层的低温外延制作方法，包含：(a)提供一第一导电型基板，并在该第一导电型基板的一正面制作绝缘栅双极晶体管的正面元件及正面金属层；(b)于第一导电型基板的背面以低温外延工艺制作多层第二导电型杂质层；(c)再于第一导电型基板的背面以低温外延工艺制作一第一导电型杂质层；(d)于第一导电型基板底部表面制作一集极金属层。
本发明的技术效果在于：
通过本发明由于场截止层(背面场栏)在正面金属完成之后制作，因此可以减少工序，降低成本。
另外，通过本发明的方法，可以制作多层具有不同杂质掺杂浓度的场截止层，有效提高崩溃电压。
以下结合附图和具体实施例对本发明进行详细描述，但不作为对本发明的限定。
附图说明
图1-图5为依据本发明一实施例的绝缘栅双极晶体管的场截止层的低温氧化制作方法各步骤的侧视图；
图6为本发明一实施例的绝缘栅双极晶体管的场截止层的低温氧化制作方法流程图。
其中，附图标记
10 N型基板
60 正面元件
62 正面金属层
20A-20D 掺磷单晶硅层
30 掺硼单晶硅层
80 集极金属层
S10-S16 步骤
具体实施方式
下面结合附图对本发明的结构原理和工作原理作具体的描述：
参见图1-图5，为依据本发明一实施例的绝缘栅双极晶体管的场截止层的低温氧化制作方法各步骤的侧视图。另外，参见图6，为依据本发明一实施例的绝缘栅双极晶体管的场截止层的低温氧化制作方法流程图。如图6所示，本发明的方法包含下列步骤：(S10)提供一第一导电型基板，并在该第一导电型基板的一正面制作绝缘栅双极晶体管的正面元件及正面金属层；(S12)于第一导电型基板的背面以低温外延工艺制作多层第二导电型杂质层；(S14)再于第一导电型基板的背面以低温外延工艺制作一第一导电型杂质层；(S16)于第一导电型基板底部表面制作一背部金属层。下面即配合图1-5详细说明上述步骤的细节。
如图1所示，首先在一N型基板10上依据传统工艺完成MOSFET正面元件60，及正面金属层62。随后如图2所示，在该N型基板10进行背面研磨，并且进行应变去除湿侵蚀(stress release wet etch)及洁净(clean)步骤，以薄化N型基板10，其中该N型基板10在薄化之后所剩余的厚度和此IGBT元件所设计的耐压相关。在薄化N型基板10之后，随即以低温外延工艺，例如以电浆增强化学气相沉积法(Plasma Enhanced Chemical VaporDeposition,简称PECVD)在N型基板10的背面制作多层掺磷单晶硅层20A-20D。PECVD是反应气体从等离子场中获得能量，激发并增强化学反应，从而实现化学气相沉积的技术。电浆增强化学气相沉积***使用射频(radio-frequency，简称RF)电源供应器提供RF电磁波产生电浆，使其为辅助能量，使得化学沉积的反应温度得以降低。在图3所示的工艺中，此PECVD工艺的反应温度在摄氏600度之下，以避免影响正面金属层62。
如图3所示，在PECVD工艺之后，例如可以制作四层杂质浓度不同的掺磷单晶硅层20A-20D，且此四层掺磷单晶硅层20A-20D作为此绝缘栅双极晶体管的场截止层。此四层掺磷单晶硅层20A-20D较佳者为沿着背面向深度方向浓度逐渐降低；换言之掺磷单晶硅层20D的浓度最高，其次为掺磷单晶硅层20C，再其次为掺磷单晶硅层20C，而掺磷单晶硅层20A的浓度最低。此外，此四层掺磷单晶硅层20A-20D的杂质浓度的范围为1X1013cm-3至1X1016cm-3；也就是说，掺磷单晶硅层20D的浓度最高，但是浓度仍低于1X1016cm-3；掺磷单晶硅层20A的浓度最低，但是浓度仍高于1X1013cm-3，以达成元件所需功效。
如图4所示，在制作完成掺磷单晶硅层20A-20D，再于N型基板10背面以低温外延工艺，例如以PECVD工艺制作一掺硼单晶硅层30，此PECVD工艺的反应温度在摄氏600度之下，以避免影响正面金属层62。
如图5所示，最后在N型基板10底部制作一背部金属层，以作为此绝缘栅双极晶体管的集极金属层80，此集极金属层80的材质可以(但是不限于)铝(Al)、氮化钛(TiN)、或是钨(W)。
通过上述的工艺，由于场截止层(背面场栏)在正面金属完成之后制作，因此可以减少工序，降低成本。
另外，通过本发明的方法，可以制作多层具有不同杂质掺杂浓度的场截止层，有效提高崩溃电压。
上述的实施例仅为本发明部分实施方式说明，本领域技术人员可知本发明仍有其余实施方式，例如上述的N型基板10可由P型基板取代，而连带的N型掺杂由P型掺杂取代、P型掺杂由N型掺杂取代，仍可达成本发明功效。
当然，本发明还可有其它多种实施例，在不背离本发明精神及其实质的情况下，熟悉本领域的技术人员当可根据本发明作出各种相应的改变和变形，但这些相应的改变和变形都应属于本发明所附的权利要求的保护范围。
Claims (7)
1.一种绝缘栅双极晶体管的场截止层的低温外延制作方法，其特征在于，包含下列步骤：
a、提供一第一导电型基板，并在该第一导电型基板的一正面制作绝缘栅双极晶体管的正面元件及正面金属层；
b、于第一导电型基板的背面以低温外延工艺制作多层第二导电型杂质层；
c、再于第一导电型基板的背面以低温外延工艺制作一第一导电型杂质层；
d、于第一导电型基板底部表面制作一集极金属层。
2.如权利要求1所述的绝缘栅双极晶体管的场截止层的低温外延制作方法，其特征在于，低温外延工艺为电浆增强化学气相沉积法。
3.如权利要求1所述的绝缘栅双极晶体管的场截止层的低温外延制作方法，其特征在于，该第一导电型为P型或是N型。
4.如权利要求1所述的绝缘栅双极晶体管的场截止层的低温外延制作方法，其特征在于，在步骤d之后形成四层场截止层。
5.如权利要求1所述的绝缘栅双极晶体管的场截止层的低温外延制作方法，其特征在于，在步骤b所形成的多层第二导电型杂质层，杂质浓度沿着背面向深度方向逐渐降低。
6.如权利要求5所述的绝缘栅双极晶体管的场截止层的低温外延制作方法，其特征在于，杂质浓度的范围为1X1013cm-3至1X1016cm-3。
7.如权利要求1所述的绝缘栅双极晶体管的场截止层的低温外延制作方法，其特征在于，该集极金属层的材质为铝、氮化钛或是钨。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511031081.2A CN106935500A (zh) | 2015-12-31 | 2015-12-31 | 绝缘栅双极晶体管的场截止层的低温外延制作方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511031081.2A CN106935500A (zh) | 2015-12-31 | 2015-12-31 | 绝缘栅双极晶体管的场截止层的低温外延制作方法 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106935500A true CN106935500A (zh) | 2017-07-07 |
Family
ID=59443900
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201511031081.2A Pending CN106935500A (zh) | 2015-12-31 | 2015-12-31 | 绝缘栅双极晶体管的场截止层的低温外延制作方法 |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106935500A (zh) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5242530A (en) * | 1991-08-05 | 1993-09-07 | International Business Machines Corporation | Pulsed gas plasma-enhanced chemical vapor deposition of silicon |
| CN103151251A (zh) * | 2011-12-07 | 2013-06-12 | 无锡华润华晶微电子有限公司 | 沟槽型绝缘栅双极型晶体管及其制备方法 |
| CN103871852A (zh) * | 2012-12-14 | 2014-06-18 | 中国科学院微电子研究所 | 一种带fs层的pt型功率器件的制作方法 |
| CN104992969A (zh) * | 2015-07-14 | 2015-10-21 | 株洲南车时代电气股份有限公司 | 具有缓冲层的半导体器件及其制作方法 |
-
2015
- 2015-12-31 CN CN201511031081.2A patent/CN106935500A/zh active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5242530A (en) * | 1991-08-05 | 1993-09-07 | International Business Machines Corporation | Pulsed gas plasma-enhanced chemical vapor deposition of silicon |
| CN103151251A (zh) * | 2011-12-07 | 2013-06-12 | 无锡华润华晶微电子有限公司 | 沟槽型绝缘栅双极型晶体管及其制备方法 |
| CN103871852A (zh) * | 2012-12-14 | 2014-06-18 | 中国科学院微电子研究所 | 一种带fs层的pt型功率器件的制作方法 |
| CN104992969A (zh) * | 2015-07-14 | 2015-10-21 | 株洲南车时代电气股份有限公司 | 具有缓冲层的半导体器件及其制作方法 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8525189B2 (en) | Silicon carbide semiconductor device | |
| US8492792B2 (en) | Semiconductor device and manufacturing method thereof | |
| TWI623102B (zh) | 半導體裝置與其形成方法 | |
| JP2011091100A (ja) | 炭化珪素半導体装置の製造方法 | |
| JP2014157896A (ja) | 半導体装置とその製造方法 | |
| JP2014236171A (ja) | 半導体装置およびその製造方法 | |
| JP2011151350A (ja) | 半導体装置の製造方法、及び半導体装置 | |
| CN106876256B (zh) | SiC双槽UMOSFET器件及其制备方法 | |
| US20150008478A1 (en) | Semiconductor device and manufacturing method of the same | |
| CN104576347A (zh) | Igbt背面金属化的改善方法 | |
| JP2012186318A (ja) | 高耐圧半導体装置 | |
| CN105493245B (zh) | 碳化硅半导体元件以及碳化硅半导体元件的制造方法 | |
| JP2012174895A (ja) | 高耐圧半導体装置 | |
| CN107946362A (zh) | 一种提高耐压范围的mosfet器件及其制备方法 | |
| CN103928345A (zh) | 离子注入形成n型重掺杂漂移层台面的碳化硅umosfet器件制备方法 | |
| JP2018152522A (ja) | 半導体装置および半導体装置の製造方法 | |
| JP6918154B2 (ja) | 半導体装置及び半導体装置の製造方法 | |
| JP5867609B2 (ja) | 半導体装置の製造方法 | |
| CN106935500A (zh) | 绝缘栅双极晶体管的场截止层的低温外延制作方法 | |
| JP6690333B2 (ja) | 炭化珪素半導体装置および炭化珪素半導体装置の製造方法 | |
| JP6325743B2 (ja) | 半導体装置およびその製造方法、並びに電力変換装置 | |
| JP2016157932A (ja) | 電力素子 | |
| CN102222619B (zh) | 半导体装置的制造方法 | |
| JP6295891B2 (ja) | 半導体装置および半導体装置の製造方法 | |
| TW201719762A (zh) | 絕緣柵雙極電晶體的背面場欄之低溫磊晶製作方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170707 |
|
| RJ01 | Rejection of invention patent application after publication |