CN106920746A - A kind of method for improving silicon chip surface microdefect - Google Patents
A kind of method for improving silicon chip surface microdefect Download PDFInfo
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- CN106920746A CN106920746A CN201510993955.6A CN201510993955A CN106920746A CN 106920746 A CN106920746 A CN 106920746A CN 201510993955 A CN201510993955 A CN 201510993955A CN 106920746 A CN106920746 A CN 106920746A
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- Prior art keywords
- annealing
- silicon chip
- chip surface
- hydrogen
- microdefect
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 41
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 40
- 239000010703 silicon Substances 0.000 title claims abstract description 39
- 238000000034 method Methods 0.000 title claims abstract description 26
- 238000000137 annealing Methods 0.000 claims abstract description 47
- 239000001257 hydrogen Substances 0.000 claims abstract description 31
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 31
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 28
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 12
- 239000007789 gas Substances 0.000 claims description 7
- 229910052786 argon Inorganic materials 0.000 claims description 6
- 150000002431 hydrogen Chemical class 0.000 claims description 3
- 239000002245 particle Substances 0.000 abstract description 3
- 238000001816 cooling Methods 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 241000208340 Araliaceae Species 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 235000019628 coolness Nutrition 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
- H01L21/3247—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering for altering the shape, e.g. smoothing the surface
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Abstract
The invention discloses a kind of method for improving silicon chip surface microdefect.In 450 DEG C of -700 DEG C of annealing, 1100 DEG C of -1250 DEG C of high annealings, 600 DEG C of -800 DEG C of annealing, 950 DEG C -1050 DEG C annealing process annealed are sequentially passed through, it is being warmed up to during 1000 DEG C from 800 DEG C, is adding trace hydrogen.Or, in 450 DEG C of -700 DEG C of annealing, 1100 DEG C of -1250 DEG C of high annealings, 600 DEG C of -800 DEG C of annealing, 950 DEG C -1050 DEG C annealing process annealed are sequentially passed through, during lowering the temperature from after 1000 DEG C of annealing, add trace hydrogen.The method of the present invention can change silicon chip surface microdefect situation in annealing process, and after annealing, (haze) of silicon chip surface improves, and reduces surface particles.
Description
Technical field
The present invention relates to a kind of method for improving silicon chip surface microdefect, belong to technical field of integrated circuits.
Background technology
Silicon chip is the main backing material of modern super large-scale integration, typically by crystal pulling, section, grinding,
The integrated circuit level semiconductor silicon chip that the technical process such as burn into annealing, polishing, cleaning are made.With ultra-large
The development of integrated circuit, 200mm/300mm silicon monocrystalline substrates have turned into the main flow of contemporary integrated circuits, to monocrystalline
The requirement of silicon chip surface quality also more and more higher, surface micro-roughness is two important ginsengs for characterizing silicon chip surface quality
Count, surface micro-roughness not only close by merchandiser crystalline phase, and also depend on silicon wafer polishing, cleaning, Deng Hou roads of annealing and add
Work technique.
Microroughness is nan orelief of the silicon chip surface in the range of nanoscale, typically with its average value Ra or square
Root RMS is characterized.It mainly describes adatom, vacancy, the torsion related with the several atomic layers in surface
The irregularity degree that rank etc. causes.It is an important indicator of modern microelectronics process, at present to diameter 300mm,
The requirement of the silicon chip surface microroughness of line width 90nm is 0.15nm.High annealing is to silicon chip surface microroughness
(haze) have a certain degree of influence, add hydrogen stream than it is larger when, the microroughness of silicon chip surface
(hazelevel) increase considerably, averagely increased more than 100%, but and non-linear change.Therefore, for
The selection of annealing atmosphere is very careful.Hydrogen is active gases, and hydrogen can be sent out with silicon atom and natural oxidizing layer simultaneously
Raw reaction, the reaction rate of the two is differed, and the course of reaction of complexity is formd in silicon chip surface, causes silicon chip table
The microroughness value in face increases.
The content of the invention
Based on above prior art, inventor is had found by research, and trace hydrogen is added in appropriate annealing process
Stream can cause that the microroughness of silicon chip surface has improvement.Hydrogen is passed through as annealing atmosphere using in reasonable time section
The external diffusion of silicon chip surface oxygen atom can be effectively facilitated, low-oxygen area is formed in silicon chip surface, and can suppress
The effect of micro amount of oxygen in atmosphere so that silicon chip surface microroughness (haze) improves.Therefore, it is of the invention
Purpose is to provide a kind of method for improving silicon chip surface microdefect.
To achieve the above object, the present invention takes following technical scheme：
It is a kind of improve silicon chip surface microdefect method, sequentially pass through 450 DEG C -700 DEG C annealing, 1100 DEG C -1250
In DEG C high annealing, 600 DEG C of -800 DEG C of annealing, the annealing process of 950 DEG C of -1050 DEG C of annealing, from 800 DEG C of intensifications
During 1000 DEG C, hydrogen is added, it is 0.5-8% to reach hydrogen with the volume ratio of argon gas.Preferably, hydrogen
Flow be 0.1-1SLM.
Or, sequentially pass through 450 DEG C of -700 DEG C of annealing, 1100 DEG C of -1250 DEG C of high annealings, 600 DEG C -800 DEG C move back
In fire, 950 DEG C -1050 DEG C annealing process annealed, during lowering the temperature from after 1000 DEG C of annealing, hydrogen is added,
It is 0.5-8% to reach hydrogen with the volume ratio of argon gas.Preferably, the flow of hydrogen is 0.1-1SLM.
The advantage of the invention is that：
The method of the present invention can change silicon chip surface microdefect situation, after annealing, silicon chip surface in annealing process
(haze) improve, and reduce surface particles.
The roughness of silicon chip surface can be reduced using the method for the present invention, therefore MOS device can be effectively improved
Gate oxide integrality.
Price due to wafer (Hi wafer) price by high-temperature hydrogen annealing far below epitaxial wafer, therefore this hair
Bright method low cost, has obtained a large amount of of the goods producers such as DRAM, Logic, Flash Memory and has used.
Specific embodiment
Below by embodiment, the present invention will be further described, but is not meant to the limit to the scope of the present invention
System.
Embodiment
It is that 300mmP types (100) crystal orientation gently mixes B silicon chips with batch to test the sample for using, and silicon wafer thickness is about
725 μm, oxygen content is (18~32) × 10-6(ASTM79), resistivity is 10~20 Ω cm, and experiment silicon chip is equal
Take from adjacent silicon chip in czochralski silicon monocrystal.
The A412 high-temperature annealing furnaces produced with ASM companies carry out high annealing.1100 DEG C of annealing temperature, constant temperature
Time 1h, during 1000 DEG C and 1000 DEG C coolings afterwards are raised to from 800 DEG C, is passed through flow for 0.3SLM
Hydrogen, it is 5.5% to control hydrogen and argon gas volume ratio, then with the surface of KLA-TENSOR companies production
Particle test instrument carries out silicon chip surface dependence test, haze level/10-60.09 is reduced to by 0.17 (when not adding hydrogen)
(when adding hydrogen).
Influence of the trace hydrogen in heating and cooling high annealing atmosphere to silicon chip surface, to using thick before and after hydrogen annealing
The contrast of rugosity, microroughness (haze) changes after illustrating to add the hydrogen in Microamounts of Hydrogen atmosphere to promote wafer anneal
It is kind.
By 1000 DEG C of annealing of constant temperature 16h temperature of annealing, in the temperature-fall period after the gentle annealing of liter before annealing,
The hydrogen that flow is 0.3SLM is passed through, it is 5.5% with argon gas volume ratio to control hydrogen, is then tested using AFM
The microroughness RMS of silicon chip is 0.112nm after annealing, 0.053nm is then become after annealing, it is also possible to illustrate to move back
Can improve the micro- coarse of silicon chip surface containing trace hydrogen during heating-cooling in internal heat atmosphere before and after 1000 DEG C
Degree.
Claims (4)
1. it is a kind of improve silicon chip surface microdefect method, it is characterised in that moved back sequentially passing through 450 DEG C -700 DEG C
In fire, 1100 DEG C of -1250 DEG C of high annealings, 600 DEG C of -800 DEG C of annealing, 950 DEG C -1050 DEG C annealing process annealed,
It is being warmed up to during 1000 DEG C from 800 DEG C, is adding hydrogen, it is being 0.5-8% to reach hydrogen with the volume ratio of argon gas.
2. it is according to claim 1 improve silicon chip surface microdefect method, it is characterised in that hydrogen flowing quantity
It is 0.1-1SLM.
3. it is a kind of improve silicon chip surface microdefect method, it is characterised in that moved back sequentially passing through 450 DEG C -700 DEG C
In fire, 1100 DEG C of -1250 DEG C of high annealings, 600 DEG C of -800 DEG C of annealing, 950 DEG C -1050 DEG C annealing process annealed,
During lowering the temperature from after 1000 DEG C of annealing, hydrogen is added, it is 0.5-8% to reach hydrogen with the volume ratio of argon gas.
4. it is according to claim 3 improve silicon chip surface microdefect method, it is characterised in that hydrogen flowing quantity
It is 0.1-1SLM.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510993955.6A CN106920746A (en) | 2015-12-25 | 2015-12-25 | A kind of method for improving silicon chip surface microdefect |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510993955.6A CN106920746A (en) | 2015-12-25 | 2015-12-25 | A kind of method for improving silicon chip surface microdefect |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106920746A true CN106920746A (en) | 2017-07-04 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510993955.6A Pending CN106920746A (en) | 2015-12-25 | 2015-12-25 | A kind of method for improving silicon chip surface microdefect |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1769549A (en) * | 2004-11-05 | 2006-05-10 | 北京有色金属研究总院 | Monocrystalline silicon buffing sheet heat treatment process |
| CN1838388A (en) * | 2005-03-21 | 2006-09-27 | 北京有色金属研究总院 | Rapid thermal process for silicon sheet capable of obtaining denuded zone and product thereof |
| CN1879204A (en) * | 2003-12-03 | 2006-12-13 | S.O.I.Tec绝缘体上硅技术公司 | Process for improving the surface roughness of a wafer |
| CN1879205A (en) * | 2003-12-03 | 2006-12-13 | S·O·I·Tec绝缘体上硅技术公司 | Process for improving the surface roughness of a semiconductor wafer |
| CN103820862A (en) * | 2012-11-16 | 2014-05-28 | 有研半导体材料股份有限公司 | Method for preparing high-temperature annealing silicon wafer |
-
2015
- 2015-12-25 CN CN201510993955.6A patent/CN106920746A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1879204A (en) * | 2003-12-03 | 2006-12-13 | S.O.I.Tec绝缘体上硅技术公司 | Process for improving the surface roughness of a wafer |
| CN1879205A (en) * | 2003-12-03 | 2006-12-13 | S·O·I·Tec绝缘体上硅技术公司 | Process for improving the surface roughness of a semiconductor wafer |
| CN1769549A (en) * | 2004-11-05 | 2006-05-10 | 北京有色金属研究总院 | Monocrystalline silicon buffing sheet heat treatment process |
| CN1838388A (en) * | 2005-03-21 | 2006-09-27 | 北京有色金属研究总院 | Rapid thermal process for silicon sheet capable of obtaining denuded zone and product thereof |
| CN103820862A (en) * | 2012-11-16 | 2014-05-28 | 有研半导体材料股份有限公司 | Method for preparing high-temperature annealing silicon wafer |
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| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170704 |
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