CN106910771A - Hermetically sealed vacuum nano pipe field-effect transistor and its manufacture method - Google Patents
Hermetically sealed vacuum nano pipe field-effect transistor and its manufacture method Download PDFInfo
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- CN106910771A CN106910771A CN201510981410.3A CN201510981410A CN106910771A CN 106910771 A CN106910771 A CN 106910771A CN 201510981410 A CN201510981410 A CN 201510981410A CN 106910771 A CN106910771 A CN 106910771A
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- 230000005669 field effect Effects 0.000 title claims abstract description 59
- 238000000034 method Methods 0.000 title claims abstract description 58
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 47
- 239000012528 membrane Substances 0.000 claims abstract description 30
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 10
- 239000002184 metal Substances 0.000 claims description 43
- 229910052751 metal Inorganic materials 0.000 claims description 43
- 239000002904 solvent Substances 0.000 claims description 18
- 239000004065 semiconductor Substances 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 13
- 238000000137 annealing Methods 0.000 claims description 12
- 229910021393 carbon nanotube Inorganic materials 0.000 claims description 9
- 239000002041 carbon nanotube Substances 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 9
- 230000008569 process Effects 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- 239000010408 film Substances 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 229910052737 gold Inorganic materials 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
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- 239000010432 diamond Substances 0.000 claims description 3
- 229910052733 gallium Inorganic materials 0.000 claims description 3
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052738 indium Inorganic materials 0.000 claims description 3
- 229910052742 iron Inorganic materials 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052758 niobium Inorganic materials 0.000 claims description 3
- 229910052763 palladium Inorganic materials 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 229910052715 tantalum Inorganic materials 0.000 claims description 3
- 229910052718 tin Inorganic materials 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 229910052720 vanadium Inorganic materials 0.000 claims description 3
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- 229910004166 TaN Inorganic materials 0.000 claims description 2
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- 239000010409 thin film Substances 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- 239000003054 catalyst Substances 0.000 abstract description 7
- 239000002105 nanoparticle Substances 0.000 abstract description 3
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- 238000010586 diagram Methods 0.000 description 5
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- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
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- 239000010944 silver (metal) Substances 0.000 description 2
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- 240000007594 Oryza sativa Species 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
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Abstract
The present invention proposes a kind of hermetically sealed vacuum nano pipe field-effect transistor and its manufacture method, nano particle is formed as catalyst on porous membrane surface, it is subsequently formed CNT, source-drain electrode surrounds gate dielectric layer, CNT is sealed in vacuum environment, so as to device operating voltages can be reduced after carbon nano field-effect transistor is subsequently formed, device service life and other performance are improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of hermetically sealed vacuum nano pipe field effect transistor
Pipe and its manufacture method.
Background technology
Conventional transistor MOSFET is by element manufacturing on monocrystalline substrate material.Constantly chasing mole fixed
Restrain under the impetus of (Moore ' s Law), the channel length of conventional transistor MOSFET is constantly reduced,
Device dimensions shrink.This contraction increased transistor density, improve the integrated level of chip, and other
Fixed factor and switching speed etc., while reducing power consumption, chip performance is constantly lifted.In future,
As technical requirements are improved constantly, and silicon can not be made smaller, then have to look for new
Chip manufacturing material, carbon nano-crystal body pipe is selection well.Received by using Single Carbon Nanotubes or carbon
Mitron array replaces the channel material of conventional bulk MOSFET structure, can to a certain extent overcome limitation simultaneously
And further reduce device dimension.
In the structure of preferable all-around-gate pole, the carbon nanotube field-effect transistor with self-aligning grid
(CarbonNano Tube Field Effect Transistor, CNTFET) size has had been reduced to 20nm.Surround
The uniformity of the grid of carbon nano-tube channel is consolidated, and such technique does not also cause to receive carbon
The infringement of mitron.
CNT chip can greatly improve the ability of high-performance computer, make big data analyze speed faster,
Increase the power and battery life of mobile device and Internet of Things, and allow cloud data center to provide more effectively and more
Economic service.
The content of the invention
It is an object of the invention to provide a kind of hermetically sealed vacuum nano pipe field-effect transistor and its manufacturer
Method, with better performance.
To achieve these goals, the present invention proposes a kind of hermetically sealed vacuum nano pipe field-effect transistor
Manufacture method, including step：
Semiconductor substrate is provided, dielectric layer and porous membrane are sequentially formed with the semiconductor substrate；
The mask layer of patterning is formed on the porous membrane surface, the mask layer exposes partially porous thin
Film；
Metal solvent is formed on the porous membrane surface for exposing, and removes the mask layer；
CNT is formed on the metal solvent, and etches the partially porous film of removal, the carbon nanometer
The two ends of pipe are supported by remaining porous membrane, make the CNT hanging；
Gate dielectric layer is formed in the carbon nano tube surface；
Metal gates are formed in the gate dielectric layer and dielectric layer surface, the metal gates are received positioned at the carbon
The middle end regions of mitron；
Etching removal exposes part CNT positioned at the part gate dielectric layer of the end surfaces of CNT two
Two ends；
The remaining porous membrane of etching removal；
Source-drain electrode, the source-drain electrode covering are formed respectively at the CNT two ends for exposing and dielectric layer surface
Part gate dielectric layer, and isolate with the metal gates.
Further, in the manufacture method of described hermetically sealed vacuum nano pipe field-effect transistor, in shape
Into after the source-drain electrode, also including step：The source-drain electrode is processed using high annealing, makes institute
State source-drain electrode and form protuberance in carbon nanotube.
Further, it is described in the manufacture method of described hermetically sealed vacuum nano pipe field-effect transistor
The range of reaction temperature of high-temperature annealing process is 600 degrees Celsius~1200 degrees Celsius.
Further, it is described in the manufacture method of described hermetically sealed vacuum nano pipe field-effect transistor
The gas that high-temperature annealing process is used is H2Or N2。
Further, it is described in the manufacture method of described hermetically sealed vacuum nano pipe field-effect transistor
The reaction time range of high-temperature annealing process is 10 seconds~120 minutes.
Further, it is described in the manufacture method of described hermetically sealed vacuum nano pipe field-effect transistor
The forming step of porous membrane includes：
Heavily doped polysilicon is formed in the dielectric layer surface；
Electronics etches the heavily doped polysilicon, forms porous polysilicon, obtains porous membrane.
Further, it is described in the manufacture method of described hermetically sealed vacuum nano pipe field-effect transistor
Mask layer includes silicon nitride layer and photoresistance, and the photoresistance is formed in the silicon nitride surface.
Further, it is described in the manufacture method of described hermetically sealed vacuum nano pipe field-effect transistor
Metal solvent includes Pt, Au, Ag, Cu or Ni.
Further, in the manufacture method of described hermetically sealed vacuum nano pipe field-effect transistor, in shape
Before forming CNT after into the metal solvent, also including step：To the porous membrane in H2Or
N2Under toasted.
Further, it is described in the manufacture method of described hermetically sealed vacuum nano pipe field-effect transistor
The forming step of CNT includes：CH is passed through in chemical vapor deposition chamber4, at high temperature and metal
CNT is formed under the conditions of catalyst.
Further, in the manufacture method of described hermetically sealed vacuum nano pipe field-effect transistor, formed
High temperature range needed for the CNT is 800 degrees Celsius~1000 degrees Celsius.
Further, it is described in the manufacture method of described hermetically sealed vacuum nano pipe field-effect transistor
The size range of metal solvent is 1nm~3nm.
Further, it is described in the manufacture method of described hermetically sealed vacuum nano pipe field-effect transistor
The material of source-drain electrode is low workfunction metal.
Further, it is described in the manufacture method of described hermetically sealed vacuum nano pipe field-effect transistor
The material of source-drain electrode be Zr, V, Nb, Ta, Cr, Mo, W, Fe, Co, Pd, Cu, Al, Ga, In,
The combination of Ti, TiN, TaN, diamond or more material.
Further, it is described in the manufacture method of described hermetically sealed vacuum nano pipe field-effect transistor
Vacuum ranges in CNT are 0.01Torr~50Torr.
Further, it is described in the manufacture method of described hermetically sealed vacuum nano pipe field-effect transistor
The length range of CNT is 2nm~100nm, and the size range of the CNT cross section is
1nm~5nm.
Further, it is described in the manufacture method of described hermetically sealed vacuum nano pipe field-effect transistor
Gate dielectric layer material is HfO2Or Al2O3。
Also, in the present invention, it is proposed that a kind of hermetically sealed vacuum nano pipe field-effect transistor, using such as above
The manufacture method of described hermetically sealed vacuum nano pipe field-effect transistor is prepared from, including：Semiconductor is served as a contrast
Bottom, dielectric layer, CNT, gate dielectric layer, metal gates and source-drain electrode, wherein, the dielectric layer shape
The dielectric layer surface, institute are formed in into the semiconductor substrate surface, the metal gates and source-drain electrode
State CNT to be surrounded by the gate dielectric layer, expose the two ends of CNT, the two of the gate dielectric layer
The two ends of the CNT held and expose are surrounded by the source-drain electrode, make the gate dielectric layer and CNT
Vacantly, the metal gates are located at the middle end regions of the CNT, and surround the gate dielectric layer.
Compared with prior art, the beneficial effects are mainly as follows：Formed on porous membrane surface and received
Rice grain is subsequently formed CNT as catalyst, and source-drain electrode surrounds gate dielectric layer, CNT is sealed
In vacuum environment, so as to device operating voltages can be reduced after carbon nano field-effect transistor is subsequently formed,
Improve device service life and other performance.
Brief description of the drawings
Fig. 1 is the stream of the manufacture method of hermetically sealed vacuum nano pipe field-effect transistor in one embodiment of the invention
Cheng Tu；
Fig. 2 to Figure 10 is the manufacture of hermetically sealed vacuum nano pipe field-effect transistor in one embodiment of the invention
The dimensional structure diagram of journey；
Figure 11 and Figure 12 be one embodiment of the invention in hermetically sealed vacuum nano pipe field-effect transistor along ditch
The generalized section in road direction；
Figure 13 be in one embodiment of the invention hermetically sealed vacuum nano pipe field-effect transistor along perpendicular to raceway groove side
To generalized section；
Figure 14 is the energy band schematic diagram of hermetically sealed vacuum nano pipe field-effect transistor in one embodiment of the invention.
Specific embodiment
Below in conjunction with schematic diagram to hermetically sealed vacuum nano pipe field-effect transistor of the invention and its manufacturer
Method is described in more detail, which show the preferred embodiments of the present invention, it should be appreciated that art technology
Personnel can change invention described herein, and still realize advantageous effects of the invention.Therefore, it is following
Description is appreciated that widely known for those skilled in the art, and is not intended as to limit of the invention
System.
For clarity, not describing whole features of practical embodiments.In the following description, public affairs are not described in detail
The function and structure known, because they can make the present invention chaotic due to unnecessary details.It will be understood that
In the exploitation of any practical embodiments, it is necessary to make a large amount of implementation details to realize the specific objective of developer,
For example according to about system or the limitation about business, another embodiment is changed into by one embodiment.Separately
Outward, it will be understood that this development is probably complicated and time-consuming, but for people in the art
It is only routine work for member.
The present invention is more specifically described by way of example referring to the drawings in the following passage.According to it is following explanation and
Claims, advantages and features of the invention will become apparent from.It should be noted that, accompanying drawing is using very simple
The form of change and use non-accurately ratio, be only used to conveniently, lucidly aid in illustrating the embodiment of the present invention
Purpose.
Fig. 1 is refer to, in the present embodiment, it is proposed that a kind of hermetically sealed vacuum nano pipe field-effect transistor
Manufacture method, including step：
S100：Semiconductor substrate is provided, dielectric layer and porous thin is sequentially formed with the semiconductor substrate
Film；
S200：The mask layer of patterning is formed on the porous membrane surface, the mask layer exposes part
Porous membrane；
S300：Metal solvent is formed on the porous membrane surface for exposing, and removes the mask layer；
S400：CNT is formed on the metal solvent, and etches the partially porous film of removal, it is described
The two ends of CNT are supported by remaining porous membrane, make the CNT hanging；
S500：Gate dielectric layer is formed in the carbon nano tube surface；
S600：Metal gates are formed in the gate dielectric layer and dielectric layer surface, the metal gates are located at institute
State the middle end regions of CNT；
S700：Etching removal exposes part carbon and receives positioned at the part gate dielectric layer of the end surfaces of CNT two
The two ends of mitron；
S800：The remaining porous membrane of etching removal；
S900：Source-drain electrode, the source and drain are formed respectively at the CNT two ends for exposing and dielectric layer surface
Pole covering part gate dielectric layer, and isolate with the metal gates.
Specifically, refer to Fig. 2, there is provided Semiconductor substrate 10, the shape successively in the Semiconductor substrate 10
Into having dielectric layer 20 and porous membrane 30.The forming step of the porous membrane 30 includes：
Heavily doped polysilicon, such as copper doped are formed on the surface of the dielectric layer 20；
Electronics etches the heavily doped polysilicon, forms porous polysilicon, obtains porous membrane 30.
Fig. 3 is refer to, the mask layer 40 of patterning, the mask layer are formed on the surface of the porous membrane 30
40 expose partially porous film 30, wherein, the mask layer 40 can include silicon nitride and photoresistance, institute
State photoresistance and be formed in the silicon nitride surface.
Fig. 4 is refer to, with the mask layer 40 as mask, gold is formed on the surface of porous membrane 30 for exposing
Category catalyst 50, and the mask layer 40 is removed, if including two-layer, first removing photoresistance, retain silicon nitride.
Wherein, the metal solvent 50 includes Pt, Au, Ag, Cu, Ni or other metal materials, gold
The size range for belonging to catalyst 50 is 1nm~3nm, and under the size, it can be very good as catalyst, after making
Continuous CNT is more readily formed, and metal solvent 50 is also used as the pillar of follow-up CNT.
Before CNT is formed after forming the metal solvent 50, also including step：To described porous
Film 30 is in H2Or N2Under toasted (Baking), this measure is in order to remove the steam in porous membrane 30
Deng impurity.At this point it is possible to remove the silicon nitride of reservation.
Fig. 5 is refer to, CNT 60 is formed on the metal solvent 50, wherein, the CNT
60 forming step includes：CH is passed through in chemical vapor deposition chamber4, at high temperature with metal solvent 50
Under the conditions of formed CNT 60.High temperature range needed for forming the CNT 60 is 800 degrees Celsius
~1000 degrees Celsius, e.g. 900 degrees Celsius, the length range of the CNT of formation is
2nm~100nm, e.g. 50nm, the size range of the cross section of the CNT 60 is 1nm~5nm,
E.g. 3nm.
Fig. 6 is refer to, using techniques such as photoresistance, exposure, etchings, partially porous film 30 is removed, it is described
The two ends of CNT 60 are supported by remaining porous membrane 30, make the CNT 60 hanging；Etching
Stop at the surface of the dielectric layer 20.
Fig. 7 is refer to, gate dielectric layer 70 is formed on the surface of the CNT 60；The gate dielectric layer 70
Material is HfO2Or Al2O3.The gate dielectric layer 70 surrounds the CNT 60.
Fig. 8 is refer to, metal gates 80 are formed in the gate dielectric layer 70 and the surface of dielectric layer 20, it is described
Metal gates 80 are located at the middle end regions of the CNT 60, i.e., positioned at the midpoint at the two ends of CNT 60
Near position, it can be formed by depositing, and then being removed by photoresistance, exposure and etching technics need not
Part.
Fig. 9 is refer to, etching removal exposes positioned at the part gate dielectric layer 70 of 60 liang of end surfaces of CNT
Go out the two ends of part CNT 60；It can be completed by photoresistance, exposure and etching, and then, etching is gone
Except remaining porous membrane 30, etching stopping is in the dielectric layer 20.
Figure 10 is refer to, source and drain is formed respectively at the two ends of CNT 60 and the surface of dielectric layer 20 for exposing
Pole 90, the covering part gate dielectric layer 70 of the source-drain electrode 90, and isolate with the metal gates 80, it is described
The material of source-drain electrode 90 be low workfunction metal, e.g. Zr, V, Nb, Ta, Cr, Mo, W, Fe,
The combination of Co, Pd, Cu, Al, Ga, In, Ti, TiN, TaN, diamond or more material, the source
Drain electrode 90 is formed using PVD or ALD techniques, and is formed under environment under low pressure, and the device after formation is cutd open
Face schematic diagram is as shown in figure 11.
Incorporated by reference to Figure 12 and Figure 13, after source-drain electrode 90 is formed, also including step：Using high annealing
The source-drain electrode 90 is processed, makes the source-drain electrode 90 that protuberance is formed at CNT 60, dashed forward
Going out portion can improve the performance of device, for example, open speed etc..The reaction temperature model of the high-temperature annealing process
It is 600 degrees Celsius~1200 degrees Celsius to enclose, e.g. 1000 degrees Celsius, the reaction of the high-temperature annealing process
Time range be 10 seconds~120 minutes, e.g. 60 minutes, the gas that the high-temperature annealing process is used for
H2Or N2。
In this application, it is also proposed that a kind of hermetically sealed vacuum nano pipe field-effect transistor, using such as above
The manufacture method of described hermetically sealed vacuum nano pipe field-effect transistor is prepared from, including：Semiconductor is served as a contrast
Bottom, dielectric layer, CNT, gate dielectric layer, metal gates and source-drain electrode, wherein, the dielectric layer shape
The dielectric layer surface, institute are formed in into the semiconductor substrate surface, the metal gates and source-drain electrode
State CNT to be surrounded by the gate dielectric layer, expose the two ends of CNT, the two of the gate dielectric layer
The two ends of the CNT held and expose are surrounded by the source-drain electrode, make the gate dielectric layer and CNT
Vacantly, the metal gates are located at the middle end regions of the CNT, and surround the gate dielectric layer.
Additionally, be able to can join with schematic diagram when the hermetically sealed vacuum nano pipe field-effect transistor for being formed works
Examine Figure 14, it is seen then that the hermetically sealed vacuum nano pipe field-effect transistor of formation open when electronics or vacancy from
The energy band migration distance that source electrode moves to drain electrode is shorter, makes the performance of whole device more preferably.
To sum up, in hermetically sealed vacuum nano pipe field-effect transistor provided in an embodiment of the present invention and its manufacturer
In method, nano particle is formed in conductive layer surface, CNT is subsequently formed, because nano particle can be made
It is catalyst, so as to contact resistance can be reduced after CNT is subsequently formed, improves device performance.
The preferred embodiments of the present invention are above are only, any restriction effect is not played to the present invention.Appoint
What person of ordinary skill in the field, is not departing from the range of technical scheme, to the present invention
The technical scheme and technology contents of exposure make any type of equivalent or modification etc. variation, belong to without departing from
The content of technical scheme, still falls within protection scope of the present invention.
Claims (18)
1. a kind of manufacture method of hermetically sealed vacuum nano pipe field-effect transistor, it is characterised in that including step
Suddenly：
Semiconductor substrate is provided, dielectric layer and porous membrane are sequentially formed with the semiconductor substrate；
The mask layer of patterning is formed on the porous membrane surface, the mask layer exposes partially porous thin
Film；
Metal solvent is formed on the porous membrane surface for exposing, and removes the mask layer；
CNT is formed on the metal solvent, and etches the partially porous film of removal, the carbon nanometer
The two ends of pipe are supported by remaining porous membrane, make the CNT hanging；
Gate dielectric layer is formed in the carbon nano tube surface；
Metal gates are formed in the gate dielectric layer and dielectric layer surface, the metal gates are received positioned at the carbon
The middle end regions of mitron；
Etching removal exposes part CNT positioned at the part gate dielectric layer of the end surfaces of CNT two
Two ends；
The remaining porous membrane of etching removal；
Source-drain electrode, the source-drain electrode covering are formed respectively at the CNT two ends for exposing and dielectric layer surface
Part gate dielectric layer, and isolate with the metal gates.
2. the manufacture method of hermetically sealed vacuum nano pipe field-effect transistor as claimed in claim 1, it is special
Levy and be, after the source-drain electrode is formed, also including step：The source-drain electrode is entered using high annealing
Row treatment, makes the source-drain electrode form protuberance in carbon nanotube.
3. the manufacture method of hermetically sealed vacuum nano pipe field-effect transistor as claimed in claim 2, it is special
Levy and be, the range of reaction temperature of the high-temperature annealing process is 600 degrees Celsius~1200 degrees Celsius.
4. the manufacture method of hermetically sealed vacuum nano pipe field-effect transistor as claimed in claim 2, it is special
Levy and be, the gas that the high-temperature annealing process is used is H2Or N2。
5. the manufacture method of hermetically sealed vacuum nano pipe field-effect transistor as claimed in claim 2, it is special
Levy and be, the reaction time range of the high-temperature annealing process is 10 seconds~120 minutes.
6. the manufacture method of hermetically sealed vacuum nano pipe field-effect transistor as claimed in claim 1, it is special
Levy and be, the forming step of the porous membrane includes：
Heavily doped polysilicon is formed in the dielectric layer surface；
Electronics etches the heavily doped polysilicon, forms porous polysilicon, obtains porous membrane.
7. the manufacture method of hermetically sealed vacuum nano pipe field-effect transistor as claimed in claim 1, it is special
Levy and be, the mask layer includes silicon nitride layer and photoresistance, the photoresistance is formed in the silicon nitride surface.
8. the manufacture method of hermetically sealed vacuum nano pipe field-effect transistor as claimed in claim 1, it is special
Levy and be, the metal solvent includes Pt, Au, Ag, Cu or Ni.
9. the manufacture method of hermetically sealed vacuum nano pipe field-effect transistor as claimed in claim 1, it is special
Levy and be, before CNT is formed after forming the metal solvent, also including step：To described many
Hole film is in H2Or N2Under toasted.
10. the manufacture method of hermetically sealed vacuum nano pipe field-effect transistor as claimed in claim 1, its
It is characterised by, the forming step of the CNT includes：CH is passed through in chemical vapor deposition chamber4,
At high temperature CNT is formed with the conditions of metal solvent.
The manufacture method of 11. hermetically sealed vacuum nano pipe field-effect transistors as claimed in claim 10, its
It is characterised by, the high temperature range needed for forming the CNT is 800 degrees Celsius~1000 degrees Celsius.
The manufacture method of 12. hermetically sealed vacuum nano pipe field-effect transistors as claimed in claim 10, its
It is characterised by, the size range of the metal solvent is 1nm~3nm.
The manufacture method of 13. hermetically sealed vacuum nano pipe field-effect transistors as claimed in claim 10, its
It is characterised by, the material of the source-drain electrode is low workfunction metal.
The manufacture method of 14. hermetically sealed vacuum nano pipe field-effect transistors as claimed in claim 13, its
Be characterised by, the material of the source-drain electrode is Zr, V, Nb, Ta, Cr, Mo, W, Fe, Co, Pd,
The combination of Cu, Al, Ga, In, Ti, TiN, TaN, diamond or more material.
The manufacture method of 15. hermetically sealed vacuum nano pipe field-effect transistors as claimed in claim 1, its
It is characterised by, the vacuum ranges in the CNT are 0.01Torr~50Torr.
The manufacture method of 16. hermetically sealed vacuum nano pipe field-effect transistors as claimed in claim 1, its
It is characterised by, the length range of the CNT is 2nm~100nm, the chi of the CNT cross section
Very little scope is 1nm~5nm.
The manufacture method of 17. hermetically sealed vacuum nano pipe field-effect transistors as claimed in claim 1, its
It is characterised by, the gate dielectric layer material is HfO2Or Al2O3。
18. a kind of hermetically sealed vacuum nano pipe field-effect transistors, using any in such as claim 1 to 17
The manufacture method of the hermetically sealed vacuum nano pipe field-effect transistor described in kind is prepared from, it is characterised in that
Including：Semiconductor substrate, dielectric layer, CNT, gate dielectric layer, metal gates and source-drain electrode, wherein,
The dielectric layer is formed in the semiconductor substrate surface, and the metal gates and source-drain electrode are formed in be given an account of
Matter layer surface, the CNT is surrounded by the gate dielectric layer, exposes the two ends of CNT, described
The two ends of the two ends of gate dielectric layer and the CNT for exposing are surrounded by the source-drain electrode, make the gate medium
Layer and CNT are hanging, and the metal gates are located at the middle end regions of the CNT, and surround described
Gate dielectric layer.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
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| CN201510981410.3A CN106910771B (en) | 2015-12-23 | 2015-12-23 | Hermetically sealed vacuum nano pipe field effect transistor and its manufacturing method |
| TW105118437A TWI594307B (en) | 2015-12-23 | 2016-06-13 | Fully vacuum sealed carbon nanotube transistor and method for preparing the same |
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| CN201510981410.3A CN106910771B (en) | 2015-12-23 | 2015-12-23 | Hermetically sealed vacuum nano pipe field effect transistor and its manufacturing method |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1922720A (en) * | 2004-12-28 | 2007-02-28 | 松下电器产业株式会社 | Semiconductor nano-wire, and semiconductor device provided with that nano-wire |
| US20090072223A1 (en) * | 2006-03-03 | 2009-03-19 | Fujitsu Limited | Field effect transistor using carbon nanotube, method of fabricating same, and sensor |
| US20140175381A1 (en) * | 2012-12-26 | 2014-06-26 | Globalfoundries Singapore Pte. Ltd. | Tunneling transistor |
| CN105097904A (en) * | 2014-05-05 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Tunneling carbon nano tube field effect transistor and manufacturing method thereof |
-
2015
- 2015-12-23 CN CN201510981410.3A patent/CN106910771B/en active Active
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2016
- 2016-06-13 TW TW105118437A patent/TWI594307B/en active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1922720A (en) * | 2004-12-28 | 2007-02-28 | 松下电器产业株式会社 | Semiconductor nano-wire, and semiconductor device provided with that nano-wire |
| US20090072223A1 (en) * | 2006-03-03 | 2009-03-19 | Fujitsu Limited | Field effect transistor using carbon nanotube, method of fabricating same, and sensor |
| US20140175381A1 (en) * | 2012-12-26 | 2014-06-26 | Globalfoundries Singapore Pte. Ltd. | Tunneling transistor |
| CN105097904A (en) * | 2014-05-05 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Tunneling carbon nano tube field effect transistor and manufacturing method thereof |
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| Publication number | Publication date |
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| TWI594307B (en) | 2017-08-01 |
| TW201724223A (en) | 2017-07-01 |
| CN106910771B (en) | 2019-11-26 |
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