CN106910687B - Vertical vacuum sealing carbon nanotube field-effect transistor and its manufacturing method - Google Patents
Vertical vacuum sealing carbon nanotube field-effect transistor and its manufacturing method Download PDFInfo
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- 239000002041 carbon nanotube Substances 0.000 title claims abstract description 124
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- 238000007789 sealing Methods 0.000 title claims abstract description 56
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/413—Nanosized electrodes, e.g. nanowire electrodes comprising one or a plurality of nanowires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
The invention proposes a kind of vertical vacuum sealing carbon nanotube field-effect transistor and its manufacturing methods, nano particle is formed as catalyst in conductive layer surface, it is subsequently formed carbon nanotube, gate dielectric layer is contacted with source-drain electrode, carbon nanotube is sealed in vacuum environment, to can reduce device operating voltages after being subsequently formed carbon nano field-effect transistor, device service life and other performance are improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of vertical vacuum sealing carbon nanotube field-effect transistors
And its manufacturing method.
Background technique
Conventional transistor MOSFET is by element manufacturing on monocrystalline substrate material.Constantly chasing Moore's Law
Under the impetus of (Moore ' s Law), the channel length of conventional transistor MOSFET is constantly reduced, device dimensions shrink.This
Kind, which is shunk, increases transistor density, improves the integrated level of chip, and other fixed factors and switching speed etc., simultaneously
Power consumption is reduced, promotes chip performance constantly.In future, as technical requirements are continuously improved, and silicon chip cannot be by
It is made to smaller, then has to look for new chip manufacturing material, carbon nano-crystal body pipe is to select well.By using single
Carbon nanotube or carbon nano pipe array replace the channel material of conventional bulk MOSFET structure, can overcome limit to a certain extent
It makes and further reduces device dimension.
In the structure of ideal all-around-gate pole, the carbon nanotube field-effect transistor with self-aligning grid
(CarbonNano Tube Field Effect Transistor, CNTFET) size has had been reduced to 20nm.Surround carbon nanometer
The uniformity of the grid in pipe trench road is consolidated, and such technique does not cause the damage to carbon nanotube yet.
Carbon nanotube chip can greatly improve the ability of high-performance computer, make big data analysis speed faster, increase
The power and battery life of mobile device and Internet of Things, and cloud data center is allowed to provide more effective and more economical service.
However, persistently becoming smaller with device size, increased contact resistance becomes carbon nanotube field-effect crystalline substance therewith
Body pipe proposes high performance maximum obstruction.It is increased since the size of transistor reduces for any advanced transistor technology
Contact resistance becomes a main performance bottleneck.Till now, the reduction of device size, causes contact resistance constantly to increase
Greatly, there is decline corresponding with contact resistance so as to cause device performance, this point is based on silicon and carbon nanometer transistor technology
Institute's facing challenges.
Summary of the invention
The purpose of the present invention is to provide a kind of vertical vacuum sealing carbon nanotube field-effect transistor and its manufacturing method,
The above problem can be overcome.
To achieve the goals above, the invention proposes a kind of systems of vertical vacuum sealing carbon nanotube field-effect transistor
Method is made, comprising steps of
Semiconductor substrate is provided, is formed with first single damascene structure on the semiconductor substrate, described first is single
Damascene structure includes dielectric layer and conductive layer, and the conductive layer is formed in the dielectric layer, and the dielectric layer exposes
The conductive layer；
Nano particle is formed in the conductive layer surface；
Multiple spaced carbon nanotubes are formed on the conductive layer；
Gate dielectric layer is formed in the dielectric layer, conductive layer and carbon nano tube surface；
Metal gates are formed on the gate dielectric layer surface, the atop part of the carbon nanotube stretches out the metal gates
Surface；
Second single damascene structure, the top of the carbon nanotube and described second are formed on the metal gates surface
Conductive layer in single damascene structure is connected.
Further, in the manufacturing method of the vertical vacuum sealing carbon nanotube field-effect transistor, described
The forming step of one single damascene structure includes:
Silicon nitride layer and dielectric layer are sequentially formed on the semiconductor substrate；
The dielectric layer is etched, forms groove, etching stopping is in the silicon nitride layer；
The conductive layer is filled in the groove.
Further, in the manufacturing method of the vertical vacuum sealing carbon nanotube field-effect transistor, described
Formed before the conductive layer in groove, be initially formed one layer of separation layer in the groove, the conductive layer be formed in it is described every
Absciss layer surface.
Further, in the manufacturing method of the vertical vacuum sealing carbon nanotube field-effect transistor, it is described every
Absciss layer is TaN or Ta.
Further, in the manufacturing method of the vertical vacuum sealing carbon nanotube field-effect transistor, described
The forming step of two single damascene structures includes:
Silicon nitride layer and dielectric layer, surface and the stretching of the silicon nitride layer are sequentially formed on the metal gates surface
It is flushed at the top of carbon nanotube；
The dielectric layer is etched, forms groove, in the silicon nitride layer, the groove exposes the carbon and receives etching stopping
The top of mitron；
Conductive layer is filled in the groove, and the conductive layer is connected with the top of the carbon nanotube.
Further, in the manufacturing method of the vertical vacuum sealing carbon nanotube field-effect transistor, described
It is formed before the conductive layer in groove, is initially formed one layer of separation layer in the groove, the separation layer is under vacuum conditions
It is formed, the conductive layer is formed in the insulation surface.
Further, in the manufacturing method of the vertical vacuum sealing carbon nanotube field-effect transistor, it is described every
Absciss layer is TaN, Mo or Ta.
Further, it in the manufacturing method of the vertical vacuum sealing carbon nanotube field-effect transistor, is given an account of
Matter layer is silica.
Further, in the manufacturing method of the vertical vacuum sealing carbon nanotube field-effect transistor, described
Nano particle is formed on conductive layer and the step of carbon nanotube includes:
Mask layer is formed in the dielectric layer surface, exposes the conductive layer；
Using the mask layer as exposure mask, nano particle is formed in the conductive layer surface；
After forming the nano particle, carbon nanotube is formed in the conductive layer surface；
Using negtive photoresist technology, the mask layer is removed.
Further, described to cover in the manufacturing method of the vertical vacuum sealing carbon nanotube field-effect transistor
The material of mold layer is BARC or unsetting carbon.
Further, described to receive in the manufacturing method of the vertical vacuum sealing carbon nanotube field-effect transistor
Rice grain material is Co or Mo.
Further, in the manufacturing method of the vertical vacuum sealing carbon nanotube field-effect transistor, the grid
Dielectric layer material is HfO2Or Al2O3。
Further, in the manufacturing method of the vertical vacuum sealing carbon nanotube field-effect transistor, the gold
Belong to grid forming step include:
Metal gates are formed on the gate dielectric layer surface, the metal gates cover the top of the carbon nanotube；
The metal gates are ground using chemical mechanical milling tech, expose the top of the carbon nanotube；
Processing is etched back to the metal gates using technique is etched back to, stretches the atop part of the carbon nanotube
The surface of the metal gates out.
Further, it in the manufacturing method of the vertical vacuum sealing carbon nanotube field-effect transistor, is being formed
After second single damascene structure, in H2Or N2The high temperature anneal is carried out under environment, makes the conduction at the carbon nanotube both ends
Layer has arcuate projection.
Further, in the manufacturing method of the vertical vacuum sealing carbon nanotube field-effect transistor, the height
The temperature range of temperature annealing is 600 degrees Celsius to 1200 degrees Celsius.
Further, in the manufacturing method of the vertical vacuum sealing carbon nanotube field-effect transistor, the height
The time range of temperature annealing is 10 seconds~120 minutes.
Further, in the manufacturing method of the vertical vacuum sealing carbon nanotube field-effect transistor, the carbon
Vacuum ranges in nanotube are 0.01Torr~50Torr.
Further, in the manufacturing method of the vertical vacuum sealing carbon nanotube field-effect transistor, the carbon
The length range of nanotube is 2nm~100nm, and the size range of the carbon nanotube cross section is 1nm~5nm.
Further, described to lead in the manufacturing method of the vertical vacuum sealing carbon nanotube field-effect transistor
The material of electric layer includes Zr, V, Nb, Ta, Cr, Mo, W, Fe, Co, Pd, Cu, Al, Ga, In, Ti, TiN, TaN, diamond or more
The combination of material.
Also, in the present invention, it is proposed that a kind of vertical vacuum sealing carbon nanotube field-effect transistor, using institute such as above
The manufacturing method for the vertical vacuum sealing carbon nanotube field-effect transistor stated is prepared, comprising: semiconductor substrate, the first list
The single damascene structure of damascene structure, carbon nanotube, gate dielectric layer, metal gates and second, wherein described first is single big
Ma Shige structure is formed on the semiconductor substrate, and the conductive layer surface in described first single damascene structure, which is formed with, to be received
Rice grain, the both ends of the carbon nanotube are separately connected conductive layer and second single big horse in described first single damascene structure
Scholar removes from office the conductive layer in structure, and the gate dielectric layer is formed in the surface of the carbon nanotube and dielectric layer, the metal gates
Be formed in the surface of the gate dielectric layer, and be located at described first single damascene structure and second single damascene structure it
Between.
Compared with prior art, the beneficial effects are mainly reflected as follows: conductive layer surface formed nano particle make
For catalyst, it is subsequently formed carbon nanotube, gate dielectric layer is contacted with source-drain electrode, carbon nanotube is sealed in vacuum environment, thus
Be subsequently formed carbon nano field-effect transistor can reduce device operating voltages later, improve device service life and other property
Energy.
Detailed description of the invention
Fig. 1 is the process of the manufacturing method of vertical vacuum sealing carbon nanotube field-effect transistor in one embodiment of the invention
Figure；
Fig. 2 to Figure 14 is the manufacturing process of vertical vacuum sealing carbon nanotube field-effect transistor in one embodiment of the invention
Diagrammatic cross-section；
Figure 15 is the diagrammatic cross-section in one embodiment of the invention along channel direction；
Figure 16 is in one embodiment of the invention along the diagrammatic cross-section perpendicular to channel direction；
Figure 17 is the energy band schematic diagram of vertical vacuum sealing carbon nanotube field-effect transistor in one embodiment of the invention.
Specific embodiment
Below in conjunction with schematic diagram to vertical vacuum sealing carbon nanotube field-effect transistor of the invention and its manufacturer
Method is described in more detail, and which show the preferred embodiment of the present invention, it should be appreciated that those skilled in the art can repair
Change invention described herein, and still realizes advantageous effects of the invention.Therefore, following description should be understood as this
Field technical staff's is widely known, and is not intended as limitation of the present invention.
For clarity, not describing whole features of practical embodiments.In the following description, it is not described in detail well known function
And structure, because they can make the present invention chaotic due to unnecessary details.It will be understood that opening in any practical embodiments
In hair, it is necessary to make a large amount of implementation details to realize the specific objective of developer, such as according to related system or related business
Limitation, changes into another embodiment by one embodiment.Additionally, it should think that this development may be complicated and expend
Time, but to those skilled in the art it is only routine work.
The present invention is more specifically described by way of example referring to attached drawing in the following passage.It is wanted according to following explanation and right
Book is sought, advantages and features of the invention will become apparent from.It should be noted that attached drawing is all made of very simplified form and using non-
Accurately ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
Referring to FIG. 1, in the present embodiment, proposing a kind of system of vertical vacuum sealing carbon nanotube field-effect transistor
Method is made, comprising steps of
S100: providing semiconductor substrate, is formed with first single damascene structure on the semiconductor substrate, and described the
One single damascene structure includes dielectric layer and conductive layer, and the conductive layer is formed in the dielectric layer, and the dielectric layer is sudden and violent
Expose the conductive layer；
S200: nano particle is formed in the conductive layer surface；
S300: multiple spaced carbon nanotubes are formed on the conductive layer；
S400: gate dielectric layer is formed in the dielectric layer, conductive layer and carbon nano tube surface；
S500: metal gates are formed on the gate dielectric layer surface, the atop part of the carbon nanotube stretches out the gold
Belong to the surface of grid；
S600: second single damascene structure, the top of the carbon nanotube and institute are formed on the metal gates surface
The conductive layer stated in second single damascene structure is connected.
Specifically, please referring to Fig. 2 to Fig. 3, the forming step of described first single damascene structure includes:
Silicon nitride layer 20 and dielectric layer 30 are sequentially formed in the semiconductor substrate 10；
The dielectric layer 30 is etched, forms groove, etching stopping is in the silicon nitride layer 20；
The conductive layer 41 is filled in the groove.
It is formed before the conductive layer 41 in the groove, is initially formed one layer of separation layer 40 in the groove, it is described
Conductive layer 41 is formed in 40 surface of separation layer, wherein the material of the conductive layer 41 can be copper, the material of dielectric layer 30
It can be silica, copper diffuses in dielectric layer 30 in order to prevent, it usually needs form conductive separation layer therebetween
40, wherein separation layer 40 can combine for Ta, TaN or both.
Fig. 4 to Fig. 7 is please referred to, includes: in the step of forming nano particle 42 and carbon nanotube 60 on the conductive layer 41
Mask layer 50 is formed on 30 surface of dielectric layer, exposes the conductive layer 41；
It is exposure mask with the mask layer 50, forms nano particle 42 on 41 surface of conductive layer；
After forming the nano particle 42, carbon nanotube 60 is formed on 41 surface of conductive layer；
Using negtive photoresist technology (lift-off), the mask layer 60 is removed.
Wherein, the material of the mask layer 60 is the materials such as BARC or unsetting carbon, and 42 material of nano particle is Co
Or Mo, the nano particle 42 of formation can be used as catalyst, reduce contact resistance.The length range of the carbon nanotube 60 is 2nm
The size range of~100nm, 60 cross section of carbon nanotube are 1nm~5nm.
Referring to FIG. 8, gate dielectric layer 70 is formed on the dielectric layer 30, conductive layer 41 and 60 surface of carbon nanotube, it is described
70 material of gate dielectric layer is HfO2Or Al2O3。
Fig. 9 to Figure 11 is please referred to, the forming step of the metal gates 80 includes:
Metal gates 80 are formed on 70 surface of gate dielectric layer, the metal gates 80 cover the carbon nanotube 60
Top, as shown in Figure 9；
The metal gates 80 are ground using chemical mechanical milling tech, expose the top of the carbon nanotube 60
Portion, as shown in Figure 10；
Processing is etched back to the metal gates 80 using technique is etched back to, pushes up the part of the carbon nanotube 60
The surface of the metal gates 80 is stretched out in portion, as shown in figure 11.
Then, Figure 12 to Figure 14 is please referred to, the forming step of described second single damascene structure includes:
In the metal gate, 80 surfaces sequentially form silicon nitride layer 20 and dielectric layer 30, the surface of the silicon nitride layer 20
It is flushed with the top of the carbon nanotube 60 of stretching；
The dielectric layer 30 is etched, groove is formed, in the silicon nitride layer 20, the groove exposes described etching stopping
The top of carbon nanotube 60 can clean the top of the carbon nanotube 60；
Conductive layer 41 is filled in the groove, and the conductive layer 41 is connected with the top of the carbon nanotube 60.
Likewise, the material of dielectric layer 30 is silica, the in order to prevent expansion of copper since the material of conductive layer 41 is copper
It dissipating, needs to form separation layer 40 between conductive layer 41 and dielectric layer 30, wherein the material of separation layer 40 can be TaN or Ta,
Doped with Co or Mo, comprising also can reduce contact electricity doped with Co or Mo in the separation layer 40 of second single damascene structure
Resistance.Wherein, the separation layer 40 is formed under vacuum conditions, and making the vacuum ranges in the carbon nanotube 60 is 0.01Torr
~50Torr.
The material of the conductive layer 41 includes Zr, V, Nb, Ta, Cr, Mo, W, Fe, Co, Pd, Cu, Al, Ga, In, Ti, TiN,
TaN, the combination of diamond or the above material.Wherein, first single damascene structure and second single damascene structure can be made
For the source-drain electrode of device.
After forming second single damascene structure, in H2Or N2The high temperature anneal is carried out under environment, and the carbon is made to receive
The conductive layer 41 or separation layer 41 at 60 both ends of mitron have arcuate projection, and the temperature range of the high annealing is 600 to take the photograph
For family name's degree to 1200 degrees Celsius, the time range of high annealing is 10 seconds~120 minutes, please refers to Figure 15, after the high temperature anneal,
Conductive layer 41 or separation layer 41 are capable of forming arcuate projection at 60 both ends of carbon nanotube, so as to improve the unlatching of channel
Speed.Wherein, the cross-sectional structure inside carbon nanotube 60 can refer to Figure 16.
In the another aspect of the present embodiment, it is also proposed that a kind of vertical vacuum sealing carbon nanotube field-effect transistor is adopted
It is prepared with the manufacturing method of vertical vacuum sealing carbon nanotube field-effect transistor as described above, comprising: semiconductor
Substrate, first single damascene structure, carbon nanotube, gate dielectric layer, metal gates and second single damascene structure, wherein
Described first single damascene structure is formed on the semiconductor substrate, the conductive layer in described first single damascene structure
Surface is formed with nano particle, and the both ends of the carbon nanotube are separately connected the conductive layer in described first single damascene structure
With the conductive layer in second single damascene structure, the gate dielectric layer is formed in the surface of the carbon nanotube and dielectric layer,
The metal gates are formed in the surface of the gate dielectric layer, and are located at described first single damascene structure and second single big horse
Scholar removes from office between structure.
In addition, energy band schematic diagram when the vertical vacuum sealing carbon nanotube field-effect transistor formed works can refer to
Figure 17, it is seen then that the vertical vacuum sealing carbon nanotube field-effect transistor of formation electronics or vacancy when opening are migrated from source electrode
Energy band migration distance to drain electrode is shorter, makes the performance of entire device more preferably.
To sum up, in vertical vacuum sealing carbon nanotube field-effect transistor provided in an embodiment of the present invention and its manufacturing method
In, nano particle is formed as catalyst in conductive layer surface, is subsequently formed carbon nanotube, and gate dielectric layer is contacted with source-drain electrode, will
Carbon nanotube is sealed in vacuum environment, to can reduce device work electricity after being subsequently formed carbon nano field-effect transistor
Pressure improves device service life and other performance.
The above is only a preferred embodiment of the present invention, does not play the role of any restrictions to the present invention.Belonging to any
Those skilled in the art, in the range of not departing from technical solution of the present invention, to the invention discloses technical solution and
Technology contents make the variation such as any type of equivalent replacement or modification, belong to the content without departing from technical solution of the present invention, still
Within belonging to the scope of protection of the present invention.
Claims (19)
1. a kind of manufacturing method of vertical vacuum sealing carbon nanotube field-effect transistor, which is characterized in that comprising steps of
Semiconductor substrate is provided, is formed with first single damascene structure, described first single big horse on the semiconductor substrate
It includes dielectric layer and conductive layer that scholar, which removes from office structure, and the conductive layer is formed in the dielectric layer, and the dielectric layer exposes described
Conductive layer；
Nano particle is formed in the conductive layer surface；
Multiple spaced carbon nanotubes are formed on the conductive layer；
Gate dielectric layer is formed in the dielectric layer, conductive layer and carbon nano tube surface；
Metal gates are formed on the gate dielectric layer surface, the atop part of the carbon nanotube stretches out the table of the metal gates
Face；
Second single damascene structure is formed on the metal gates surface, the top of the carbon nanotube and second list are big
Conductive layer in Ma Shige structure is connected；
After forming second single damascene structure, the high temperature anneal is carried out under H2 or N2 environment, makes the carbon nanometer
The conductive layer at pipe both ends has arcuate projection.
2. the manufacturing method of vertical vacuum sealing carbon nanotube field-effect transistor as described in claim 1, which is characterized in that
The forming step of first single damascene structure includes:
Silicon nitride layer and dielectric layer are sequentially formed on the semiconductor substrate；
The dielectric layer is etched, forms groove, etching stopping is in the silicon nitride layer；
The conductive layer is filled in the groove.
3. the manufacturing method of vertical vacuum sealing carbon nanotube field-effect transistor as claimed in claim 2, which is characterized in that
It is formed before the conductive layer in the groove, is initially formed one layer of separation layer in the groove, the conductive layer is formed in
The insulation surface.
4. the manufacturing method of vertical vacuum sealing carbon nanotube field-effect transistor as claimed in claim 3, which is characterized in that
The separation layer is TaN or Ta.
5. the manufacturing method of vertical vacuum sealing carbon nanotube field-effect transistor as described in claim 1, which is characterized in that
The forming step of second single damascene structure includes:
Silicon nitride layer and dielectric layer are sequentially formed on the metal gates surface, the surface of the silicon nitride layer and the carbon of stretching are received
It is flushed at the top of mitron；
The dielectric layer is etched, groove is formed, etching stopping exposes the carbon nanotube in the silicon nitride layer, the groove
Top；
Conductive layer is filled in the groove, and the conductive layer is connected with the top of the carbon nanotube.
6. the manufacturing method of vertical vacuum sealing carbon nanotube field-effect transistor as claimed in claim 5, which is characterized in that
It is formed before the conductive layer in the groove, is initially formed one layer of separation layer in the groove, the separation layer is in vacuum
Under the conditions of formed, the conductive layer is formed in the insulation surface.
7. the manufacturing method of vertical vacuum sealing carbon nanotube field-effect transistor as claimed in claim 6, which is characterized in that
The separation layer is TaN or Ta, doped with Co or Mo.
8. the manufacturing method of vertical vacuum sealing carbon nanotube field-effect transistor as described in claim 1, which is characterized in that
The dielectric layer is silica.
9. the manufacturing method of vertical vacuum sealing carbon nanotube field-effect transistor as described in claim 1, which is characterized in that
Include: in the step of forming nano particle and carbon nanotube on the conductive layer
Mask layer is formed in the dielectric layer surface, exposes the conductive layer；
Using the mask layer as exposure mask, nano particle is formed in the conductive layer surface；
After forming the nano particle, carbon nanotube is formed in the conductive layer surface；
Using negtive photoresist technology, the mask layer is removed.
10. the manufacturing method of vertical vacuum sealing carbon nanotube field-effect transistor as claimed in claim 9, feature exist
In the material of the mask layer is BARC or unsetting carbon.
11. the manufacturing method of vertical vacuum sealing carbon nanotube field-effect transistor as claimed in claim 9, feature exist
In the nano particle material is Co or Mo.
12. the manufacturing method of vertical vacuum sealing carbon nanotube field-effect transistor as described in claim 1, feature exist
In the gate dielectric layer material is HfO2 or Al2O3.
13. the manufacturing method of vertical vacuum sealing carbon nanotube field-effect transistor as described in claim 1, feature exist
In the forming step of the metal gates includes:
Metal gates are formed on the gate dielectric layer surface, the metal gates cover the top of the carbon nanotube；
The metal gates are ground using chemical mechanical milling tech, expose the top of the carbon nanotube；
Processing is etched back to the metal gates using technique is etched back to, the atop part of the carbon nanotube is made to stretch out institute
State the surface of metal gates.
14. the manufacturing method of vertical vacuum sealing carbon nanotube field-effect transistor as described in claim 1, feature exist
In the temperature range of the high annealing is 600 degrees Celsius to 1200 degrees Celsius.
15. the manufacturing method of vertical vacuum sealing carbon nanotube field-effect transistor as described in claim 1, feature exist
In the time range of the high annealing is 10 seconds~120 minutes.
16. the manufacturing method of vertical vacuum sealing carbon nanotube field-effect transistor as described in claim 1, feature exist
In the vacuum ranges in the carbon nanotube are 0.01Torr~50Torr.
17. the manufacturing method of vertical vacuum sealing carbon nanotube field-effect transistor as described in claim 1, feature exist
In the length range of the carbon nanotube is 2nm~100nm, and the size range of the carbon nanotube cross section is 1nm~5nm.
18. the manufacturing method of vertical vacuum sealing carbon nanotube field-effect transistor as described in claim 1, feature exist
In the material of the conductive layer includes Zr, V, Nb, Ta, Cr, Mo, W, Fe, Co, Pd, Cu, Al, Ga, In, Ti, TiN, TaN, gold
The combination of hard rock or the above material.
19. a kind of vertical vacuum sealing carbon nanotube field-effect transistor, using as described in any in claim 1 to 18
The manufacturing method of vertical vacuum sealing carbon nanotube field-effect transistor is prepared characterized by comprising semiconductor lining
Bottom, first single damascene structure, carbon nanotube, gate dielectric layer, metal gates and second single damascene structure, wherein institute
It states first single damascene structure to be formed on the semiconductor substrate, the conductive layer table in described first single damascene structure
Face is formed with nano particle, the both ends of the carbon nanotube be separately connected conductive layer in described first single damascene structure and
Conductive layer in second single damascene structure, the gate dielectric layer are formed in the surface of the carbon nanotube and dielectric layer, institute
The surface that metal gates are formed in the gate dielectric layer is stated, and is located at described first single damascene structure and second single damascene
It removes from office between structure, the conductive layer at the carbon nanotube both ends has arcuate projection.
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| CN1720606A (en) * | 2002-11-29 | 2006-01-11 | 日本电气株式会社 | Semiconductor device and manufacture method thereof |
| CN1926680A (en) * | 2004-02-26 | 2007-03-07 | 国际商业机器公司 | Integrated circuit chip utilizing carbon nanotube composite interconnection vias |
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| CN1638066A (en) * | 2004-01-07 | 2005-07-13 | 国际商业机器公司 | Vertical carbon nanotube field effect transistor |
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