CN106910687A - Vertical vacuum sealing carbon nanotube field-effect transistor and its manufacture method - Google Patents
Vertical vacuum sealing carbon nanotube field-effect transistor and its manufacture method Download PDFInfo
- Publication number
- CN106910687A CN106910687A CN201510981315.3A CN201510981315A CN106910687A CN 106910687 A CN106910687 A CN 106910687A CN 201510981315 A CN201510981315 A CN 201510981315A CN 106910687 A CN106910687 A CN 106910687A
- Authority
- CN
- China
- Prior art keywords
- carbon nanotube
- layer
- conductive layer
- manufacture method
- vacuum sealing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 title claims abstract description 77
- 239000002041 carbon nanotube Substances 0.000 title claims abstract description 68
- 229910021393 carbon nanotube Inorganic materials 0.000 title claims abstract description 65
- 230000005669 field effect Effects 0.000 title claims abstract description 62
- 238000007789 sealing Methods 0.000 title claims abstract description 57
- 238000000034 method Methods 0.000 title claims abstract description 54
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 52
- 239000002105 nanoparticle Substances 0.000 claims abstract description 21
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims description 33
- 229910052751 metal Inorganic materials 0.000 claims description 33
- 239000000463 material Substances 0.000 claims description 24
- 239000000758 substrate Substances 0.000 claims description 16
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 15
- 239000004065 semiconductor Substances 0.000 claims description 15
- 238000000926 separation method Methods 0.000 claims description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 15
- 229910052750 molybdenum Inorganic materials 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 229910004166 TaN Inorganic materials 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 238000005516 engineering process Methods 0.000 claims description 7
- 238000000137 annealing Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 238000009413 insulation Methods 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 229910052715 tantalum Inorganic materials 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 3
- 229910052804 chromium Inorganic materials 0.000 claims description 3
- 229910052593 corundum Inorganic materials 0.000 claims description 3
- 229910003460 diamond Inorganic materials 0.000 claims description 3
- 239000010432 diamond Substances 0.000 claims description 3
- 229910052733 gallium Inorganic materials 0.000 claims description 3
- 239000003292 glue Substances 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052738 indium Inorganic materials 0.000 claims description 3
- 229910052742 iron Inorganic materials 0.000 claims description 3
- 238000003701 mechanical milling Methods 0.000 claims description 3
- 229910052758 niobium Inorganic materials 0.000 claims description 3
- 229910052763 palladium Inorganic materials 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 229910052718 tin Inorganic materials 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 229910052720 vanadium Inorganic materials 0.000 claims description 3
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 3
- 229910052726 zirconium Inorganic materials 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- 239000004020 conductor Substances 0.000 claims 1
- 239000010985 leather Substances 0.000 claims 1
- 239000003054 catalyst Substances 0.000 abstract description 4
- 239000010949 copper Substances 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000011203 carbon fibre reinforced carbon Substances 0.000 description 1
- 230000000739 chaotic effect Effects 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000003467 diminishing effect Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000002159 nanocrystal Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/413—Nanosized electrodes, e.g. nanowire electrodes comprising one or a plurality of nanowires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
The present invention proposes a kind of vertical vacuum sealing carbon nanotube field-effect transistor and its manufacture method, nano particle is formed as catalyst in conductive layer surface, it is subsequently formed CNT, gate dielectric layer is contacted with source-drain electrode, CNT is sealed in vacuum environment, so as to device operating voltages can be reduced after carbon nano field-effect transistor is subsequently formed, device service life and other performance are improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of vertical vacuum sealing carbon nanotube field-effect
Transistor and its manufacture method.
Background technology
Conventional transistor MOSFET is by element manufacturing on monocrystalline substrate material.Constantly chasing mole fixed
Restrain under the impetus of (Moore ' s Law), the channel length of conventional transistor MOSFET is constantly reduced,
Device dimensions shrink.This contraction increased transistor density, improve the integrated level of chip, and other
Fixed factor and switching speed etc., while reducing power consumption, chip performance is constantly lifted.In future,
As technical requirements are improved constantly, and silicon can not be made smaller, then have to look for new
Chip manufacturing material, carbon nano-crystal body pipe is selection well.Received by using Single Carbon Nanotubes or carbon
Mitron array replaces the channel material of conventional bulk MOSFET structure, can to a certain extent overcome limitation simultaneously
And further reduce device dimension.
In the structure of preferable all-around-gate pole, the carbon nanotube field-effect transistor with self-aligning grid
(CarbonNano Tube Field Effect Transistor, CNTFET) size has had been reduced to 20nm.Surround
The uniformity of the grid of carbon nano-tube channel is consolidated, and such technique does not also cause to receive carbon
The infringement of mitron.
CNT chip can greatly improve the ability of high-performance computer, make big data analyze speed faster,
Increase the power and battery life of mobile device and Internet of Things, and allow cloud data center to provide more effectively and more
Economic service.
However, persistently diminishing with device size, increased contact resistance becomes carbon nano tube field therewith
Effect transistor puies forward high performance maximum obstruction.For any advanced transistor technology, due to transistor
Size reduces and increased contact resistance turns into a main performance bottleneck.Till now, device size
Reduction, cause contact resistance constantly to increase, so as to cause device performance exist it is corresponding with contact resistance under
Drop, this point is based on silicon and carbon nanometer transistor technology institute facing challenges.
The content of the invention
It is an object of the invention to provide a kind of vertical vacuum sealing carbon nanotube field-effect transistor and its manufacture
Method, can overcome above mentioned problem.
To achieve these goals, the present invention proposes a kind of vertical vacuum sealing carbon nanotube field-effect crystal
The manufacture method of pipe, including step：
Semiconductor substrate is provided, first single damascene structure is formed with the semiconductor substrate, it is described
First single damascene structure includes dielectric layer and conductive layer, and the conductive layer is formed in the dielectric layer,
The dielectric layer exposes the conductive layer；
Nano particle is formed in the conductive layer surface；
Multiple spaced CNTs are formed on the conductive layer；
Gate dielectric layer is formed in the dielectric layer, conductive layer and carbon nano tube surface；
Metal gates are formed on the gate dielectric layer surface, the atop part of the CNT stretches out the gold
Belong to the surface of grid；
Second single damascene structure, the top of the CNT and institute are formed on the metal gates surface
The conductive layer stated in second single damascene structure is connected.
Further, in the manufacture method of described vertical vacuum sealing carbon nanotube field-effect transistor,
The forming step of described first single damascene structure includes：
Silicon nitride layer and dielectric layer are sequentially formed on the semiconductor substrate；
The dielectric layer is etched, groove is formed, etching stopping is in the silicon nitride layer；
The conductive layer is filled in the groove.
Further, in the manufacture method of described vertical vacuum sealing carbon nanotube field-effect transistor,
Before the conductive layer is formed in the groove, one layer of separation layer is initially formed in the groove, it is described to lead
Electric layer is formed in the insulation surface.
Further, in the manufacture method of described vertical vacuum sealing carbon nanotube field-effect transistor,
The separation layer is TaN or Ta.
Further, in the manufacture method of described vertical vacuum sealing carbon nanotube field-effect transistor,
The forming step of described second single damascene structure includes：
Sequentially form silicon nitride layer and dielectric layer on the metal gates surface, the surface of the silicon nitride layer with
Flushed at the top of the CNT for stretching out；
The dielectric layer is etched, groove is formed, etching stopping exposes in the silicon nitride layer, the groove
The top of the CNT；
Conductive layer is filled in the groove, the conductive layer is connected with the top of the CNT.
Further, in the manufacture method of described vertical vacuum sealing carbon nanotube field-effect transistor,
Before the conductive layer is formed in the groove, be initially formed one layer of separation layer in the groove, it is described every
Absciss layer is formed under vacuum, and the conductive layer is formed in the insulation surface.
Further, in the manufacture method of described vertical vacuum sealing carbon nanotube field-effect transistor,
The separation layer is TaN, Mo or Ta.
Further, in the manufacture method of described vertical vacuum sealing carbon nanotube field-effect transistor,
The dielectric layer is silica.
Further, in the manufacture method of described vertical vacuum sealing carbon nanotube field-effect transistor,
The step of nano particle and CNT are formed on the conductive layer includes：
Mask layer is formed in the dielectric layer surface, the conductive layer is exposed；
With the mask layer as mask, nano particle is formed in the conductive layer surface；
After the nano particle is formed, CNT is formed in the conductive layer surface；
Using negative glue technology, the mask layer is removed.
Further, in the manufacture method of described vertical vacuum sealing carbon nanotube field-effect transistor,
The material of the mask layer is BARC or unsetting carbon.
Further, in the manufacture method of described vertical vacuum sealing carbon nanotube field-effect transistor,
The nano particle material is Co or Mo.
Further, in the manufacture method of described vertical vacuum sealing carbon nanotube field-effect transistor,
The gate dielectric layer material is HfO2Or Al2O3。
Further, in the manufacture method of described vertical vacuum sealing carbon nanotube field-effect transistor,
The forming step of the metal gates includes：
Metal gates are formed on the gate dielectric layer surface, the metal gates cover the top of the CNT
Portion；
The metal gates are ground using chemical mechanical milling tech, expose the CNT
Top；
Treatment is etched back to the metal gates using technique is etched back to, makes the part of the CNT
The surface of the metal gates is stretched out at top.
Further, in the manufacture method of described vertical vacuum sealing carbon nanotube field-effect transistor,
After second single damascene structure is formed, in H2Or N2The high temperature anneal is carried out under environment, is made described
The conductive layer at CNT two ends has arcuate projection.
Further, in the manufacture method of described vertical vacuum sealing carbon nanotube field-effect transistor,
The temperature range of the high annealing is 600 degrees Celsius to 1200 degrees Celsius.
Further, in the manufacture method of described vertical vacuum sealing carbon nanotube field-effect transistor,
The time range of the high annealing is 10 seconds~120 minutes.
Further, in the manufacture method of described vertical vacuum sealing carbon nanotube field-effect transistor,
Vacuum ranges in the CNT are 0.01Torr~50Torr.
Further, in the manufacture method of described vertical vacuum sealing carbon nanotube field-effect transistor,
The length range of the CNT is 2nm~100nm, and the size range of the CNT cross section is
1nm~5nm.
Further, in the manufacture method of described vertical vacuum sealing carbon nanotube field-effect transistor,
The material of the conductive layer includes Zr, V, Nb, Ta, Cr, Mo, W, Fe, Co, Pd, Cu, Al, Ga, In, Ti, TiN,
The combination of TaN, diamond or more material.
Also, in the present invention, it is proposed that a kind of vertical vacuum sealing carbon nanotube field-effect transistor, using such as
The manufacture method of vertical vacuum sealing carbon nanotube field-effect transistor mentioned above is prepared from, including：
Semiconductor substrate, first single damascene structure, CNT, gate dielectric layer, metal gates and second are single
Damascene structure, wherein, described first single damascene structure is formed on the semiconductor substrate, institute
The conductive layer surface stated in first single damascene structure is formed with nano particle, the two ends of the CNT
The conduction in the conductive layer and second single damascene structure in described first single damascene structure is connected respectively
Layer, the gate dielectric layer is formed in the surface of the CNT and dielectric layer, and the metal gates are formed in
The surface of the gate dielectric layer, and positioned at described first single damascene structure and second single damascene structure
Between.
Compared with prior art, the beneficial effects are mainly as follows：Nanometer is formed in conductive layer surface
Particle is subsequently formed CNT as catalyst, and gate dielectric layer is contacted with source-drain electrode, and CNT is sealed
In vacuum environment, so as to device operating voltages can be reduced after carbon nano field-effect transistor is subsequently formed,
Improve device service life and other performance.
Brief description of the drawings
Fig. 1 is the manufacture method of vertical vacuum sealing carbon nanotube field-effect transistor in one embodiment of the invention
Flow chart；
Fig. 2 to Figure 14 is the system of vertical vacuum sealing carbon nanotube field-effect transistor in one embodiment of the invention
Make the generalized section of process；
Figure 15 is the generalized section in one embodiment of the invention along channel direction；
Figure 16 is generalized section of the edge perpendicular to channel direction in one embodiment of the invention；
Figure 17 is that the energy band of vertical vacuum sealing carbon nanotube field-effect transistor in one embodiment of the invention is illustrated
Figure.
Specific embodiment
Below in conjunction with schematic diagram to vertical vacuum sealing carbon nanotube field-effect transistor of the invention and its system
The method of making is described in more detail, which show the preferred embodiments of the present invention, it should be appreciated that this area
Technical staff can change invention described herein, and still realize advantageous effects of the invention.Therefore,
Description below is appreciated that widely known for those skilled in the art, and is not intended as to the present invention
Limitation.
For clarity, not describing whole features of practical embodiments.In the following description, public affairs are not described in detail
The function and structure known, because they can make the present invention chaotic due to unnecessary details.It will be understood that
In the exploitation of any practical embodiments, it is necessary to make a large amount of implementation details to realize the specific objective of developer,
For example according to about system or the limitation about business, another embodiment is changed into by one embodiment.Separately
Outward, it will be understood that this development is probably complicated and time-consuming, but for people in the art
It is only routine work for member.
The present invention is more specifically described by way of example referring to the drawings in the following passage.According to it is following explanation and
Claims, advantages and features of the invention will become apparent from.It should be noted that, accompanying drawing is using very simple
The form of change and use non-accurately ratio, be only used to conveniently, lucidly aid in illustrating the embodiment of the present invention
Purpose.
Fig. 1 is refer to, in the present embodiment, it is proposed that a kind of vertical vacuum sealing carbon nanotube field-effect crystal
The manufacture method of pipe, including step：
S100：Semiconductor substrate is provided, first single damascene structure is formed with the semiconductor substrate,
Described first single damascene structure includes dielectric layer and conductive layer, and the conductive layer is formed in the dielectric layer
Interior, the dielectric layer exposes the conductive layer；
S200：Nano particle is formed in the conductive layer surface；
S300：Multiple spaced CNTs are formed on the conductive layer；
S400：Gate dielectric layer is formed in the dielectric layer, conductive layer and carbon nano tube surface；
S500：Metal gates are formed on the gate dielectric layer surface, the atop part of the CNT stretches out
The surface of the metal gates；
S600：Second single damascene structure, the top of the CNT are formed on the metal gates surface
Portion is connected with the conductive layer in described second single damascene structure.
Specifically, refer to Fig. 2 to Fig. 3, the forming step of described first single damascene structure includes：
Silicon nitride layer 20 and dielectric layer 30 are sequentially formed in the Semiconductor substrate 10；
The dielectric layer 30 is etched, groove is formed, etching stopping is in the silicon nitride layer 20；
The conductive layer 41 is filled in the groove.
Before the conductive layer 41 is formed in the groove, one layer of separation layer 40 is initially formed in the groove,
The conductive layer 41 is formed in the surface of the separation layer 40, wherein, the material of the conductive layer 41 can be
Copper, the material of dielectric layer 30 can be silica, in order to prevent copper from diffusing in dielectric layer 30, generally
Need to form conductive separation layer 40 therebetween, wherein separation layer 40 can be Ta, TaN or both
With reference to.
Fig. 4 to Fig. 7 is refer to, nano particle 42 and CNT 60 are formed on the conductive layer 41
Step includes：
Mask layer 50 is formed on the surface of the dielectric layer 30, the conductive layer 41 is exposed；
With the mask layer 50 as mask, nano particle 42 is formed on the surface of the conductive layer 41；
After the nano particle 42 is formed, CNT 60 is formed on the surface of the conductive layer 41；
Using negative glue technology (lift-off), the mask layer 60 is removed.
Wherein, the material of the mask layer 60 is the materials, the nano particle such as BARC or unsetting carbon
42 materials are Co or Mo, and the nano particle 42 of formation can reduce contact resistance as catalyst.It is described
The length range of CNT 60 is 2nm~100nm, and the size range of the cross section of the CNT 60 is
1nm~5nm.
Fig. 8 is refer to, gate medium is formed on the dielectric layer 30, conductive layer 41 and the surface of CNT 60
Layer 70, the material of the gate dielectric layer 70 is HfO2Or Al2O3。
Fig. 9 to Figure 11 is refer to, the forming step of the metal gates 80 includes：
Metal gates 80 are formed on the surface of the gate dielectric layer 70, the metal gates 80 cover the carbon and receive
The top of mitron 60, as shown in Figure 9；
The metal gates 80 are ground using chemical mechanical milling tech, expose the CNT
60 top, as shown in Figure 10；
Treatment is etched back to the metal gates 80 using technique is etched back to, makes the CNT 60
Atop part stretch out the surface of the metal gates 80, as shown in figure 11.
Then, Figure 12 to Figure 14 is refer to, the forming step of described second single damascene structure includes：
In the metal gate, 80 surfaces sequentially form silicon nitride layer 20 and dielectric layer 30, the silicon nitride layer 20
Surface flushed with the top of the CNT 60 for stretching out；
The dielectric layer 30 is etched, groove is formed, etching stopping is in the silicon nitride layer 20, and the groove is sudden and violent
Expose the top of the CNT 60, the top of the CNT 60 can be cleaned；
Conductive layer 41, the top phase of the conductive layer 41 and the CNT 60 are filled in the groove
Even.
Likewise, because the material of conductive layer 41 is copper, the material of dielectric layer 30 is silica, in order to
The diffusion of copper is prevented, it is necessary to form separation layer 40 between conductive layer 41 and dielectric layer 30, wherein, isolation
The material of layer 40 can be TaN or Ta, doped with Co or Mo, second single damascene structure every
Being included in absciss layer 40 can also reduce contact resistance doped with Co or Mo.Wherein, the separation layer 40 exists
Formed under vacuum condition, make the vacuum ranges in the CNT 60 be 0.01Torr~50Torr.
The material of the conductive layer 41 includes Zr, V, Nb, Ta, Cr, Mo, W, Fe, Co, Pd, Cu, Al, Ga, In,
The combination of Ti, TiN, TaN, diamond or more material.Wherein, first single damascene structure and the second list are big
Ma Shige structures can be as the source-drain electrode of device.
After second single damascene structure is formed, in H2Or N2The high temperature anneal is carried out under environment, is made
The conductive layer 41 or separation layer 41 at the two ends of the CNT 60 have arcuate projection, and the high temperature is moved back
The temperature range of fire is 600 degrees Celsius to 1200 degrees Celsius, and the time range of high annealing is 10 seconds~120
Minute, Figure 15 is refer to, after the high temperature anneal, conductive layer 41 or separation layer 41 are in CNT 60
Two ends can form arcuate projection such that it is able to improve the opening speed of raceway groove.Wherein, CNT 60
Internal cross-sectional structure may be referred to Figure 16.
In the another aspect of the present embodiment, it is also proposed that a kind of vertical vacuum sealing carbon nanotube field-effect crystal
Pipe, using the manufacture method preparation of vertical vacuum sealing carbon nanotube field-effect transistor as described above
Into, including：Semiconductor substrate, first single damascene structure, CNT, gate dielectric layer, metal gate
Pole and second single damascene structure, wherein, described first single damascene structure is formed in the semiconductor
On substrate, the conductive layer surface in described first single damascene structure is formed with nano particle, and the carbon is received
The two ends of mitron connect conductive layer and second single Damascus knot in described first single damascene structure respectively
Conductive layer in structure, the gate dielectric layer is formed in the surface of the CNT and dielectric layer, the metal
Grid is formed in the surface of the gate dielectric layer, and single big positioned at described first single damascene structure and second
Between Ma Shige structures.
Additionally, energy band schematic diagram when the vertical vacuum sealing carbon nanotube field-effect transistor for being formed works can
To refer to Figure 17, it is seen then that the vertical vacuum sealing carbon nanotube field-effect transistor of formation electronics when opening
Or vacancy from source electrode move to drain electrode can band migration distance it is shorter, make the performance of whole device more preferably.
To sum up, in vertical vacuum sealing carbon nanotube field-effect transistor provided in an embodiment of the present invention and its system
Make in method, nano particle is formed as catalyst in conductive layer surface, be subsequently formed CNT, gate medium
Layer is contacted with source-drain electrode, and CNT is sealed in into vacuum environment, so as to be subsequently formed carbon nano field-effect
Device operating voltages can be reduced after transistor, device service life and other performance is improved.
The preferred embodiments of the present invention are above are only, any restriction effect is not played to the present invention.Appoint
What person of ordinary skill in the field, is not departing from the range of technical scheme, to the present invention
The technical scheme and technology contents of exposure make any type of equivalent or modification etc. variation, belong to without departing from
The content of technical scheme, still falls within protection scope of the present invention.
Claims (20)
1. a kind of manufacture method of vertical vacuum sealing carbon nanotube field-effect transistor, it is characterised in that bag
Include step：
Semiconductor substrate is provided, first single damascene structure is formed with the semiconductor substrate, it is described
First single damascene structure includes dielectric layer and conductive layer, and the conductive layer is formed in the dielectric layer,
The dielectric layer exposes the conductive layer；
Nano particle is formed in the conductive layer surface；
Multiple spaced CNTs are formed on the conductive layer；
Gate dielectric layer is formed in the dielectric layer, conductive layer and carbon nano tube surface；
Metal gates are formed on the gate dielectric layer surface, the atop part of the CNT stretches out the gold
Belong to the surface of grid；
Second single damascene structure, the top of the CNT and institute are formed on the metal gates surface
The conductive layer stated in second single damascene structure is connected.
2. the manufacture method of vacuum sealing carbon nanotube field-effect transistor as claimed in claim 1 vertical,
Characterized in that, the forming step of described first single damascene structure includes：
Silicon nitride layer and dielectric layer are sequentially formed on the semiconductor substrate；
The dielectric layer is etched, groove is formed, etching stopping is in the silicon nitride layer；
The conductive layer is filled in the groove.
3. the manufacture method of vacuum sealing carbon nanotube field-effect transistor as claimed in claim 2 vertical,
Characterized in that, before forming the conductive layer in the groove, be initially formed in the groove one layer every
Absciss layer, the conductive layer is formed in the insulation surface.
4. the manufacture method of vacuum sealing carbon nanotube field-effect transistor as claimed in claim 3 vertical,
Characterized in that, the separation layer is TaN or Ta.
5. the manufacture method of vacuum sealing carbon nanotube field-effect transistor as claimed in claim 1 vertical,
Characterized in that, the forming step of described second single damascene structure includes：
Sequentially form silicon nitride layer and dielectric layer on the metal gates surface, the surface of the silicon nitride layer with
Flushed at the top of the CNT for stretching out；
The dielectric layer is etched, groove is formed, etching stopping exposes in the silicon nitride layer, the groove
The top of the CNT；
Conductive layer is filled in the groove, the conductive layer is connected with the top of the CNT.
6. the manufacture method of vacuum sealing carbon nanotube field-effect transistor as claimed in claim 5 vertical,
Characterized in that, before forming the conductive layer in the groove, be initially formed in the groove one layer every
Absciss layer, the separation layer is formed under vacuum, and the conductive layer is formed in the insulation surface.
7. the manufacture method of vacuum sealing carbon nanotube field-effect transistor as claimed in claim 6 vertical,
Characterized in that, the separation layer is TaN or Ta, doped with Co or Mo.
8. the manufacture method of vacuum sealing carbon nanotube field-effect transistor as claimed in claim 1 vertical,
Characterized in that, the dielectric layer is silica.
9. the manufacture method of vacuum sealing carbon nanotube field-effect transistor as claimed in claim 1 vertical,
Characterized in that, the step of nano particle and CNT are formed on the conductive layer includes：
Mask layer is formed in the dielectric layer surface, the conductive layer is exposed；
With the mask layer as mask, nano particle is formed in the conductive layer surface；
After the nano particle is formed, CNT is formed in the conductive layer surface；
Using negative glue technology, the mask layer is removed.
10. the manufacture method of vacuum sealing carbon nanotube field-effect transistor as claimed in claim 9 vertical,
Characterized in that, the material of the mask layer is BARC or unsetting carbon.
The manufacture method of 11. vertical vacuum sealing carbon nanotube field-effect transistors as claimed in claim 9,
Characterized in that, the nano particle material is Co or Mo.
The manufacture method of 12. vertical vacuum sealing carbon nanotube field-effect transistors as claimed in claim 1,
Characterized in that, the gate dielectric layer material is HfO2Or Al2O3。
The manufacture method of 13. vertical vacuum sealing carbon nanotube field-effect transistors as claimed in claim 1,
Characterized in that, the forming step of the metal gates includes：
Metal gates are formed on the gate dielectric layer surface, the metal gates cover the top of the CNT
Portion；
The metal gates are ground using chemical mechanical milling tech, expose the CNT
Top；
Treatment is etched back to the metal gates using technique is etched back to, makes the part of the CNT
The surface of the metal gates is stretched out at top.
The manufacture method of 14. vertical vacuum sealing carbon nanotube field-effect transistors as claimed in claim 1,
Characterized in that, after second single damascene structure is formed, in H2Or N2High annealing is carried out under environment
Treatment, making the conductive layer at the CNT two ends has arcuate projection.
The manufacture method of 15. vertical vacuum sealing carbon nanotube field-effect transistors as claimed in claim 14,
Characterized in that, the temperature range of the high annealing is 600 degrees Celsius to 1200 degrees Celsius.
The manufacture method of 16. vertical vacuum sealing carbon nanotube field-effect transistors as claimed in claim 14,
Characterized in that, the time range of the high annealing is 10 seconds~120 minutes.
The manufacture method of 17. vertical vacuum sealing carbon nanotube field-effect transistors as claimed in claim 1,
Characterized in that, the vacuum ranges in the CNT are 0.01Torr~50Torr.
The manufacture method of 18. vertical vacuum sealing carbon nanotube field-effect transistors as claimed in claim 1,
Characterized in that, the length range of the CNT is 2nm~100nm, the CNT cross section
Size range is 1nm~5nm.
The manufacture method of 19. vertical vacuum sealing carbon nanotube field-effect transistors as claimed in claim 1,
Characterized in that, the material of the conductive layer includes Zr, V, Nb, Ta, Cr, Mo, W, Fe, Co, Pd, Cu, Al,
The combination of Ga, In, Ti, TiN, TaN, diamond or more material.
20. a kind of vertical vacuum sealing carbon nanotube field-effect transistors, using in such as claim 1 to 19
The manufacture method of the vertical vacuum sealing carbon nanotube field-effect transistor described in any one is prepared from, and it is special
Levy and be, including：Semiconductor substrate, first single damascene structure, CNT, gate dielectric layer, gold
Category grid and second single damascene structure, wherein, described first single damascene structure is formed in described half
On conductor substrate, the conductive layer surface in described first single damascene structure is formed with nano particle, described
The two ends of CNT connect conductive layer and second single damascene in described first single damascene structure respectively
Conductive layer in leather structure, the gate dielectric layer is formed in the surface of the CNT and dielectric layer, described
Metal gates are formed in the surface of the gate dielectric layer, and positioned at described first single damascene structure and second
Between single damascene structure.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510981315.3A CN106910687B (en) | 2015-12-23 | 2015-12-23 | Vertical vacuum sealing carbon nanotube field-effect transistor and its manufacturing method |
| TW105118033A TWI569314B (en) | 2015-12-23 | 2016-06-07 | A vertical vacuum sealed carbon nanotube transistor and method for preparing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510981315.3A CN106910687B (en) | 2015-12-23 | 2015-12-23 | Vertical vacuum sealing carbon nanotube field-effect transistor and its manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106910687A true CN106910687A (en) | 2017-06-30 |
| CN106910687B CN106910687B (en) | 2019-11-26 |
Family
ID=58608366
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510981315.3A Active CN106910687B (en) | 2015-12-23 | 2015-12-23 | Vertical vacuum sealing carbon nanotube field-effect transistor and its manufacturing method |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN106910687B (en) |
| TW (1) | TWI569314B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108258044B (en) * | 2016-12-28 | 2020-12-15 | 上海新昇半导体科技有限公司 | Neuron transistor structure and preparation method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1638066A (en) * | 2004-01-07 | 2005-07-13 | 国际商业机器公司 | Vertical carbon nanotube field effect transistor |
| CN1720606A (en) * | 2002-11-29 | 2006-01-11 | 日本电气株式会社 | Semiconductor device and manufacture method thereof |
| US20060278901A1 (en) * | 2003-01-24 | 2006-12-14 | Carlos Dangelo | In-chip structures and methods for removing heat from integrated circuits |
| CN1926680A (en) * | 2004-02-26 | 2007-03-07 | 国际商业机器公司 | Integrated circuit chip utilizing carbon nanotube composite interconnection vias |
| US20130228933A1 (en) * | 2011-08-31 | 2013-09-05 | Applied Materials, Inc. | BEOL Interconnect With Carbon Nanotubes |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201538340A (en) * | 2014-04-10 | 2015-10-16 | Univ Nat Taiwan | Flexible and stretchable graphene composite film and preparing method of the same |
-
2015
- 2015-12-23 CN CN201510981315.3A patent/CN106910687B/en active Active
-
2016
- 2016-06-07 TW TW105118033A patent/TWI569314B/en active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1720606A (en) * | 2002-11-29 | 2006-01-11 | 日本电气株式会社 | Semiconductor device and manufacture method thereof |
| US20060278901A1 (en) * | 2003-01-24 | 2006-12-14 | Carlos Dangelo | In-chip structures and methods for removing heat from integrated circuits |
| CN1638066A (en) * | 2004-01-07 | 2005-07-13 | 国际商业机器公司 | Vertical carbon nanotube field effect transistor |
| CN1926680A (en) * | 2004-02-26 | 2007-03-07 | 国际商业机器公司 | Integrated circuit chip utilizing carbon nanotube composite interconnection vias |
| US20130228933A1 (en) * | 2011-08-31 | 2013-09-05 | Applied Materials, Inc. | BEOL Interconnect With Carbon Nanotubes |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI569314B (en) | 2017-02-01 |
| CN106910687B (en) | 2019-11-26 |
| TW201724222A (en) | 2017-07-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Zhang et al. | III–V nanowire transistors for low-power logic applications: a review and outlook | |
| US10115788B2 (en) | Semiconductor devices with horizontal gate all around structure and methods of forming the same | |
| Kim et al. | Demonstration of complementary ternary graphene field-effect transistors | |
| CN103325836B (en) | A kind of graphene field effect transistor and preparation method thereof | |
| JP2014508396A (en) | Transistor device, integrated circuit, and manufacturing method | |
| US8022393B2 (en) | Lithographic process using a nanowire mask, and nanoscale devices fabricated using the process | |
| CN107851664A (en) | Technology for the sub- fin electric leakage of controlling transistor | |
| CN104835840B (en) | Super steep averagely subthreshold amplitude of oscillation nanowire tunneling field-effect transistor and preparation method | |
| KR102311607B1 (en) | Vertical channel transistors fabrication process by selective subtraction of a regular grid | |
| Dragoman et al. | 2D materials nanoelectronics: new concepts, fabrication, characterization from microwaves up to optical spectrum | |
| Zhai et al. | High-Performance Vertical Gate-All-Around Silicon Nanowire FET With High-$\kappa $/Metal Gate | |
| CN110534563A (en) | A kind of transistor and preparation method thereof with autoregistration feedback grid | |
| Nasr et al. | Seamless Fabrication and Threshold Engineering in Monolayer MoS2 Dual‐Gated Transistors via Hydrogen Silsesquioxane | |
| US9240552B2 (en) | Carbon nanotube semiconductor devices and deterministic nanofabrication methods | |
| CN106910687A (en) | Vertical vacuum sealing carbon nanotube field-effect transistor and its manufacture method | |
| CN104241334A (en) | Junctionless transistor | |
| Froberg et al. | Heterostructure barriers in wrap gated nanowire FETs | |
| TW201347198A (en) | Field effect transistor and method of fabricating the same | |
| Xie et al. | Demonstration of Germanium Vertical Gate-All-Around Field-Effect Transistors Featured by Self-Aligned High-κ Metal Gates with Record High Performance | |
| TWI628703B (en) | Gate-all-around complementary nanowire device with iii-v quantum well transistor, germanium junctionless transistor and method for making the same | |
| CN102376625B (en) | Semiconductor device and manufacturing method thereof | |
| Nashed et al. | Ultra-high mobility in dielectrically pinned CVD graphene | |
| CN103928342B (en) | A kind of silicon nanowires tunneling field-effect transistor and preparation method thereof | |
| Zhang et al. | Optimization of Structure and Electrical Characteristics for Four-Layer Vertically-Stacked Horizontal Gate-All-Around Si Nanosheets Devices., 2021, 11, 646 | |
| del Moral et al. | CMOS compatible manufacturing of a hybrid SET-FET circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |