CN104241334A - Junctionless transistor - Google Patents
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- CN104241334A CN104241334A CN201410375232.5A CN201410375232A CN104241334A CN 104241334 A CN104241334 A CN 104241334A CN 201410375232 A CN201410375232 A CN 201410375232A CN 104241334 A CN104241334 A CN 104241334A
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- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 50
- 239000013078 crystal Substances 0.000 claims abstract description 24
- 239000000463 material Substances 0.000 claims abstract description 10
- 230000005669 field effect Effects 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims description 35
- 239000000126 substance Substances 0.000 claims description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 10
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 6
- 229910052796 boron Inorganic materials 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 239000002070 nanowire Substances 0.000 abstract description 20
- 230000000694 effects Effects 0.000 abstract description 7
- 239000004065 semiconductor Substances 0.000 abstract description 5
- 230000002708 enhancing effect Effects 0.000 abstract description 2
- 230000005012 migration Effects 0.000 abstract 5
- 238000013508 migration Methods 0.000 abstract 5
- 239000012535 impurity Substances 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000002800 charge carrier Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
Abstract
The invention relates to the technical field of semiconductor field-effect transistors, in particular to a junctionless transistor. SiGe is adopted as materials of the junctionless transistor, the migration rate of electronics and a hole of the junctionless tube can be improved through the Ge, the Ge contents in a source region and a drain region of a device and a channel region are different, and the emission speed and the migration rate of the hole can be improved through the structure of the source and drain heterojunction. Meanwhile, the <100> crystal orientation capable of improving the hole migration rate is used as the crystal orientation of a transistor channel, the <100> crystal orientation and the effect of the heterojunction SiGe of enhancing the hole migration rate act together, and the problem that a nanowire transistor is too small in migration rate is solved.
Description
Technical field
The present invention relates to semiconductor field effect transistor technical field, particularly relate to a kind of nodeless mesh body pipe.
Background technology
Under the guidance of Moore's Law, the size of integrated circuit semiconductor apparatus is more and more less, but can not infinitely reduce, and to a certain degree will reach its physics limit narrowing down to, serious short-channel effect and gate leakage current will there will be.This will be a challenge to the validity of Moore's Law.But people actively find alternative shortening device size putting forward high performance method, people have been put into use hafnium the focus technically explored and have explored on new device structure, particularly the latter, novel device architecture will be direction and the trend of future semiconductor devices research and development.Silicon nano line transistor is a kind of new device structure, and it is one of optimum competitor wished under integrated circuit development course Figure 22 nanometer end node.The silicon nanowire structure transistor of Preliminary report has useful Sub-Threshold Characteristic, carrier mobility and closes step response both at home and abroad at present, can be good at suppressing short-channel effect.Than traditional body silicon planar device, the nanowire MOS FET of One Dimensional Quasi ballistic transport shows very strong minification advantage, and nano-wire transistor will show great potentiality to the set objective realizing semiconductor route map.Because expand the area that grid surround raceway groove, thus improve the ability controlling channel inversion electronics, reduce the short-channel effect of MOS device, avoid the reduction of the gate oxide thickness done required in reduction of device size simultaneously, thus also reduce the leakage current of grid.
After MOSFET characteristic size enters nanoscale, one of the principal element be lowered into as limiting device performance of carrier mobility.By at channel direction stress application, or adopting different Substrate orientation, when not changing device set size, the performance of MOSFET can be strengthened significantly.
First by people such as Jean-Pierre Colinge, in 2010, the article " Nanowire transistors without junctions " be published on Nature proposed nodeless mesh body pipe.Its operation principle is to use Uniform Doped substrate to replace source-drain structure, eliminates the structure of the original PN junction of transistor, reduces process complexity and improves the performance of transistor.Do not have in the transistor of PN junction this, the conductivity utilizing the on-off action of grid to control transistor reaches the effect of switch.During shutoff, gate voltage is less than threshold voltage, and intermediate channel part is depleted and turn off.During break-over of device, gate voltage is more than or equal to threshold voltage, and intermediate channel part is formed and can conduct electricity.Traditional nodeless mesh body pipe substrate is Uniform Doped and does not have the PN junction of source and drain, therefore it can save the technological process and ion diffuse process that form source and drain, greatly saves processing step and cost, as is shown in figs. la to ld.
For nodeless mesh body Guan Eryan, according to the report of document " Theory of the Junctionless Nanowire FET ", its electron mobility of nano wire nodeless mesh body pipe is just beyond 100cm
2/ Vs, still far below the 1300cm of general long ditch planar MOSFET
2the electron mobility of/Vs.Under same condition, the mobility of electronics is close to 3 times of hole mobility, therefore the hole mobility of general nodeless mesh body pipe and general long ditch planar MOSFET is respectively 33cm
2/ Vs and 433cm
2/ Vs, the former be the latter 1/10 less than.So the problem that class P type nodeless mesh body pipe mobility urgently to be resolved hurrily is too small.
Chinese patent (publication number: CN102082096A) describes a kind of preparation method of Ge or SiGe nano field-effect transistor, and the separator first on sinking to the bottom forms polysilicon gate; Then the gate dielectric layer of hafnium is formed, deposit SiGe film on gate dielectric layer again, after carrying out source and drain doping to SiGe film, lithographic definition goes out source-drain area figure, and anisotropic dry etch SiGe film, form SiGe side wall in polysilicon gate both sides, on grid length direction, two of SiGe side wall forms source region and drain region respectively simultaneously, is finally oxidized SiGe side wall, remove the oxide layer that surface is formed, obtain the SiGe nano wire of Ge nano wire or high Ge content.
Chinese patent (publication number: CN102822971A) describes a kind of technology based on embedding silicon Germanium source and drain stressor in the field-effect transistor of nano-groove, in one aspect, a kind of method of FET of manufacture comprises the following steps, the substrate of doping is provided, the substrate of described doping has dielectric, described dielectric arranges at least one silicon nanowires.One or more parts two of sheltering described nano wire make other parts of described nano wire expose, in the grown over portions epitaxial Germanium of the exposure of described nano wire, described epitaxial Germanium is made to form with the Si phase counterdiffusion in described nano wire the SiGe territory be embedded in described nano wire, compression strain is introduced in described SiGe territory in described nano wire, the substrate of described doping is used as the grid of described FET, the masked portion of described nano wire is used as the raceway groove of described FET, and the SiGe territory embedded is used as source electrode and the drain region of described FET.
Above-mentioned two pieces patent is not all recorded any about employing SiGe disclosed by the invention is as the material of source-drain area and channel region, with the technical characteristic of the carrier mobility and drive current that improve nodeless mesh body pipe.
Summary of the invention
In view of the above problems, the invention provides a kind of nodeless mesh body pipe.
A kind of nodeless mesh body pipe, it is characterized in that, comprise the grid be positioned on a SiGe substrate, the substrate being arranged in described gate bottom both sides is formed with source region and drain region, be formed with channel region between described source region and drain region, and described channel region is <100> along the crystal orientation on the direction in sensing drain region, described source region;
Wherein, described source region is different with the Ge content of described channel region with the Ge content in drain region, forms the field-effect transistor without knot by the source region of making in SiGe substrate, drain region and channel region and grid.
Above-mentioned transistor, wherein, in described source region and drain region, the chemical mol ratio of Ge is less than the chemical mol ratio of Ge in described channel region.
Above-mentioned transistor, wherein, described source region is identical with the chemical mol ratio of Ge in drain region.
Above-mentioned transistor, wherein, described grid is polysilicon gate, and the material of described gate oxide is silicon dioxide.
Above-mentioned transistor, wherein, described SiGe substrate is through the doped substrate of boron, and doping content is 5e19/cm
3.
Above-mentioned transistor, wherein, in described source region and drain region, the chemical mol ratio of Ge is 1%-100%.
Above-mentioned transistor, wherein, in described channel region, the chemical mol ratio of Ge is 1%-100%.
Above-mentioned transistor, wherein, described substrate is P type substrate.
Above-mentioned transistor, wherein, described grid comprises the gate oxide be positioned on substrate and the polysilicon gate be positioned on this gate oxide.
In sum, nodeless mesh body pipe disclosed by the invention, by the SiGe that the adopts Ge content different material as source-drain area and channel region, thus increase the mobility (because the lattice constant of SiGe is larger than Si) of charge carrier, and due to source-drain area different with the Ge content of channel region, thus make the energy gap of channel region and lattice constant all different from source-drain area, cavity speed is caused to increase, and cause there is horizontal compression further enhancing hole mobility, and the present invention uses <100> as transistor channel crystal orientation, thus further increase the hole mobility of nodeless mesh body pipe, reduce nodeless mesh body pipe dead resistance.
Accompanying drawing explanation
With reference to appended accompanying drawing, to describe embodiments of the invention more fully.But, appended accompanying drawing only for illustration of and elaboration, do not form limitation of the scope of the invention.
Fig. 1 a-1d is the fundamental diagram of nodeless mesh body pipe in background technology;
Fig. 2 is the structural representation of nodeless mesh body pipe in the embodiment of the present invention;
Fig. 3 is the electron energy band schematic diagram of nodeless mesh body pipe in the embodiment of the present invention.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment, the present invention is further illustrated, but not as limiting to the invention.
Core concept of the present invention adopts SiGe as the material of nodeless mesh body pipe, adding of Ge can improve the electronics of nodeless mesh body pipe and the mobility in hole, and the Ge content in the source region of device and drain region and channel region has difference, the structure of this source and drain heterojunction can improve emission rate and the mobility in hole, simultaneously, use can improve the crystal orientation of <100> crystal orientation as transistor channel of hole mobility, the effect acting in conjunction of hole mobility is strengthened with heterojunction SiGe, solve the problem that nano-wire transistor mobility is too small.
Comparing of the electrology characteristic of 13nm diameter heterogeneous SiGe nano wire PMOSFET and plane homogeneity SiGe channel device (width 1 μm), the former is 4.5 times of the latter, simultaneously the comparing of gm and Vg relation of 13nm diameter heterogeneous SiGe nano wire PMOSFET and plane homogeneity SiGe channel device (width 1 μm), all demonstrating the former in saturation region and linear zone increases by 4.5 times than the latter; If the p-MOSFET of stress Si0.8Ge0.2 adopts <100> crystal orientation as raceway groove crystal orientation, there is the reduction of the hole mobility raising of 25% and the dead resistance of 20% than the p-MOSFET of the stress Si0.8Ge0.2 in <110> raceway groove crystal orientation.And the latter has more superior mobility and threshold voltage to tumble (Threshold Voltage Roll-Off) performance characteristic than Si p-MOSFET.
Therefore can predict, if the nodeless mesh body pipe of SiGe heterojunction adopts <100> as raceway groove crystal orientation, then can significantly improve hole mobility and reduce dead resistance.
Embodiment 1:
As shown in Figure 2, the present embodiment relates to a kind of nodeless mesh body pipe, and a SiGe substrate is formed source region 4 and drain region 3, forms a channel region 5 between this source region 4 and drain region 3, the upper surface being positioned at channel region 5 is provided with a gate oxide 2, and the upper surface of this gate oxide 2 is coated with a grid 1; Preferably, the material of gate oxide 2 is silicon dioxide, and grid 1 is polysilicon gate; In an embodiment of the present invention, in advance this SiGe substrate has been carried out to the Uniform Doped of P type ionic impurity; As shown in Figure 2, this SiGe substrate is divided into 3 parts, separate respectively by black dotted lines, wherein, the Ge content being positioned at the source region 4 of leftmost side part is 30%, and the Ge content being positioned at middle channel region 5 is 70%, and the Ge content being positioned at drain region, the rightmost side 3 is 30%, namely in source region 4 and drain region 3, the chemical mol ratio of Ge is all less than the chemical mol ratio of Ge in channel region 5, and in source region 4 and drain region 3, the chemical mol ratio of Ge is identical.Concrete, when carrying out manufacture technics, wafer is selected the direction of <100> crystal orientation as channel region 5, this crystal orientation, channel region 5 is the direction (as shown in Figure 2 arrow points) that drain region 3 is pointed in source region 4, as long as <100> crystal orientation is defined as the direction of raceway groove in the step such as photoetching and domain after knowing the accurate location in crystal orientation and direction.
Device band structure such as Fig. 3 of the present invention shows, in the SiGe in source region 4 and drain region 3, the content of Ge is 30%, in the SiGe of channel region 5, the content of Ge is 70%, source region 4 and drain region 3 and the structure of the heterojunction in intermediate channel district 5 bring channel region 5 valence band on move, and valence band on move the emission rate in hole and mobility can be made to get a promotion.In an embodiment of the present invention, whole SiGe substrate is the substrate that Uniform Doped has boron, and the concentration of boron is 5e19/cm3.As shown in Figures 2 and 3.
As shown in Figure 2, SiGe, as the material forming source region 4, drain region 3 and channel region 5, because SiGe lattice constant is larger than Si, therefore can improve the mobility of charge carrier.Meanwhile, the channel region 5 in <100> crystal orientation can suppress the diffusion of drain region 3P type impurity, thus when device has just been opened or normally worked, can increase the concentration of drain region 3 impurity, reduces dead resistance.
Embodiment 2:
As shown in Figure 2, the present embodiment relates to a kind of nodeless mesh body pipe, and a SiGe substrate is formed source region 4 and drain region 3, forms a channel region 5 between this source region 4 and drain region 3, the upper surface being positioned at channel region 5 is provided with a gate oxide 2, and the upper surface of this gate oxide 2 is coated with a grid 1; Preferably, the material of gate oxide 2 is silicon dioxide, and grid 1 is polysilicon gate; In an embodiment of the present invention, in advance this SiGe substrate has been carried out to the Uniform Doped of P type ionic impurity; As shown in Figure 2, this SiGe substrate is divided into 3 parts, separate respectively by black dotted lines, wherein, the Ge content being positioned at the source region 4 of leftmost side part is 20%, and the Ge content being positioned at middle channel region 5 is 80%, and the Ge content being positioned at drain region, the rightmost side 3 is 20%, namely in source region 4 and drain region 3, the chemical mol ratio of Ge is all less than the chemical mol ratio of Ge in channel region 5, and in source region 4 and drain region 3, the chemical mol ratio of Ge is identical.Concrete, when carrying out manufacture technics, wafer is selected the direction of <100> crystal orientation as channel region 5, this crystal orientation, channel region 5 is the direction that drain region 3 is pointed in source region 4, as long as <100> crystal orientation is defined as the direction of raceway groove in the step such as photoetching and domain after knowing the accurate location in crystal orientation and direction.
Device band structure such as Fig. 3 of the present invention shows, in the SiGe in source region 4 and drain region 3, the content of Ge is 20%, in the SiGe of channel region 5, the content of Ge is 80%, source region 4 and drain region 3 and the structure of the heterojunction in intermediate channel district 5 bring channel region 5 valence band on move, and valence band on move the emission rate in hole and mobility can be made to get a promotion.In an embodiment of the present invention, whole SiGe substrate is the substrate that Uniform Doped has boron, and the concentration of boron is 5e19/cm
3.As shown in Figures 2 and 3.
As shown in Figure 2, SiGe, as the material forming source region 4, drain region 3 and channel region 5, because SiGe lattice constant is larger than Si, therefore can improve the mobility of charge carrier.Meanwhile, the channel region 5 in <100> crystal orientation can suppress the diffusion of drain region 3P type impurity, thus when device has just been opened or normally worked, can increase the concentration of drain region 3 impurity, reduces dead resistance.
As the SiGe of substrate in zones of different, the content of its Ge is also different, Ge content chemistry mol ratio in source region 4 and drain region 3 is at 1%-100%, and the chemical mol ratio of Ge is identical in source region 4 and drain region 3, the Ge content chemistry mol ratio of channel region 5 is at 1%-100%, wherein in source region 4 and drain region 3, the chemical mol ratio of Ge is the chemical mol ratio of the Ge be less than in channel region 5, such structural design make the structure of the heterojunction of the right and left and intermediate channel part bring intermediate channel part valence band on move, valence band is moved the emission rate in hole and mobility are got a promotion.
In order to obtain the nodeless mesh body pipe of better effect, the polysilicon gate of this transistor is long is 35-45nm (such as 38nm, 40nm, 42nm and 45nm); Thickness is 70-80nm (such as 72nm, 75nm, 78nm and 80nm); In SiGe substrate, the length of channel region 5 is identical with the length of polysilicon gate as can be seen here, and silicon dioxide layer 2 thickness as gate oxide is 0.5-1.5nm (such as 0.8nm, 1nm, 1.2nm and 1.5nm), preferably 1nm; The width of this SiGe substrate is 15-25nm (such as 15nm, 18nm, 20nm or 25nm), and thickness is 5-15nm (such as 8nm, 10nm, 12nm and 15nm).
From above-described embodiment, SiGe heterojunction structure is applied in nodeless mesh body pipe, this transistor hole mobility and drive current can be improved, adopt <100> crystal orientation as transistor channel crystal orientation simultaneously, hole mobility can be significantly improved and reduce dead resistance, both combine by the present invention, thus substantially increase hole mobility and the drive current of nodeless mesh body pipe, and reduce dead resistance.
By illustrating and accompanying drawing, giving the exemplary embodiments of the ad hoc structure of embodiment, based on the present invention's spirit, also can do other conversion.Although foregoing invention proposes existing preferred embodiment, but these contents are not as limitation.
For a person skilled in the art, after reading above-mentioned explanation, various changes and modifications undoubtedly will be apparent.Therefore, appending claims should regard the whole change and correction of containing true intention of the present invention and scope as.In Claims scope, the scope of any and all equivalences and content, all should think and still belong to the intent and scope of the invention.
Claims (9)
1. a nodeless mesh body pipe, it is characterized in that, comprise the grid be positioned on a SiGe substrate, the substrate being arranged in described gate bottom both sides is formed with source region and drain region, be formed with channel region between described source region and drain region, and described channel region is <100> along the crystal orientation on the direction in sensing drain region, described source region;
Wherein, described source region is different with the Ge content of described channel region with the Ge content in drain region, forms the field-effect transistor without knot by the source region of making in SiGe substrate, drain region and channel region and grid.
2. transistor according to claim 1, is characterized in that, in described source region and drain region, the chemical mol ratio of Ge is less than the chemical mol ratio of Ge in described channel region.
3. transistor according to claim 1, is characterized in that, described source region is identical with the chemical mol ratio of Ge in drain region.
4. transistor according to claim 1, is characterized in that, described grid is polysilicon gate, and the material of described gate oxide is silicon dioxide.
5. transistor according to claim 1, is characterized in that, described SiGe substrate is through the doped substrate of boron, and doping content is 5e19/cm
3.
6. transistor according to claim 1, is characterized in that, in described source region and drain region, the chemical mol ratio of Ge is 1%-100%.
7. transistor according to claim 1, is characterized in that, in described channel region, the chemical mol ratio of Ge is 1%-100%.
8. transistor according to claim 1, is characterized in that, described substrate is P type substrate.
9. transistor according to claim 1, is characterized in that, described grid comprises the gate oxide be positioned on substrate and the polysilicon gate be positioned on this gate oxide.
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| CN201410375232.5A CN104241334A (en) | 2014-07-31 | 2014-07-31 | Junctionless transistor |
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| CN201410375232.5A CN104241334A (en) | 2014-07-31 | 2014-07-31 | Junctionless transistor |
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| CN111697048A (en) * | 2019-03-13 | 2020-09-22 | 北京大学 | Method for improving total dose irradiation resistance of FinFET device |
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