CN106847894B - 具有与栅极自对准的体扩散的ldmos器件 - Google Patents

具有与栅极自对准的体扩散的ldmos器件 Download PDF

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CN106847894B
CN106847894B CN201611074855.4A CN201611074855A CN106847894B CN 106847894 B CN106847894 B CN 106847894B CN 201611074855 A CN201611074855 A CN 201611074855A CN 106847894 B CN106847894 B CN 106847894B
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dwell
ldmos device
ndrift
gate
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CN106847894A (zh
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H·L·爱德华兹
B·胡
J·R·托德
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Texas Instruments Inc
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Abstract

本发明公开一种具有与栅极自对准的体扩散的LDMOS器件。一种横向扩散金属氧化物半导体(LDMOS)器件(200)包括其上具有p外延层(115)的衬底(105)，在p外延层中的p体区(140)，以及在p体内以提供漏极延伸区的n漂移(NDRIFT)区(120)。栅极堆叠包括在p体区中的沟道区上方与具有NDRIFT区的结的相应侧相邻并且在所述相应侧上的栅极介电层(122)。图案化栅极电极(123)在栅极电介质上。DWELL区(130)在p体区内。源极区(148)在DWELL区内，并且漏极区(145)在NDRIFT区(120)内。LDMOS器件的有效沟道长度(Leff)为75nm至150nm，其显示DWELL注入，所述DWELL注入利用栅极电极的边缘以描绘DWELL离子注入的边缘，使得DWELL区与栅极电极自对准。

Description

具有与栅极自对准的体扩散的LDMOS器件
技术领域
所公开的实施例涉及横向扩散金属氧化物半导体(LDMOS)器件。
背景技术
由于DC-DC转换器被扩展到下一代功率转换器产品，因而需要增加开关频率以减小外部无源部件诸如电感器的尺寸，同时在其集成功率场效应晶体管(FET)诸如LDMOS器件中保持低功耗。在LDMOS器件中，横向布置漏极以允许电流横向流动，并且在沟道和漏极之间***漂移区，以将高的漏极提供到源极击穿电压。这涉及减小功率FET的开关寄生Qgate和Cdrain，同时也减小导通状态电阻。
Qgate是在漏极基本上处在在电源轨之间的开关转换期间导通功率FET栅极所需的电荷。Qgate导致(1)功率损耗，因为该开关电荷在开关过程期间没有恢复，以及(2)降低的面积利用率，因为驱动大面积功率FET的栅极所需的电路***可占据芯片面积的很大部分。Cdrain是漏极电容，其决定每次开关转换时开关损耗多少电荷。RSP是功率FET的面积标准化导通状态电阻。常规地，新的集成功率(例如，线性BiCMOS(LBC))技术将减小RSP，使得可以在减小的芯片面积处获得功率开关的总导通电阻，因此降低了产品成本。
发明内容
提供本发明内容以便以简化形式介绍所公开概念的简要选择，所公开的概念在下面包括所提供的附图的具体说明中进一步描述。本发明内容并非旨在限制所要求保护的主题的范围。
所公开的实施例包括横向扩散金属氧化物半导体(LDMOS)器件和用于形成此类器件的工艺，其使得能够减小寄生Qgate、Cdrain和面积标准化导通状态电阻(RSP)。如本文所用，LDMOS器件与扩散金属氧化物半导体(DMOS)器件同义。常规的n-LDMOS功率器件在工艺流程初期使用掩蔽的(masked)硼体注入然后使用扩散这两者，以在添加多晶硅栅极和浅p型阱和浅n型阱(SPWELL和SNWELL)分别完成LDMOS器件的p型体区和形成n型源极延伸部之前，形成在本文中所称的DWELL区。历史上，DWELL工艺使用长炉退火和/或MeV(或近MeV)硼掩埋层(PBL)注入，以在沟道中实现横向分级的p体掺杂分布，其产生加速电子移动的内建电场，从而提高LDMOS器件的电流驱动能力。
此外，认为在常规工艺流程早期的DWELL工艺的位置产生了DWELL扩散与栅极电极(通常为多晶硅栅极)的边缘之间的未对准，这也防止了减小LDMOS器件的有效沟道长度。如本文所用，所公开的n沟道LDMOS器件的有效沟道长度(LEFF)是指在栅极电介质上方的栅极电极下的源极和漏极之间的半导体(例如，硅)表面的净p型区(多数载流子)的宽度(或在该表面的约100埃内，其是形成反型层的量子力学基态的宽度，无论宽度最窄的地方在哪里)，其在所有零器件端子电压处指定。总而言之，长DWELL扩散时间、来自高能量PBL注入的横向蔓延以及DWELL掩模和栅极电极材料(例如，多晶硅)之间的光刻未对准变化导致LEFF为至少200nm，通常为≥500nm(0.5μm)。长的最小LEFF(例如，为≥0.5μm)在栅极电容、RSP、电流驱动(Idrive)和Idlin上设置下限(最小)，所述电流驱动(Idrive)也称为IDsat(饱和区中的漏极电流)，并且所述Idlin为LDMOS器件的线性区(从中计算RDSon和RSP)的漏极电流。
所公开的实施例提供一种LDMOS设计和包括DWELL工艺的相关联的工艺流程，该DWELL工艺包括至少DWELL p型(例如，硼)注入，通过使栅极电极(例如，多晶硅栅极)的至少一个边缘包括在用于DWELL的光掩模开口中，所述DWELL p型(例如，硼)注入与栅极电极自对准，使得栅极电极描绘DWELL注入的边缘。这使得LDMOS器件的LEFF显著地减小(例如，LEFF为75nm至150nm)为比常规LDMOS的LEFF小至少约2倍，以便提供下一代功率场效应晶体管(FET)性能。
附图说明
现在参照附图，附图不必按比例绘制，在附图中：
图1是示出根据示例实施例的用于形成具有与栅极电极自对准的DWELL区的所公开的LDMOS器件的示例方法中的步骤的流程图。
图2A是示出根据示例实施例的具有显示DWELL注入的DWELL区的示例LDMOS器件的横截面图，DWELL注入利用栅极电极的至少一个边缘描绘DWELL离子注入的边缘，使得DWELL区与栅极电极自对准。
图2B是根据示例实施例的具有显示DWELL注入的DWELL区的示例LDMOS器件的顶视图，DWELL注入利用栅极电极的边缘描绘DWELL离子注入的边缘，使得DWELL区与栅极电极自对准，其中栅极电极处于跑道型配置中。
图3示出根据示例实施例的具有显示DWELL注入的DWELL区的所公开的LDMOS器件(没有硅的局部氧化(LOCOS)层)的平面版本，DWELL注入利用栅极电极的至少一个边缘描绘DWELL离子注入的边缘，使得DWELL区与栅极电极自对准。
图4A示出针对所公开的LDMOS器件与已知的LDMOS器件的模拟VGate与QGate曲线图，图4B示出针对所公开的LDMOS器件与已知的LDMOS器件的RDS.QGtot的模拟数据，并且图4C示出针对所公开的LDMOS器件与已知的LDMOS器件的RSP的模拟数据。
具体实施方式
参考附图描述示例实施例，其中类似的附图标号用于指代相似或等同元件。说明的动作或事件的顺序不应被认为是限制性的，因为一些动作或事件可以以不同的顺序发生和/或与其他动作或事件同时发生。此外，根据本公开，可能不需要一些说明的动作或事件来实现方法。
另外，如在没有进一步限制的情况下在本文中使用的术语“联接(couple)到…”或“与…联接”(等等)旨在描述间接或直接电连接。因此，如果第一装置“联接”到第二装置，则该连接能够通过其中在路径中仅存在寄生的直接电连接，或通过经由包括其他装置和连接件的中间项的间接电连接。对于间接联接，中间项通常不修改信号的信息，但可调节其电流电平、电压电平和/或功率电平。
所公开的实施例包括具有新的DWELL工艺流程的LDMOS制造工艺，以及来源于该工艺的LDMOS器件，LDMOS器件通常具有仅75nm至150nm的LEFF。DWELL工艺移动到刚好在栅极堆叠形成之后(而不是常规上在栅极堆叠形成之前)，并且是在BiCMOS工艺的部分(仅针对公开的方法的示例被描述为BiCMOS工艺的部分)的条件下，在使用与NLDD处理类似的处理的CMOS轻掺杂漏极(LDD)环路(通常包括NLDD2、NLDD、PLDD、PLDD2注入和激活退火)之前。在一个或多个Dwell注入之后能够添加专用的(任选的)DWELL快速热退火(RTA)工艺以(1)激活一种或多种DWELL掺杂剂，以及(2)轻微驱动DWELL p型掺杂剂，以实现用于LDMOS器件的更好的导通状态击穿电压(BVII)和更可控的电压阈值(VT)。
图1是示出根据示例实施例的用于形成具有与栅极电极自对准的DWELL区的公开的LDMOS器件的示例方法100中的步骤的流程图。图2A是示出根据示例实施例的具有显示DWELL注入的DWELL区130的示例LDMOS器件的横截面图，DWELL注入利用栅极电极的至少一个边缘描绘DWELL离子注入的边缘，使得DWELL区显示与栅极电极自对准，其中自对准的证据包括LDMOS器件的Leff仅为75nm至150nm。使用BiCMOS工艺流程描述方法100，如本领域已知的，BiCMOS工艺流程结合双极性技术和CMOS技术。虽然本文描述了n沟道LDMOS晶体管，但是本领域的普通技术人员清楚的是，通过用p掺杂区代替n掺杂区来使用该信息形成p沟道LDMOS晶体管，并且反之亦然。
步骤101包括提供其上具有p外延层115的衬底110。p外延层115可以是约15μm至40μm厚。该工艺能够包括在衬底上形成第一外延层，形成毯覆式(blanket)n+掩埋层(NBL)111，并且然后在NBL 111上形成第二外延层。衬底110一般为p+衬底或p-衬底，通常是从1×1016到1×1019cm-3的硼掺杂，并且p外延层115能够具有从3×1014cm-3到3×1016cm-3的掺杂水平。衬底110和p外延层115两者均能够包括硅，并且还能够包括其他材料。
所公开的LDMOS器件能够包括隔离结构。例如，外部n型槽能够以几种方式形成。深沟槽(DT)能够具有任选的电介质衬垫和NBL，DEEPN和NBL，DNWELL和NBL以及浅n阱(SNW)、BISO和NBL。BISO是在NBL 111的边缘处的第二外延工艺(在两外延工艺中)之前执行的磷注入(但是在NBL炉驱动之后，NBL炉驱动将NBL 111更深地扩散到半导体诸如Si中)。BISO向上扩散到第二p外延中，使得能够与例如SNW建立n槽连接(因此避免使用有时期望的DEEPN)。在所有这些情况下，NBL 111形成n型槽的底部，并且另一元件(DT，DEEPN等)形成n槽的向上连接到顶部半导体表面的垂直壁，这种顶部Si表面具有n+掺杂(来自NSD)、硅化物和接触。
步骤102包括注入毯覆式PBL注入然后使PBL注入退火以在p外延115中的NBL 111上方形成p体区140的任选步骤。PBL注入能够在400keV至3MeV的能量下使用从1×1012cm-2至1×1013cm-2的硼剂量。代替PBL注入，能够另选地增加p外延层115中的掺杂水平，以控制p体区140中的背景硼掺杂水平。
步骤103包括在p体区140的部分内形成包括NDRIFT离子注入的n漂移(NDRIFT)区120。NDRIFT区120为LDMOS器件200提供漏极延伸区。对于LDMOS器件200，接着进行局部氧化工艺以形成LOCOS层137。然而，如图3所示，在另一个实施例中，LDMOS器件是缺少LOCOS层137的“平面”器件。
此外，在步骤103之后，还可以形成SNW和浅p阱(SPW)。在图2A中被示为SPW1 149的区是SPW的部分，SPW能够来自利用用于形成CMOS逻辑和5V NMOS体扩散的常规浅p体注入的BiCMOS工艺，CMOS逻辑和5V NMOS体扩散两者均可以针对LDMOS器件200任选地被注入(通常被注入有多个注入以提供不同的注入能量)，以形成用于LDMOS器件的深p体掺杂区。由SPW1149提供的体掺杂增加了基极掺杂水平，以抑制由n+源极-p体-n+漏极形成的寄生横向NPN双极性。这种寄生NPN双极性能够限制LDMOS器件200的高电流工作，因为其能够形成到安全工作区域(SOA)的边界。任选的SNW在图2A中被示为SNWell 155。
步骤102(PBL)、步骤103(NDRIFT)中的注入以及SNW和SPW注入通常能够以任何顺序执行。该方法还能够包括在恢复引发的晶格损伤的注入的所有这些注入之后的RTA损伤退火。
步骤104包括形成栅极堆叠，其包括在p体区140上方形成栅极介电层122，其邻近于p体区140和NDRIFT区120之间的结的相应侧并且在p体区140和NDRIFT区120之间的结的相应侧上，然后在栅极介电层122上形成图案化栅极电极123。栅极介电层122可以是包括约10至15nm厚的氧化硅的5V栅极电介质。还可以使用与约3nm的二氧化硅一样薄的栅极电介质，或使用比二氧化硅稍薄但具有比二氧化硅的大约为3.9的介电常数要高的介电常数的氮氧化硅(SION))栅极电介质。多晶硅是用于栅极电极123的一个示例栅极电极材料。然而，金属栅极或基于CMOS的替换栅极工艺也能够用于提供栅极电极123。
步骤105包括至少第一后栅极阱离子注入，第一后栅极阱离子注入包括进入到p体区140中的p型掺杂剂(DWELL离子注入)以形成DWELL区130。步骤105能够包括全部处于不同能量的2个或更多个p型DWELL离子注入。一个或多个DWELL离子注入与栅极电极123(例如，多晶硅)的至少一个边缘自对准，这使由所公开的LDMOS器件提供的短Leff(例如，75nm至150nm)能够通过具有包括在用于DWELL离子注入的光掩模开口中的栅极电极的至少一个边缘使得栅极电极123描绘出DWELL离子注入的边缘并且作为结果DWELL与栅极自对准。包围用于源极和集成背栅极区的栅极电极123开口的DWELL掩模开口以最小量暴露栅极电极123(诸如25nm至150nm，这取决于光刻设备的对准能力)，以确保DWELL注入被栅极电极123的一个或多个边缘掩蔽。
由所公开的LDMOS器件提供的短Leff(例如，75nm至150nm)是从顶视图图像可获得的特征签名，诸如通过使用掺杂分布的扫描电容显微镜图像或扫描扩展电阻显微镜图像获得的。在BiMOS工艺流程的情况下，具有与用于BiMOS IC上的MOS器件的PSD或PLDD2大约一样深的相对重的和陡峭分级的浅p型掺杂(来自自对准的DWELL离子注入)将是另一个特征签名。常规的DWELL掺杂将不仅进一步延伸到LDMOS沟道中，而且其将更均匀并且基本上更垂直地展开。又一个特征签名是当栅极电极为Dwell注入(例如具有跑道形栅极电极，参见图2B)提供2个掩模边缘时在栅极电极123的相应侧上的浅DWELL p型注入的掺杂对称性，这类似于具有用于S/D注入工艺的自对准栅极的常规MOS器件的源极和漏极中的对称掺杂。
DWELL p型注入能量可以类似于在BiCMOS工艺中用于硼PSD和PLDD2步骤的能量，并且剂量通常应足以横向形成沟道并抑制寄生体NPN效应。例如，可以使用这样的硼注入，即能量为20keV，剂量为8×1013cm-2至3.0×1014cm-2，诸如1.5×1014cm-2，并且倾斜角小于5度，诸如2度。然而，除了硼，DWELL p型注入也能够使用铟(In)。用于该注入的能量处于低能量以避免穿透所暴露的栅极电极123，诸如包括多晶硅。DWELL硼注入是垂直的或接近垂直(例如，2度倾斜)的并且剂量相对高(1.5×1014cm-2)，其两个特性被认为在抑制体NPN动作同时维持形成良好的沟道区方面是有利的。上述SPWELL注入在栅极处理之前允许SPW1区149提供p体掺杂的较深部分，这进一步抑制寄生NPN。
还能够添加任选的DWELL n型掺杂剂，诸如砷(或锑)，其中n型DWELL 135在图2A中示出，砷(或锑)注入和p型Dwell注入是以任何顺序。例如，剂量为4×1014cm-2至1.2×1015cm-2(例如，8×1014cm-2)，能量为4至30keV(例如，15keV)以及15度离子注入倾斜角的砷注入可以用于在一个具体实施例中形成n型DWELL 135，或者以例如45度(2或4个旋转)成角度的该注入中的一些或全部。约15keV的砷注入能量允许砷穿过邻近于栅极电极123的栅极电介质122(例如，当5V氧化物时)，并且还通过反掺杂降低其中的掺杂浓度，以便减少栅极引发的参数转变。15度左右的砷(或锑)注入角能够降低电压阈值(Vt)，而不减少DWELL p型注入剂量，使得能够同时改善Vt和控制寄生NPN的体掺杂。DWELL p型注入和任选的Dwell砷(或锑)注入能够使用相同的掩模。然而，NLDD注入(用于BiCMOS工艺流程)可以与仅包含p型注入的DWELL一起使用。
所公开的多晶硅栅极工艺的DWELL激活/驱动能够包括已经被包括在常规BiMOS工艺流程中的多晶硅氧化步骤，其在栅极图案化、栅极蚀刻和栅极光致抗蚀剂去除之后，是短暂的热氧化，所述短暂的热氧化轻微氧化多晶硅的侧壁，并形成“多晶硅裂口(polysiliconsmile)”，其是在多晶硅栅极的边缘处的栅极氧化物的轻微增厚。DWELL激活/驱动还能够包括RTA工艺以激活一个或多个Dwell掺杂剂并轻微横向扩展掺杂分布，这有助于形成良好限定的LDMOS器件沟道并抑制寄生体NPN双极性作用。例如，在一个具体实施例中可以使用在约1,000℃下持续1至4分钟的RTA。当栅极电极材料包括多晶硅时，n型源极-漏极注入(NSD)可以任选地与DWELL共同图案化以降低源极电阻并且改善多晶硅栅极n型掺杂。
侧壁间隔物138通常形成在栅极电极123的侧壁上。间隔物材料的薄层也任选地显示在栅极电极123的顶部上。在图2A中示出的栅极电极123的顶部上的间隔物材料可以存在或可以不存在。在一个实施例中，侧壁间隔物138包括氮化硅。示出了包括在间隔物138上方的金属前电介质(PMD)139。
步骤106包括在DWELL区130中形成n+源极(源极)区148，以及在NDRIFT区120中形成n+漏极(漏极)区145。通常随后进行接触(例如，任选的硅化物，PMD 139和通孔)和金属化处理，包括接触DWELL区130的到背栅极的接触142，到源极的接触143，到漏极的接触144，以及到栅极的接触147。
使用该公开的DWELL工艺和相关联的LDMOS布局，由于DWELL与栅极电极的一个或多个边缘自对准，如上所述，LDMOS器件的LEFF可以减小到低至75nm。减小的LEFF使得能够显著改善RSP和Qgate两者。LDMOS器件200还具有如图2A所示的其XD参数，其对应于NDRIFT区120的外边缘上的栅极电介质122的有源部分，该XD参数通常仅为200nm至300nm。先前的技术节点LDMOS器件具有约500nm至1,000nm的XD。因为更尖锐的DWELL掺杂，制造更尖锐的pn结，提供使用更尖锐的NDRIFT 120掺杂分布的机会，所以所公开的实施例减小了XD。由于该公开的特征使得一切更小，所以需注意，光刻对准通常变得更重要，使得所公开的DWELL处理的自对准性质通常变得更重要。
对于功率转换器应用，诸如在一个具体应用中用于半桥式降压DC/DC转换器，通常有三种不同类型的LDMOS器件。低侧LDMOS晶体管具有接地的源极和体区，因此此类LDMOS器件能够在p外延115中工作而没有任何隔离(即，没有深沟槽(DT)，没有NBL，没有BISO，以及没有DEEPN下沉槽(sinker))。另一个LDMOS器件是构建到n型槽中的ISO LDMOS晶体管。ISO端子是n槽，并且其能够与源极/背栅极区和漏极分开地偏置。又一个用于高侧应用的LDMOS器件与ISO LDMOS晶体管类似地构建，但是ISO和漏极电连接在一起(通常通过金属1(MET1))。对于这些类型的LDMOS器件中的每一个，需要增加开关频率以减小外部无源部件诸如电感器的尺寸，同时保持集成功率FET中的低功耗。这涉及在导通状态电阻RSP减小时减小功率FET的开关寄生Qgate和Cdrain，这些减小都由所公开的LDMOS器件提供。
图2B是根据示例实施例的具有显示DWELL注入的DWELL区130的示例LDMOS器件200’的顶视图，DWELL注入利用栅极电极123’的边缘描绘DWELL离子注入的边缘，使得DWELL区130与栅极电极123自对准，其中栅极电极123是跑道配置。隔离槽240被示出为框架化LDMOS器件200’，LDMOS器件200’如上所述能够包括NBL以及提供将p外延115的顶表面联接到NBL 111的垂直壁的n+下沉槽。被示为142a的背栅极/体接触区是在Dwell区130的表面处的集成背栅极接触。背栅极/体接触区142a能够通过添加用于CMOS区段的p+SD(PSD)注入而形成在DWELL区130内，p+SD(PSD)注入是非常重度(p+)的硼掺杂。一种布置具有在常规几何形状中的多个背栅极PSD条纹或正方形，其中NSD注入覆盖源极/背栅极区的未被PSD覆盖的区域以与源极148的低电阻接触。背栅极/体接触区142a允许p型体区(Dwell区130和p体140)通过硅化物层欧姆短接至n+源极148。
对于LDMOS器件200’，DWELL掩模被图案化，从而在两侧上的栅极电极123’上停止。通常期望避免将DWELL掩模开口延伸太远进入栅极电极123’中，以避免用p型DWELL注入反掺杂多晶硅。
图3示出根据示例实施例的具有显示DWELL注入的DWELL区130的所公开的LDMOS器件300(没有如图2A中所示的LOCOS层137)的平面版本，DWELL注入利用栅极电极的边缘描绘DWELL离子注入的边缘，使得DWELL区130与栅极电极123自对准。如上所述，DWELL掩模被图案化，在这种情况下，图案停止在跑道形状的两侧上的栅极电极123(例如，多晶硅)上。
用于CMOS电路***的p型源极-漏极注入(PSD)可以任选地被图案化以提供背栅极/体接触142a(邻近于NSD+DWELL区形成)，以减小寄生NPN的p体140的基极电阻，进一步抑制体NPN作用。DWELL掩模可以跨过背栅极/体接触142a任选地延伸，或者其可以邻近PSD边缘停止。PLDD2(用于形成5V PMOS的纯p型SD延伸注入)也可以任选地被添加到背栅极/体接触142a，从而任选地部分延伸到图2A中的n型DWELL 135中，以加强其中的p型体掺杂，从而进一步抑制寄生体NPN作用。
实例
通过以下具体实例进一步说明所公开的实施例，其不应以任何方式解释为限制本公开的范围或内容。
图4A示出针对与具有LOCOS层137的LDMOS器件200类似的所公开的LDMOS器件(示为“10V新LDMOS”)与已知的LDMOS器件(示为“已知的LDMOS 7V ISO LDMOS”)的模拟VGate与QGate曲线图。如上所述，已知的LDMOS器件在工艺早期(栅极之前)具有DWELL，其被认为产生DWELL扩散与多晶硅栅极的边缘之间的未对准，这导致LDMOS器件的LEFF为至少200nm，通常为≥500nm(0.5μm)。Qgate被示为通过所提供的短Leff(约100nm)和LOCOS层显著改善。
图4B示出针对所公开的LDMOS器件(示为“新LDMOS”)与已知的LDMOS器件的RDS.QGtot的模拟数据。RDS.QGtot被示为通过所公开的LDMOS器件大大减少。图4C示出针对所公开的LDMOS器件(再次示为“新LDMOS”)与已知的LDMOS器件的RSP的模拟数据。RSP被示为也通过所公开的LDMOS器件大大减少。这些参数比已知的LDMOS器件显著改善，同时还发现了保持LDMOS器件抵挡漏极电压的能力(即，不牺牲漏极-源极击穿电压(BVDSS))并维持低的结泄漏。
所公开的实施例能够用于形成半导体芯片，其可以集成到各种组装流程中以形成各种不同的器件和相关产品。半导体芯片可包括其中的各种元件和/或其上的各层，包括阻挡层、介电层、器件结构、有源元件和无源元件，包括源极区、漏极区、位线、基极、发射极、集电极、导电线、导电通孔等。此外，半导体芯片能够由包括双极性、绝缘栅双极性晶体管(IGBT)、CMOS、BiCMOS和MEMS的各种工艺形成。
本公开相关领域的技术人员将理解，在要求保护的发明的范围内，许多其他实施例和实施例的变型是可能的，并且在不脱离本公开的范围的情况下，可以对所描述的实施例做出进一步的添加、删除、替换和修改。

Claims (29)

1.一种形成横向扩散金属氧化物半导体器件即LDMOS器件的方法，其包括：
提供其上具有p外延层的衬底；
通过注入毯覆式p掩埋层注入物即PBL注入物在所述p外延层中形成p体区；
通过在所述p外延层中的所述p体区内注入n漂移离子注入物即NDRIFT离子注入物来形成n漂移区即NDRIFT区；
形成栅极介电层，其在所述p外延层的表面沟道区上方邻近于具有所述NDRIFT区的结的相应侧并且在具有所述NDRIFT区的结的相应侧上；
在所述栅极介电层上形成图案化栅极电极；
通过将包括p型掺杂剂的第一后栅极阱离子注入物注入到所述p外延层中的所述p体区来形成DWELL区，其中所述栅极电极的至少一个边缘被包括在用于所述第一后栅极阱离子注入物的光掩模开口中，使得所述栅极电极描绘出所述第一后栅极阱离子注入物的边缘；以及
在所述DWELL区中形成源极区，以及在NDRIFT区中形成漏极区。
2.根据权利要求1所述的方法，其中形成所述p体区进一步包括使所述PBL注入物退火。
3.根据权利要求1所述的方法，其进一步包括在形成所述源极区和所述漏极区之前在所述栅极电极的侧壁上形成侧壁间隔物。
4.根据权利要求1所述的方法，其中所述第一后栅极阱离子注入物包括硼，其具有在15KeV和30KeV之间的能量，小于5度的角度，以及在8×1013cm-2和3.0×1014cm-2之间的剂量。
5.根据权利要求1所述的方法，其进一步包括：通过注入包括n型掺杂剂的第二后栅极阱离子注入物在所述DWELL区中形成n型DWELL区。
6.根据权利要求5所述的方法，其中所述第二后栅极阱离子注入物包括砷，其具有从10KeV至30KeV的能量以及从4×1014cm-2至1.2×1015cm-2的剂量。
7.根据权利要求1所述的方法，其进一步包括形成隔离槽，其包括在形成所述NDRIFT区之前在所述p外延层中形成n+掩埋层即NBL，以及提供将所述p外延层的顶表面联接到所述NBL的垂直壁的n+下沉槽。
8.根据权利要求1所述的方法，其进一步包括在所述NDRIFT区的部分上方形成局部氧化层即LOCOS层，其中所述栅极电极形成在所述LOCOS层的至少一部分上。
9.根据权利要求1所述的方法，其中用于所述LDMOS器件的有效沟道长度即Leff为75nm至150nm。
10.一种横向扩散金属氧化物半导体器件即LDMOS器件，其包括：
衬底；
设置在所述衬底上的p外延层；
p体区，其设置在所述p外延层中；
n漂移区即NDRIFT区，其设置在所述p体区中以提供漏极延伸区；
栅极堆叠，其包括：
设置在所述p体区中的沟道区上方的栅极介电层，其中所述栅极介电层邻近于在所述p体区和所述NDRIFT区之间的结的相应侧并且在所述p体区和所述NDRIFT区之间的结的相应侧上；以及
设置在所述栅极介电层上方的栅极电极；
DWELL区，其设置在所述p体区中，其中所述DWELL区具有由所述栅极电极的第一边缘描绘出的第一边缘；
源极区，其设置在所述DWELL区中；以及
漏极区，其设置在所述NDRIFT区中。
11.根据权利要求10所述的LDMOS器件，其中所述衬底包括硅。
12.根据权利要求10所述的LDMOS器件，其进一步包括设置在所述栅极电极的侧壁上的侧壁间隔物。
13.根据权利要求10所述的LDMOS器件，其中所述栅极介电层包括氧化硅或氮氧化硅即SiON，并且其中所述栅极电极包括多晶硅。
14.根据权利要求10所述的LDMOS器件，其进一步包括隔离槽，所述隔离槽包括在所述p外延层中的n+掩埋层即NBL，以及提供将所述p外延层的顶表面联接到所述NBL的垂直壁的n+下沉槽。
15.根据权利要求10所述的LDMOS器件，其进一步包括在所述NDRIFT区的部分上方的局部氧化层即LOCOS层，其中所述栅极电极设置在所述LOCOS层的至少一部分上方。
16.根据权利要求15所述的LDMOS器件，其中所述LOCOS层通过所述NDRIFT区的部分与所述p体区和所述NDRIFT区之间的结分隔开。
17.根据权利要求10所述的LDMOS器件，其中所述LDMOS器件为平面器件。
18.根据权利要求10所述的LDMOS器件，其中所述栅极电极是以跑道型几何形状布置的。
19.根据权利要求10所述的LDMOS器件，其进一步包括在所述DWELL区的表面处的集成背栅极/体接触区。
20.根据权利要求10所述的LDMOS器件，其包括设置在所述NDRIFT区中的浅n型阱，其中所述漏极区设置在所述浅n型阱中。
21.根据权利要求20所述的LDMOS器件，其中所述栅极电极的第二边缘描绘出所述浅n型阱的边缘。
22.根据权利要求10所述的LDMOS器件，其包括在所述DWELL区中设置在所述源极区和所述DWELL区的所述第一边缘之间的n型DWELL区。
23.根据权利要求22所述的LDMOS器件，其中所述n型DWELL区的至少一部分被所述栅极堆叠重叠。
24.根据权利要求10所述的LDMOS器件，其包括至少部分地设置在所述p体区中但在所述NDRIFT区外部的浅p型阱。
25.根据权利要求24所述的LDMOS器件，其中所述DWELL区设置在所述浅p型阱的上方。
26.根据权利要求25所述的LDMOS器件，其中所述DWELL区通过所述p体区的部分与所述浅p型阱分开。
27.根据权利要求10所述的LDMOS器件，其中所述LDMOS器件的有效沟道长度在75nm和150nm之间。
28.根据权利要求27所述的LDMOS器件，其中所述有效沟道长度被限定在所述DWELL区的所述第一边缘与在所述NDRIFT区和所述p体区之间的所述结之间。
29.一种横向扩散金属氧化物半导体器件即LDMOS器件，其包括：
衬底；
设置在所述衬底上的p外延层；
p体区，其设置在所述p外延层中；
n漂移区即NDRIFT区，其设置在所述p体区中以提供漏极延伸区；
栅极介电层，其设置在所述p体区中的沟道区上方，其中所述栅极介电层从所述NDRIFT区上方的第一端延伸到所述NDRIFT区外部的所述p体区的部分上方的第二端，使得所述栅极介电层设置在所述NDRIFT区和所述p体区之间的结上方；
栅极电极，其设置在所述栅极介电层上方；
DWELL区，其设置在所述p体区中并且具有由所述栅极电极的边缘描绘出的边缘，其中在所述DWELL区的边缘与在所述NDRIFT区和所述p体区之间的所述结之间的有效沟道长度是在近似75nm和150nm之间；
源极区，其设置在所述DWELL区中；以及
漏极区，其设置在所述NDRIFT区中。
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