CN106841894B - FPGA interconnection line testing method and device - Google Patents
FPGA interconnection line testing method and device Download PDFInfo
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- CN106841894B CN106841894B CN201611207324.8A CN201611207324A CN106841894B CN 106841894 B CN106841894 B CN 106841894B CN 201611207324 A CN201611207324 A CN 201611207324A CN 106841894 B CN106841894 B CN 106841894B
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Abstract
The invention discloses a method and a device for testing an FPGA (field programmable gate array) interconnection line, which are used for acquiring a transverse interconnection line to be tested and a longitudinal interconnection line to be tested outside a switch matrix to be tested of an FPGA device, then modeling the acquired transverse interconnection line to be tested and the acquired longitudinal interconnection line to be tested in the transverse direction and the longitudinal direction respectively to generate an interconnection line test pattern, and then converting the acquired interconnection line test pattern into a test bit stream file to be input into the switch matrix to be tested for testing. Therefore, the invention can separate the interconnection lines in the transverse direction and the longitudinal direction into the connection type, only needs to divide the interconnection lines into two parts in the transverse direction and the longitudinal direction when generating the interconnection line test pattern, the longitudinal and transverse decomposition model is easier and simpler than the layer decomposition in the application and processing, and only needs to divide the interconnection lines into two parts aiming at various types of interconnection lines, thereby simplifying the test operation and improving the test efficiency to a great extent.
Description
Technical Field
The invention relates to the Field of FPGA (Field-Programmable Gate Array) testing, in particular to a method and a device for testing FPGA interconnection lines.
Background
Programmable interconnect lines are a vital part of the resources in FPGA devices. The FPGA device connects programmable resources, clock control resources and the like in the device into a whole through interconnection lines. Programmable switch arrays exist between the interconnection lines, and the programmable switch arrays enable the interconnection lines in the FPGA device to be connected and insulated according to the designation of a user, so that the designed function is realized.
The integrity of the interconnect lines is the basis for the testability of the internal resources of the entire FPGA device. Any faults present in the interconnect lines may cause the configuration of the circuit design to fail. In order to reduce or even eliminate interconnection line faults inside the FPGA device and ensure that the product has higher programming reliability, test vectors with less configuration times and high connection coverage rate need to be designed. The existing model for establishing the interconnection line is a layer decomposition model, and the existing layer decomposition model is briefly introduced as follows:
referring to fig. 1, the external interconnection line distribution of the complete switch matrix is shown. Taking two long lines as an example, in fig. 1, there are interconnection lines to be tested on the upper, lower, and left sides of the switch matrix, the two long lines on the upper and lower sides have ten left-direction (i.e., left-direction) two long lines and ten right-direction (i.e., right-direction) two long lines, and the two long lines on the left side have twenty upward (i.e., upward) two long lines and twenty downward (i.e., downward) two long lines. When the layer decomposition type model is established, ten upward two long lines and ten downward two long lines of the switch matrix are transferred to the right side, and thus, each side of the switch matrix is provided with twenty interconnecting lines to form a regular interconnecting line pattern. Then, the connecting line pattern layer is decomposed, and each direction is just provided with ten connecting lines, so that the connecting line pattern is divided into 10 layers, each direction is provided with one connecting line, and the pattern layer decomposition type model is built. And then digitalizing the decomposed layers, giving connection equations of the connection lines and the connection lines, processing each layer by using a stream algorithm, optimizing and combining the test paths after finding the test path of each layer, and compiling a bit stream file for testing. The image layer decomposition model is an existing classical model for testing the interconnection line, but the efficiency of testing the interconnection line by applying the model is very low, and the two long lines are divided into 10 layers, so that 36 times of FPGA devices need to be configured for testing the two long lines independently, and the tests of other types of interconnection lines of the FPGA devices are carried out up to more than hundred times of tests on the FPGA devices.
Disclosure of Invention
The invention aims to solve the main technical problem of providing a method and a device for testing FPGA (field programmable gate array) interconnecting wires, and solving the problem of low efficiency in the existing testing of the FPGA interconnecting wires based on a layer decomposition model.
In order to solve the technical problem, the invention provides a method for testing an interconnection line of an FPGA, which comprises the following steps:
acquiring a transverse interconnection line to be tested and a longitudinal interconnection line to be tested outside a switch matrix to be tested of the FPGA device;
modeling the transverse interconnection line to be tested and the longitudinal interconnection line to be tested respectively to generate an interconnection line test pattern;
and converting the interconnection line test pattern into a test bit stream file and inputting the test bit stream file into the switch matrix to be tested for testing.
In an embodiment of the present invention, the modeling the horizontal interconnection line to be tested and the vertical interconnection line to be tested to generate an interconnection line test pattern includes:
selecting N corresponding interconnection lines to be tested from the transverse interconnection lines to be tested and the longitudinal interconnection lines to be tested respectively according to the connection types of the interconnection lines to be tested, wherein the N interconnection lines to be tested selected in one direction are different;
arranging interconnection lines to be tested selected from the transverse interconnection lines to be tested in each row of the switch matrix to be tested, and arranging interconnection lines to be tested selected from the longitudinal interconnection lines to be tested in each column of the switch matrix to be tested;
merging the interconnection lines to be tested of each row, and merging the interconnection lines to be tested of each column;
performing code modeling on the transverse interconnection line to be tested after the merging processing to obtain a transverse model code, and performing code modeling on the longitudinal interconnection line to be tested after the merging processing to obtain a longitudinal model code;
merging the transverse model codes and the longitudinal model codes to obtain interconnection line test model codes;
and generating an interconnection line test pattern according to the interconnection line test model code.
In one embodiment of the present invention, the connection type includes at least one of a two-long line, a six-long line, a long line, and a direct connection.
In an embodiment of the present invention, when the connection type is a two-long line or a six-long line, the value of N is 10;
when the connection type is a long line, the value of N is 4;
and when the connection type is direct connection, the value of N is 2.
In an embodiment of the present invention, when the connection type is a two-long line, a six-long line, or a long line, before the to-be-tested interconnection line selected from the transverse to-be-tested interconnection lines is arranged in each row of the to-be-tested switch matrix, the method further includes:
carrying out interconnection line normalization processing on N interconnection lines to be tested selected from the transverse interconnection lines to be tested;
before each column of the switch matrix to be tested is provided with an interconnection line to be tested selected from the longitudinal interconnection lines to be tested, the method also comprises the following steps:
and carrying out interconnection line normalization processing on the N interconnection lines to be tested selected from the longitudinal interconnection lines to be tested.
In an embodiment of the present invention, the performing interconnection line normalization processing on the N interconnection lines to be tested includes:
firstly, transferring and merging the N interconnection lines to be tested by adopting an input-output unit structure;
and if the interconnection lines to be merged still exist after the N interconnection lines to be merged are subjected to the transferring and merging treatment according to the input and output unit structure, merging the interconnection lines to be merged by adopting the programmable logic unit line structure of the lookup table.
In an embodiment of the present invention, the merging the to-be-tested interconnection lines in each row includes:
sequentially connecting the output port of the interconnection line to be tested in the upper line of the two adjacent lines with the input port of the interconnection line to be tested in the lower line;
the row merging processing of the interconnection lines to be tested of each row comprises the following steps:
and sequentially connecting the output port of the interconnection line to be tested in the upper column of the adjacent two columns with the input port of the interconnection line to be tested in the next column.
In order to solve the above problems, the present invention further provides an FPGA interconnection line testing apparatus, including:
the interconnection line acquisition module is used for acquiring a transverse interconnection line to be tested and a longitudinal interconnection line to be tested outside a switch matrix to be tested of the FPGA device;
the test pattern generation module is used for respectively modeling the transverse interconnection line to be tested and the longitudinal interconnection line to be tested so as to generate an interconnection line test pattern;
and the test module is used for converting the interconnection line test pattern into a test bit stream file and inputting the test bit stream file into the switch matrix to be tested for testing.
In an embodiment of the present invention, the test pattern generation module includes:
a model generation submodule for selecting corresponding N interconnection lines to be tested from the transverse interconnection line to be tested and the longitudinal interconnection line to be tested respectively according to the connection type of the interconnection lines to be tested, wherein the N interconnection lines to be tested selected in one direction are different from each other, arranging interconnection lines to be tested selected from the transverse interconnection lines to be tested in each row of the switch matrix to be tested, and each column of the switch matrix to be tested is provided with an interconnection line to be tested selected from the longitudinal interconnection lines to be tested, then merging the interconnection lines to be tested of each row, merging the interconnection lines to be tested of each column, performing code modeling on the merged transverse interconnection lines to be tested to obtain transverse model codes, code modeling is carried out on the combined longitudinal interconnection line to be tested to obtain a longitudinal model code;
and the graph generation sub-module is used for merging the transverse model codes and the longitudinal model codes to obtain interconnection line test model codes and generating interconnection line test graphs according to the interconnection line test model codes.
In an embodiment of the present invention, the model generation sub-module is configured to sequentially connect the output port of the interconnection line to be tested in the upper row in the two adjacent rows to the input port of the interconnection line to be tested in the lower row, and to sequentially connect the output port of the interconnection line to be tested in the upper column in the two adjacent rows to the input port of the interconnection line to be tested in the lower column.
The invention has the beneficial effects that:
the FPGA interconnection line testing method and the FPGA interconnection line testing device provided by the invention are used for acquiring the transverse interconnection line to be tested and the longitudinal interconnection line to be tested outside a switch matrix to be tested of an FPGA device, then modeling the acquired transverse interconnection line to be tested and the longitudinal interconnection line to be tested in the transverse direction and the longitudinal direction respectively to generate an interconnection line testing graph, and then converting the acquired interconnection line testing graph into a testing bit stream file to be input into the switch matrix to be tested for testing. It can be seen that the invention breaks the interconnection lines in the transverse direction and the longitudinal direction to form the connection type, only needs to divide the interconnection lines into two parts in the transverse direction and the longitudinal direction when generating the interconnection line test pattern, the longitudinal and transverse decomposition is easier and simpler than the pattern layer decomposition in the application process, and only needs to divide the interconnection lines of various types into two parts (for example, two long lines and only needs to divide the interconnection lines into two parts instead of the existing division into 10 layers), thereby simplifying the test operation and greatly improving the test efficiency.
Drawings
FIG. 1 is a schematic diagram of a distribution of external interconnection lines of a switch matrix;
fig. 2 is a schematic flow chart of a method for testing an interconnect line of an FPGA according to an embodiment of the present invention;
FIG. 3 is a schematic flowchart of generating an interconnect testing pattern according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of an FPGA interconnection line testing apparatus according to a second embodiment of the present invention;
FIG. 5-1 is a schematic view of a longitudinal two-long line connection provided in a third embodiment of the present invention;
FIG. 5-2 is a schematic diagram of a transverse two-long-line connection according to a third embodiment of the present invention;
fig. 6 is a test chart of a single switch matrix interconnection line provided in the third embodiment of the present invention;
fig. 7 is a test chart of a plurality of switch matrix interconnect lines according to a third embodiment of the present invention;
fig. 8 is a waveform diagram of sample points of a test pattern according to a third embodiment of the present invention.
Detailed Description
The invention aims at the problem of low efficiency of the existing layer decomposition-based model for testing the FPGA interconnecting wire, the interconnecting wire to be tested is disconnected in the transverse direction and the longitudinal direction to form a connecting line type, and the generating of the interconnecting wire test pattern only needs to divide the interconnecting wire into two in the transverse direction and the longitudinal direction, namely, adopts longitudinal and transverse decomposition, so that the testing operation can be simplified and the testing efficiency can be improved to a great extent. The present invention will be described in further detail with reference to the following detailed description and accompanying drawings.
The first embodiment is as follows:
referring to fig. 2, the FPGA interconnection line testing method provided in this embodiment includes:
s201: and acquiring a transverse interconnection line to be tested and a longitudinal interconnection line to be tested outside a switch matrix to be tested of the FPGA device.
In the embodiment, different types of interconnection lines to be tested can be tested respectively, and the test mode in the embodiment is suitable for testing any type of interconnection line; the transverse interconnection line to be tested in the embodiment refers to the interconnection line to be tested on the upper side and the lower side of the switch matrix; the longitudinal interconnecting lines refer to the interconnecting lines to be tested on the left side and the right side of the switch matrix.
S202: and modeling the obtained transverse interconnection line to be tested and the longitudinal interconnection line to be tested respectively to generate an interconnection line test pattern.
And respectively modeling the obtained transverse interconnection line to be tested and the longitudinal interconnection line to be tested, namely modeling the transverse interconnection line to be tested in the transverse direction and modeling the longitudinal interconnection line to be tested in the longitudinal direction. That is, in the embodiment, the interconnection lines are disconnected in the transverse direction and the longitudinal direction and are independently connected, and the generation of the interconnection line test pattern only needs to divide the interconnection lines into two parts in the transverse direction and the longitudinal direction, so that the decomposition is easier and simpler compared with the existing pattern layer, and only needs to divide the interconnection lines into two parts for various types of interconnection lines, thereby simplifying the test operation and improving the test efficiency to a great extent.
S203: and converting the interconnection line test pattern into a test bit stream file and inputting the test bit stream file into the switch matrix to be tested for testing.
In this embodiment, the mode of the test bitstream file written with the interconnection line test image may adopt any bitstream file generation mode.
In the above S202, the process of modeling the horizontal interconnection line to be tested and the vertical interconnection line to be tested respectively to generate the interconnection line test pattern is shown in fig. 3, and includes:
s301: and respectively selecting N corresponding interconnection lines to be tested from the transverse interconnection lines to be tested and the longitudinal interconnection lines to be tested according to the connection type of the interconnection lines to be tested.
The N interconnection lines to be tested selected in one direction are different from each other, and the N selected interconnection lines to be tested can completely cover the connection and distribution of the interconnection lines of the type.
S302: and arranging the interconnection lines to be tested selected from the transverse interconnection lines to be tested in each row of the switch matrix to be tested, and arranging the interconnection lines to be tested selected from the longitudinal interconnection lines to be tested in each column of the switch matrix to be tested.
It should be understood that there is no strict timing limitation between the two execution steps in S302, and the two execution steps may be executed simultaneously or not simultaneously, and the execution order of the two execution steps when they are not executed simultaneously may be flexibly selected.
S303: and merging the interconnection lines to be tested of each row, and merging the interconnection lines to be tested of each column.
It should be understood that there is no strict timing limitation between the two execution steps in S303, and the two execution steps may be executed simultaneously or not simultaneously, and the execution order of the two execution steps in non-simultaneous execution may be flexibly selected.
In one example, the merging the interconnection lines to be tested in each row includes:
sequentially connecting the output port of the interconnection line to be tested in the upper line of the two adjacent lines with the input port of the interconnection line to be tested in the lower line;
the row merging processing of the interconnection lines to be tested of each row comprises the following steps:
and sequentially connecting the output port of the interconnection line to be tested in the upper column of the adjacent two columns with the input port of the interconnection line to be tested in the next column.
S304: and performing code modeling on the combined transverse interconnection line to be tested to obtain a transverse model code, and performing code modeling on the combined longitudinal interconnection line to be tested to obtain a longitudinal model code.
It should be understood that there is no strict timing limitation between the two execution steps in S304, and the two execution steps may be executed simultaneously or not simultaneously, and the execution order of the two execution steps in different execution times may be flexibly selected.
S305: and combining the transverse model codes and the longitudinal model codes to obtain the interconnection line test model codes.
In this embodiment, any existing merging method capable of realizing model codes may be used as the method for merging the horizontal model codes and the vertical model codes.
S306: and generating an interconnection line test pattern according to the obtained interconnection line test model code, wherein the interconnection line test pattern comprises the interconnection line to be tested transversely and the interconnection line to be tested longitudinally, so that the transverse interconnection line and the longitudinal interconnection line can be tested at one time.
In this embodiment, the interconnect type of the FPGA device includes, but is not limited to, at least one of a two-long line, a six-long line, a long line, and a direct interconnect.
The two long lines are interconnection lines which are connected with the two switch matrixes at intervals;
the six long lines are interconnection lines which are connected at intervals of five switch matrixes;
the long line is an interconnecting line which penetrates through the whole longitudinal direction or the whole transverse direction and can be provided with a plurality of middle connecting points, and five switch matrixes are arranged between every two adjacent middle connecting points;
the direct connection line refers to directly connecting the switch matrixes adjacent to each other up and down and left and right or the switch matrixes adjacent to each other in a diagonal line.
In an example, when the connection type of the interconnection line to be tested is a two-long line or a six-long line, the value of N is 10;
when the connection type of the interconnection line to be tested is a long line, the value of N is 4;
and when the connection type of the interconnection line to be tested is a direct connection, the value of N is 2.
In addition, the excessive wiring paths may increase the number of stimuli required for testing, so the embodiment may also merge the wiring paths of each row to reduce the number of additional stimuli. Therefore, in this embodiment, when the connection type of the interconnection line to be tested is two long lines, six long lines, or long lines, before the interconnection line to be tested selected from the transverse interconnection lines to be tested is set in each row of the switch matrix to be tested, the method further includes:
and carrying out interconnection line normalization processing on N interconnection lines to be tested selected from the transverse interconnection lines to be tested, wherein the interconnection lines in one row after the normalization processing have only one interconnection line with an opening facing to the left and one interconnection line with an opening facing to the right.
Similarly, before each column of the switch matrix to be tested is provided with the interconnection line to be tested selected from the longitudinal interconnection line to be tested, the method further comprises the following steps:
and carrying out interconnection line normalization processing on N interconnection lines to be tested selected from the longitudinal interconnection lines to be tested, wherein the interconnection lines in one row after the normalization processing only have one interconnection line with an upward opening and one interconnection line with a downward opening.
In this embodiment, when performing the interconnection normalization processing on the N interconnection lines to be tested, at least one of an input/output unit (IOB) structure and a programmable logic unit line structure of the lookup table may be used, or a combination of the two structures. The method can be flexibly set according to actual requirements. For example, considering the simplification degree with subsequent codes, when performing the interconnection line normalization processing, the input/output unit structure may be used to perform the transfer and merging processing on the N interconnection lines to be tested, and if there still exist interconnection lines to be tested that need to be merged after the transfer and merging processing is performed on the N interconnection lines to be tested according to the input/output unit structure, the programmable logic unit line structure of the lookup table is used to perform the merging processing on the interconnection lines to be tested that need to be merged. Of course, before the merging process, merging of the loop wirings of the N interconnection lines is preferentially performed.
In the method for testing the interconnection lines based on the vertical and horizontal decomposition model provided in this embodiment, the connection lines of the switch matrix are divided into the horizontal connection lines and the vertical connection lines, and the vertical and horizontal decomposition model adopts horizontal and vertical disconnection, which are respectively connected to the connection lines individually. Compared with a layer decomposition model, the vertical and horizontal decomposition is simpler in establishment mode, for example, for two long lines or six long lines, ten layers are used for the layer decomposition model, and the vertical and horizontal decomposition in the embodiment only needs to be divided into two parts for all types of interconnection lines; and the vertical and horizontal decomposition is easier than the layer decomposition in application processing, the layer decomposition model needs to use a maximum flow algorithm to perform model simulation and path search in the process of testing the interconnection line, and the vertical and horizontal decomposition only needs to merge each annular path. Therefore, the advantage of the implementation of the interconnection line test based on the longitudinal and transverse decomposition type model is that the test efficiency is greatly improved on the premise of ensuring the accuracy of the test result. For example, two long lines are tested, the FPGA device is configured for 2 times by applying the vertical and horizontal decomposition type model, which is far less than 36 times by applying the layer decomposition type model, and the testing efficiency by applying the vertical and horizontal decomposition type model is 18 times that of the layer decomposition type model.
Example two:
the embodiment provides an FPGA interconnection line testing apparatus, as shown in fig. 4, including:
the interconnection line acquisition module 41 is configured to acquire a transverse interconnection line to be tested and a longitudinal interconnection line to be tested outside a switch matrix to be tested of the FPGA device; the transverse interconnection line to be tested in the embodiment refers to the interconnection line to be tested on the upper side and the lower side of the switch matrix; the longitudinal interconnecting lines refer to the interconnecting lines to be tested on the left side and the right side of the switch matrix.
And the test pattern generation module 42 is configured to model the horizontal interconnection line to be tested and the vertical interconnection line to be tested respectively to generate an interconnection line test pattern. The test pattern generation module 42 models the obtained transverse interconnection line to be tested and the longitudinal interconnection line to be tested, that is, models the transverse interconnection line to be tested in the transverse direction, and models the longitudinal interconnection line to be tested in the longitudinal direction. That is, in the embodiment, the interconnection lines are disconnected in the transverse direction and the longitudinal direction and are independently connected to form a connection type, and the generation of the interconnection line test pattern only needs to divide the interconnection lines into two parts in the transverse direction and the longitudinal direction, so that the decomposition is easier and simpler compared with the existing pattern layer, and only needs to divide the interconnection lines into two parts for various types of interconnection lines, so that the test efficiency can be improved to a great extent.
And the test module 43 is configured to convert the interconnection test pattern into a test bit stream file, and input the test bit stream file into the switch matrix to be tested for testing. The test bitstream file written by the test module 43 with the interconnection line test image may be generated in any bitstream file generation manner.
Referring to fig. 4, the test pattern generation module 42 in the present embodiment includes:
the model generation submodule 421 is configured to select, according to the connection type of the interconnection line to be detected, N corresponding interconnection lines to be detected from the horizontal interconnection line to be detected and the longitudinal interconnection line to be detected, where the N interconnection lines to be detected selected in one direction are different from each other, and the N selected interconnection lines to be detected can completely cover the connection and distribution of the interconnection lines of the type; the model generation sub-module 421 sets, in each row of the switch matrix to be tested, the interconnection lines to be tested selected from the transverse interconnection lines to be tested, sets, in each column of the switch matrix to be tested, the interconnection lines to be tested selected from the longitudinal interconnection lines to be tested, then performs merging processing on the interconnection lines to be tested in each row, and performs column merging processing on the interconnection lines to be tested in each column; in an example, the model generation sub-module 421 sequentially connects the output port of the interconnection line to be tested in the upper row in two adjacent rows to the input port of the interconnection line to be tested in the lower row, and sequentially connects the output port of the interconnection line to be tested in the upper row in two adjacent columns to the input port of the interconnection line to be tested in the lower column. The model generation sub-module 421 performs code modeling on the merged transverse interconnection line to be tested to obtain a transverse model code, and performs code modeling on the merged longitudinal interconnection line to be tested to obtain a longitudinal model code;
and the pattern generation sub-module 422 is configured to combine the horizontal model code and the vertical model code to obtain an interconnection line test model code, and generate an interconnection line test pattern according to the interconnection line test model code.
In this embodiment, the interconnect type of the FPGA device includes, but is not limited to, at least one of a two-long line, a six-long line, a long line, and a direct interconnect.
The two long lines are interconnection lines which are connected with the two switch matrixes at intervals;
the six long lines are interconnection lines which are connected at intervals of five switch matrixes;
the long line is an interconnecting line which penetrates through the whole longitudinal direction or the whole transverse direction and can be provided with a plurality of middle connecting points, and five switch matrixes are arranged between every two adjacent middle connecting points;
the direct connection line refers to directly connecting the switch matrixes adjacent to each other up and down and left and right or the switch matrixes adjacent to each other in a diagonal line.
In an example, when the connection type of the interconnection line to be tested is a two-long line or a six-long line, the value of N is 10;
when the connection type of the interconnection line to be tested is a long line, the value of N is 4;
and when the connection type of the interconnection line to be tested is a direct connection, the value of N is 2.
In addition, the excessive wiring paths may increase the number of stimuli required for testing, so the embodiment may also merge the wiring paths of each row to reduce the number of additional stimuli. Therefore, in this embodiment, when the connection type of the interconnection line to be tested is two long lines, six long lines, or long lines, the model generation sub-module 421 further performs interconnection line normalization on N interconnection lines to be tested selected from the horizontal interconnection lines to be tested before the interconnection line to be tested is set in each row of the switch matrix to be tested, and after the normalization, there is only one interconnection line with an opening facing to the left and one interconnection line with an opening facing to the right in the wiring in one row. Similarly, before the to-be-tested interconnection line selected from the longitudinal to-be-tested interconnection lines is arranged in each column of the to-be-tested switch matrix, the model generation sub-module 421 further performs interconnection line normalization on the N to-be-tested interconnection lines selected from the longitudinal to-be-tested interconnection lines, and after the normalization, only one interconnection line with an upward opening and one interconnection line with a downward opening are arranged in one row of wiring.
In this embodiment, when the model generation sub-module 421 performs interconnection line normalization on the N interconnection lines to be tested, at least one of an input/output unit (IOB) structure and a programmable logic unit line structure of the lookup table may be used, or a combination of the two structures may be used. The method can be flexibly set according to actual requirements. For example, considering the simplification degree with subsequent codes, when performing the interconnection line normalization processing, the input/output unit structure may be used to perform the transfer and merging processing on the N interconnection lines to be tested, and if there still exist interconnection lines to be tested that need to be merged after the transfer and merging processing is performed on the N interconnection lines to be tested according to the input/output unit structure, the programmable logic unit line structure of the lookup table is used to perform the merging processing on the interconnection lines to be tested that need to be merged. Of course, before the merging process, merging of the loop wirings of the N interconnection lines is preferentially performed.
The FPGA interconnection line testing arrangement that this embodiment provided is based on the mode that the decomposed model carries out the test to the interconnection line with great ease, divide into horizontal connecting wire and longitudinal connecting wire with switch matrix's line, what decomposed model adopted with great ease is horizontal and vertical disconnection, becomes the line connection type separately, compares in the picture layer and decomposes the prerequisite that the model can guarantee the test result accuracy under, very big promotion efficiency of software testing.
Example three:
the FPGA interconnection line vertical and horizontal decomposition type model provided by the embodiment has universality, does not aim at a certain type of FPGA device, does not need a special unit structure, and only needs the design of the interconnection line to meet the distribution in vertical and horizontal directions. At present, any FPGA device in the market has a two-long-line structure, so for easy understanding, the present embodiment takes a representative two-long-line as an example, and a vertical and horizontal decomposition model of the interconnection line is described. As shown in fig. 5-1 and 5-2, the lengthwise two-long lines and the widthwise two-long lines are separately modeled. In fig. 5-1 and 5-2, the wire-split model is an abstraction of the physical connections of the interconnect lines within the FPGA device. In an actual chip, no matter the chip is a horizontal interconnection line or a vertical interconnection line, in order to ensure that the connection in the vertical and horizontal directions is continued, the two long lines in the same direction have a one-to-one corresponding connection relationship (for example, the two horizontal long lines have a one-to-one corresponding connection relationship in the left and right directions). At both ends of the switch matrix in each row and column there is a turn matrix which turns the connecting lines in one direction into the other opposite direction, which makes a wrap-around routing possible.
In fig. 5-1 and 5-2, the 100% coverage of the transverse interconnection line can be realized by adopting 10 times of non-repeated surrounding wiring based on the distribution characteristics and the connection characteristics of the two long lines, and the same principle is applied to the longitudinal interconnection line. Therefore, each connection relationship outside the switch matrix in fig. 5-1 and 5-2 represents 10 interconnection lines, which is used as a model of the interconnection line to perform the overlay path merging process.
In the process of applying the vertical and horizontal decomposition type model, the excitation required by the test is increased due to too many wiring paths, so the wiring paths in each row and each column are merged, and the number of external excitation sources is reduced. The FPGA device has two general structures of an IOB and a Slice, a through transmission line from input to output is arranged in the IOB, a lookup table structure in the Slice can also provide through connection, and the lookup table structure can be used for normalizing 10 surrounding wiring lines. The selection of the resources consumed by the rounding routing normalization may set a certain priority, for example, merge the rounding routing at first, then merge the IOB transitions, and finally merge the Slice transitions, or even realize the normalization of the routing path without using the Slice. The IOB has a higher priority of use than Slice because its connection is more flexible. The normalization of the surrounding wiring is not unique.
FIG. 6 illustrates an interconnect test pattern for a single switch matrix generated using a cross-hatch decomposition model, and FIG. 7 illustrates an interconnect test pattern for a plurality of switch matrices generated using a cross-hatch decomposition model; it can be seen from fig. 7 that all the interconnection lines in the longitudinal direction and the transverse direction are on the test path, the coverage rate of the two long lines is up to 97% when the first test is configured, and the second test is configured to test the switch matrix connection lines adjacent to the BRAM module, so that the goal of 100% coverage of the two long lines when the 2 times configuration is realized.
After the interconnection line test pattern shown in fig. 7 is obtained, the pattern is converted into a bit stream file, and the actual FPGA device is tested. Fig. 8 shows waveforms of sampling points of a test pattern, and the interconnect test model in this embodiment uses complete combinational logic, and an input signal is given from an external port, and a pin header leading out from a circuit board detects an output signal. The upper waveform 81 in fig. 8 is an input waveform, and the lower waveform 82 is an output waveform. The frequency characteristics of the output waveform and the input waveform are consistent, which indicates that the signal transmission is not obstructed, and the two long lines of the FPGA passing the test are complete. The processing modes of the other types of interconnection lines are similar to those of the two long lines, and are not described in detail.
The invention aims at the problem of low efficiency of the existing layer decomposition-based model for testing the FPGA interconnecting wire, the interconnecting wire to be tested is disconnected in the transverse direction and the longitudinal direction to form a connecting line type, and the generating of the interconnecting wire test pattern only needs to divide the interconnecting wire into two in the transverse direction and the longitudinal direction, namely, adopts longitudinal and transverse decomposition, so that the testing operation can be simplified and the testing efficiency can be improved to a great extent.
The foregoing is a more detailed description of the present invention that is presented in conjunction with specific embodiments, and the practice of the invention is not to be considered limited to those descriptions. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (8)
1. An FPGA interconnection line testing method is characterized by comprising the following steps:
acquiring a transverse interconnection line to be tested and a longitudinal interconnection line to be tested outside a switch matrix to be tested of the FPGA device;
modeling the transverse interconnection line to be tested and the longitudinal interconnection line to be tested respectively to generate an interconnection line test pattern, wherein the modeling the transverse interconnection line to be tested and the longitudinal interconnection line to be tested respectively to generate the interconnection line test pattern comprises: selecting N corresponding interconnection lines to be tested from the transverse interconnection lines to be tested and the longitudinal interconnection lines to be tested respectively according to the connection types of the interconnection lines to be tested, wherein the N interconnection lines to be tested selected in one direction are different; arranging interconnection lines to be tested selected from the transverse interconnection lines to be tested in each row of the switch matrix to be tested, and arranging interconnection lines to be tested selected from the longitudinal interconnection lines to be tested in each column of the switch matrix to be tested; merging the interconnection lines to be tested of each row, and merging the interconnection lines to be tested of each column; performing code modeling on the transverse interconnection line to be tested after the merging processing to obtain a transverse model code, and performing code modeling on the longitudinal interconnection line to be tested after the merging processing to obtain a longitudinal model code; merging the transverse model codes and the longitudinal model codes to obtain interconnection line test model codes; generating an interconnection line test pattern according to the interconnection line test model code;
and converting the interconnection line test pattern into a test bit stream file and inputting the test bit stream file into the switch matrix to be tested for testing.
2. The FPGA interconnect testing method of claim 1, wherein the wire type comprises at least one of a two-long wire, a six-long wire, a long wire, and a direct wire.
3. The FPGA interconnection line testing method of claim 2, wherein when the connection type is a two-long line or a six-long line, the value of N is 10;
when the connection type is a long line, the value of N is 4;
and when the connection type is direct connection, the value of N is 2.
4. The FPGA interconnecting line testing method of claim 2, wherein when the connection type is a two-long line, a six-long line, or a long line, before setting, in each row of the switch matrix to be tested, an interconnecting line to be tested selected from the transverse interconnecting lines to be tested, further comprising:
carrying out interconnection line normalization processing on N interconnection lines to be tested selected from the transverse interconnection lines to be tested;
before each column of the switch matrix to be tested is provided with the interconnection line to be tested selected from the longitudinal interconnection lines to be tested, the method further comprises the following steps:
and carrying out interconnection line normalization processing on N interconnection lines to be tested selected from the longitudinal interconnection lines to be tested.
5. The FPGA interconnect testing method of claim 4, wherein the interconnect normalizing the N interconnects to be tested comprises:
firstly, transferring and merging the N interconnection lines to be tested by adopting an input-output unit structure;
and if the interconnection lines to be merged still exist after the N interconnection lines to be merged are subjected to the transferring and merging treatment according to the input and output unit structure, merging the interconnection lines to be merged by adopting the programmable logic unit line structure of the lookup table.
6. The FPGA interconnect testing method of any one of claims 1-5, wherein merging the to-be-tested interconnects of each row comprises:
sequentially connecting the output port of the interconnection line to be tested in the upper line of the two adjacent lines with the input port of the interconnection line to be tested in the lower line;
the row merging processing of the interconnection lines to be tested of each row comprises the following steps:
and sequentially connecting the output port of the interconnection line to be tested in the upper column of the adjacent two columns with the input port of the interconnection line to be tested in the next column.
7. An FPGA interconnect testing arrangement, its characterized in that includes:
the interconnection line acquisition module is used for acquiring a transverse interconnection line to be tested and a longitudinal interconnection line to be tested outside a switch matrix to be tested of the FPGA device;
the test pattern generation module is used for respectively modeling the transverse interconnection line to be tested and the longitudinal interconnection line to be tested so as to generate an interconnection line test pattern; the test pattern generation module includes: a model generation submodule and a graph generation submodule; the model generation submodule is used for respectively selecting corresponding N interconnection lines to be tested from the transverse interconnection lines to be tested and the longitudinal interconnection lines to be tested according to the connection types of the interconnection lines to be tested, the N interconnection lines to be tested selected in one direction are different, arranging interconnection lines to be tested selected from the transverse interconnection lines to be tested in each row of the switch matrix to be tested, and arranging interconnection lines to be tested selected from the longitudinal interconnection lines to be tested in each column of the switch matrix to be tested, then merging the interconnection lines to be tested of each row, merging the interconnection lines to be tested of each column, performing code modeling on the merged transverse interconnection lines to be tested to obtain transverse model codes, code modeling is carried out on the combined longitudinal interconnection line to be tested to obtain a longitudinal model code; the graph generation submodule is used for merging the transverse model codes and the longitudinal model codes to obtain interconnection line test model codes and generating interconnection line test graphs according to the interconnection line test model codes;
and the test module is used for converting the interconnection line test pattern into a test bit stream file and inputting the test bit stream file into the switch matrix to be tested for testing.
8. The FPGA interconnection line testing device of claim 7, wherein the model generation sub-module is configured to sequentially connect the output port of the interconnection line to be tested in the upper row of the two adjacent rows to the input port of the interconnection line to be tested in the lower row, and to sequentially connect the output port of the interconnection line to be tested in the upper column of the two adjacent columns to the input port of the interconnection line to be tested in the lower column.
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| CN108051729B (en) * | 2017-12-06 | 2020-03-24 | 西安智多晶微电子有限公司 | FPGA wiring coverage rate test method |
| CN110826293B (en) * | 2019-11-08 | 2023-06-16 | 中国电子科技集团公司第四十一研究所 | Microwave switch matrix visual modeling method and system |
| CN113295990B (en) * | 2021-07-26 | 2021-10-01 | 中科亿海微电子科技（苏州）有限公司 | Method, system, medium and equipment for generating FPGA feasibility test path |
| CN115130413B (en) * | 2022-09-01 | 2023-01-20 | 深圳市国电科技通信有限公司 | Topological structure design method of field programmable gate array and electronic equipment |
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