CN104281508A - Test method of interconnected wire stuck-at fault of field-programmable gate array (FPGA) - Google Patents
Test method of interconnected wire stuck-at fault of field-programmable gate array (FPGA) Download PDFInfo
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- CN104281508A CN104281508A CN201310290426.0A CN201310290426A CN104281508A CN 104281508 A CN104281508 A CN 104281508A CN 201310290426 A CN201310290426 A CN 201310290426A CN 104281508 A CN104281508 A CN 104281508A
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Abstract
The invention relates to a test method of an interconnected wire stuck-at fault of a field-programmable gate array (FPGA). The method comprises the following steps of dividing PLB (Personal Locator Beacon) on an FPGA chip into M groups according to the columns, wherein each group comprises m columns of PLBs, and M and m are natural numbers; connecting each group of PLBs with an input interface and an output interface on the chip; sequentially connecting the PLBs in M groups according to an interconnected wire with the preset length of L1, wherein the interconnected wire at the edge part in each column has a loopback structure; when the interconnected wire reaches the boundary of the top part or the boundary of the tail part, returning through the loopback structure; inputting a binary data flow to each group of PLBs on the FPGA chip through the input interface of each group of PLBs according to the length of the interconnected wire connecting with each PLB in each group of PLBs; confirming the failed PLB sub group according to the output result. According to the method, only less test case is needed to achieve 100 percent of coverage rate for detection of the interconnected wire between base blocks, and the detected fault position can be located easily.
Description
Technical field
The present invention relates to field of computer technology, particularly relate to a kind of method of testing of field programmable gate array interconnection line persistent fault.
Background technology
In production test, need to provide a large amount of test cases, to ensure the coverage rate that can reach 100% to the detection of corresponding failure.The present invention is directed to and account for field programmable gate array (Field Programmable Gate Array, FPGA) detection of the persistent fault (stuck-at fault) of the interconnection line of 80% area in, according to the structure of interconnection line in block fundamental mode Tile-based FPGA, propose a kind of generation method of test case.By the method, only need the test case of seldom (tens) just can reach and the coverage rate of 100% is reached to the detection of interconnection line between matrix (tile), and be easy to orient detected location of fault.
Summary of the invention
The object of this invention is to provide the little test case of a kind of needs just can reach and reach the coverage rate of 100% to the detection of interconnection line between tile, and be easy to the method orienting detected location of fault.
For achieving the above object, first aspect, the invention provides a kind of method of testing of field programmable gate array interconnection line persistent fault, comprising:
Programmed logical module PLB on field programmable gate array fpga chip is divided into M group by row, and often group comprises the PLB of m row, and wherein, M, m are natural number;
All be connected often organizing PLB with the input interface on described chip and output interface;
Length according to presetting is L
1interconnection line connect each PLB in described M group successively; Wherein, the interconnection line of the marginal portion often in row is provided with loopback structure, after interconnection line reaches top boundary or afterbody border, is returned by described loopback structure;
According to the length connecting the interconnection line of each PLB in each group of PLB, by the input interface of each group of PLB, to each group of PLB binary load on described fpga chip according to stream; The PLB grouping of breaking down is determined according to Output rusults.
In the above-mentioned methods, the method also comprises:
Often arrange PLB and comprise a PLB, be followed successively by PLB from afterbody to top
1, PLB
2..., PLB
a;
Length according to presetting is L
3interconnection line connect the PLB of each row in every group successively
1.
In the above-mentioned methods, the method also comprises:
PLB on fpga chip is divided into N group by row, and often group comprises the capable PLB of n, and wherein, N, n are natural number;
All be connected often organizing PLB with the input interface on described chip and output interface;
Length according to presetting is L
2interconnection line connect each PLB in described N group successively; Wherein, the interconnection line of the marginal portion often in row is provided with loopback structure, after interconnection line reaches right side boundary or left border, is returned by described loopback structure.
In the above-mentioned methods, the method also comprises:
Often row PLB comprises b PLB, is followed successively by PLB from left side to right side
1, PLB
2..., PLB
b;
Length according to presetting is L
3interconnection line connect the PLB of each row in every group successively
1.
Second aspect, the invention provides a kind of method of testing of field programmable gate array interconnection line persistent fault, comprising:
PLB on fpga chip is divided into N group by row, and often group comprises the capable PLB of n, and wherein, N, n are natural number;
All be connected often organizing PLB with the input interface on described chip and output interface;
Length according to presetting is L
2interconnection line connect each PLB in described N group successively; Wherein, the interconnection line of the marginal portion often in row is provided with loopback structure, after interconnection line reaches right side boundary or left border, is returned by described loopback structure;
According to the length connecting the interconnection line of each PLB in each group of PLB, by the input interface of each group of PLB, to each group of PLB binary load on described fpga chip according to stream;
The PLB grouping of breaking down is determined according to Output rusults.
In the above-mentioned methods, the method also comprises:
Often row PLB comprises b PLB, is followed successively by PLB from left side to right side
1, PLB
2..., PLB
b;
Length according to presetting is L
3interconnection line connect the PLB of each row in every group successively
1.
In the above-mentioned methods, the method also comprises:
PLB on fpga chip is divided into M group by row, and often group comprises the PLB of m row, and wherein, M, m are natural number;
All be connected often organizing PLB with the input interface on described chip and output interface;
Length according to presetting is L
1interconnection line connect each PLB in described M group successively; Wherein, the interconnection line of the marginal portion often in row is provided with loopback structure, after interconnection line reaches top boundary or afterbody border, is returned by described loopback structure.
In the above-mentioned methods, the method also comprises:
Often arrange PLB and comprise a PLB, be followed successively by PLB from afterbody to top
1, PLB
2..., PLB
a;
Length according to presetting is L
3interconnection line connect the PLB of each row in every group successively
1.
In the above-mentioned methods, the method comprises further:
To two row PLB of arbitrary neighborhood on fpga chip, described two row PLB are connected with input interface and output interface, connect two PLB on a diagonal line in two row of arbitrary neighborhood according to broken line successively; Wherein, the interconnection line of the marginal portion often in row is provided with loopback structure, after broken line arrives top boundary or afterbody border, is returned by described loopback structure.
In the above-mentioned methods, the method comprises further:
Often arrange PLB and comprise a PLB, be followed successively by PLB from afterbody to top
1, PLB
2..., PLB
a;
Length according to presetting is L
3interconnection line connect two row PLB in PLB
1.
Method provided by the invention is first by the interconnection line of different designated length, by each programmed logical module (the Programmable Logic Block on chip, PLB) and with this PLB at same 1 row, couple together with each PLB on 1 row and same diagonal line, again the 1st PLB often organizing the 1st row or the 1st row is connected with input port, the 1st PLB often organizing last 1 row or last 1 row is connected with delivery outlet, then to the interconnection line between PLB each on chip, corresponding test case is selected to test respectively according to the length of interconnection line, finally detect and orient location of fault.Thus achieving only needs little test case just can reach to reach the coverage rate of 100% to the detection of interconnection line between matrix, and is easy to orient detected location of fault.
Accompanying drawing explanation
Fig. 1 is the process flow diagram of the FPGA interconnection line persistent fault method of testing of the embodiment of the present invention;
Fig. 2 is from the interconnection line schematic diagram between the PLB of ixbar output on fpga chip;
Fig. 3 to be length be 4 the wiring diagram of octal line on row PLB;
Fig. 4 to be length be 8 the wiring diagram of octal line on row PLB;
Fig. 5 to be length be 3 the wiring diagram of triple-m molded line on row PLB;
Fig. 6 to be length be 2 the wiring diagram of triple-m molded line on row PLB;
Fig. 7 to be length be 4 the octal line wiring diagram of being expert on PLB;
Fig. 8 to be length be 8 the octal line wiring diagram of being expert on PLB;
Fig. 9 to be length be 3 the triple-m molded line wiring diagram of being expert on PLB;
Figure 10 to be length be 2 the triple-m molded line wiring diagram of being expert on PLB;
Figure 11 is the wiring diagram of broken line on adjacent two row PLB;
Figure 12 is the wiring diagram of the sub-broken line of diagonal on adjacent three row PLB.
Embodiment
Below by drawings and Examples, technical scheme of the present invention is described in further detail.
Matrix tile comprises PLB and some embedded stone block MAC, EMB, its difference is that internal logic is inconsistent, but this interconnection resource of interconnection line is the same, because tile most of in FPGA is PLB, below just with PLB replace tile state connecting between interconnection line.
Fig. 1 is the process flow diagram of the FPGA interconnection line persistent fault method of testing of the embodiment of the present invention.As shown in Figure 1, FPGA interconnection line persistent fault method of testing of the present invention comprises:
Step 101, is divided into M group by the programmed logical module PLB on field programmable gate array fpga chip by row, and often group comprises the PLB of m row.
In a step 101, on fpga chip, input I/O interface and export I/O interface not enough, usually divided into groups by row by the PLB on fpga chip, be divided into M group, often group comprises the PLB of m row.Wherein each PLB is made up of wiring matrix ioxbar and logical block, and wherein, ioxbar comprises 4 ixbar(64 inputs, the 32 interconnection line matrixes exported) input with 1 oxbar(24, the 24 interconnection line matrixes exported).Fig. 2 is from the interconnection line schematic diagram between the PLB of ixbar output on fpga chip.In Fig. 2, length be 4,8 octal line (octuple line) be equipped with 9 in the vertical, length be 4,8 octal line be equipped with 7 in the horizontal, length is triple-m(m type three times of lines of 2,3) molded line is equipped with 4 on horizontal and vertical, length is triple-t(t type three times of lines of 1,2,3) molded line is equipped with 6 on horizontal and vertical; Namely horizontal and vertical upper length be 1 triple line (three times of lines) have 6, horizontal and vertical upper length be 2 triple line have 10, horizontal and vertical upper length be 3 triple line have 10.The PLB of m row shares an input and an output, and an input I/O interface on corresponding chip, one exports I/O interface.
Step 102, the 1st PLB often organizing the 1st row in PLB is connected with input interface, and the 1st PLB often organizing the m row in PLB is connected with output interface, and wherein, M, m are natural number.
In a step 102, the input I/O interface on usual fpga chip and export I/O interface and be arranged on the end of upper and lower, left and right four direction, therefore general by near end PLB with input I/O interface, export in I/O interface one or both be connected.In a kind of specific embodiment, to the m row PLB in the often group be divided into group according to step 101, the 1st PLB that the 1st arranges is connected with input interface, the 1st PLB that m arranges is connected with output interface.Wherein, the 1st PLB often arranged refers to the PLB near afterbody border in these row; In connecting column, the 1st PLB is 1 with input I/O interface, one or both the interconnect length exported in I/O interface, and preferably, this interconnection line is triple-t molded line.
Step 103, the length according to presetting is L
1interconnection line connect each PLB in described M group successively.
In step 103, the length preset is L
1interconnection line comprise the octal line that length is 4 and 8, length be 2 and 3 triple-m molded line and length be 2 and 3 triple-t molded line.Fig. 3 to be length be 4 the wiring diagram of octal line on row PLB, in figure, the size of fpga chip is 32*19.PLB on fpga chip is divided into 19 groups by row, and often group comprises the PLB of 1 row, often shows 32 PLB, is followed successively by PLB from afterbody to top
1, PLB
2..., PLB
32, wherein the wiring matrix of each PLB octal line in the vertical comprises 9 root lines, afterbody border PLB
1with top boundary PLB
32octal line in be provided with loopback structure; Often row PLB in figure is one group, often organizes PLB an input I/O interface and one and exports I/O interface, thus need by two length be 1 triple-t molded line, respectively by the 1st PLB in this group with input I/O interface and export I/O interface and be connected.
From the PLB being positioned at afterbody border of these row
1start, along go north to wherein 1 root line across 4 PLB units to PLB
5, from PLB
5start again across 4 units to PLB
9, connect other PLB of same column successively, until PLB
29; Because from PLB
29start to walk around PLB across during 4 units again
32, and PLB
32octal line in be provided with loopback structure, so from PLB
29start across 4 unit loopbacks to PLB
32; Then from PLB
32start, connect each PLB successively, until rap around to PLB
1; Finally remaining 8 root lines are carried out identical connection successively, until all sub-lines connect complete;
Be now PLB at current starting point PLB(
1) adjacent PLB and PLB of the next one
2in do not exist from PLB
2start across 4 units to PLB
6the wiring of octal line style when connecting, the length according to presetting is the interconnection line of 1, preferably, this interconnection line to be length be 1 triple-t molded line, by PLB
1be connected to PLB
2.Then from PLB
2start, to PLB
2do and PLB
1same wiring operations.Finally, to PLB
3and PLB
4do and PLB
2after same judgement and wiring operations, judge and the current PLB completing wiring
4adjacent PLB
5middle existence is from PLB
5start across 4 units to PLB
9octal line style wiring connect, circulation wiring operations terminates.Via the triple-t molded line that length is 1, from PLB
4start, connect PLB successively
3..., PLB
1, the operation of this column wiring terminates; Because this group only comprises 1 row PLB, so after completing the wiring operations to the 1st row, this group wiring operations terminates.To on chip all the other 18 groups do same wiring operations.
Fig. 4 to be length be 8 the wiring diagram of octal line on row PLB.In Fig. 4, length be 8 the wire laying mode of octal line on row PLB and length be that the octal line of 4 is to arrange the wire laying mode on PLB similar, the wiring matrix of each PLB in the vertical length be 8 octal line comprise 9 root lines, unlike the PLB of span 8 units of front starting point PLB PLB adjacent with the next one.
Fig. 5 to be length be 3 the wiring diagram of triple-m molded line on row PLB.In Fig. 5, length be 3 the wire laying mode of triple-m line on row PLB and length be that the octal line of 4 is to arrange the wire laying mode on PLB similar, the wiring matrix of each PLB in the vertical length be 3 triple-m line comprise 4 root lines, unlike the PLB of span 3 units of front starting point PLB PLB adjacent with the next one.Length be 3 triple-t line comprise 6 root lines in the vertical, its wire laying mode is identical with triple-m line.
Fig. 6 to be length be 2 the wiring diagram of triple-m molded line on row PLB.In Fig. 6, length be 2 the wire laying mode of triple-m line on row PLB and length be that the octal line of 4 is to arrange the wire laying mode on PLB similar, the wiring matrix of each PLB in the vertical length be 2 triple-m line comprise 4 root lines, unlike the PLB of span 2 units of front starting point PLB PLB adjacent with the next one.Length be 2 triple-t line comprise 6 root lines in the vertical, its wire laying mode is identical with triple-m line.
Get back to Fig. 1, step 104, the PLB on fpga chip is divided into N group by row; Often group comprises the capable PLB of n.
At step 104, also for ease of and avoid fpga chip inputs I/O interface and export I/O interface not enough, usually divided into groups by row by the PLB on fpga chip, be divided into N group, often group comprises the capable PLB of n.Wherein each PLB is made up of wiring matrix (ioxbar) and logical block, and wherein, ioxbar comprises 4 ixbar(64 inputs, the 32 interconnection line matrixes exported) input with 1 oxbar(24, the 24 interconnection line matrixes exported).The PLB that N is capable shares an input and an output, and an input I/O interface on corresponding chip, one exports I/O interface.
Step 105, the 1st PLB of the 1st row often organized in PLB is connected with input interface, and the 1st PLB of the n-th line often organized in PLB is connected with output interface, and wherein, N, n are natural number.
In step 105, to the capable PLB of n in the often group be divided into group according to step 104, the 1st of the 1st row the PLB is connected with input interface, the 1st of n-th line the PLB is connected with output interface.Wherein, often the 1st PLB of row refers to the PLB near left border in this row; In connected row, the 1st PLB is 1 with input I/O interface, one or both the interconnect length exported in I/O interface, and preferably, this interconnection line is triple-t molded line.
Step 106, the length according to presetting is L
2interconnection line connect each PLB in described N group successively.
In step 106, the length preset is L
2interconnection line comprise the octal line that length is 4 and 8, length be 2 and 3 triple-m molded line and length be 2 and 3 triple-t molded line.Fig. 7 to be length be 4 the octal line wiring diagram of being expert on PLB, in figure, the size of fpga chip is 32*19.PLB on fpga chip is divided into 16 groups by row, and often group comprises the PLB of two row, and often row has 19 PLB, is followed successively by PLB from left side to right side
1, PLB
2..., PLB
19, wherein the wiring matrix of each PLB octal line in the horizontal comprises 7 root lines, left border PLB
1with right side boundary PLB
19octal line in be provided with loopback structure; In figure, two row PLB are one group, often organize PLB an input I/O interface and one and export I/O interface, so needs are the triple-t molded line of 1 by two length, respectively the 1st PLB of the 1st row in this group is connected with input I/O interface, the 1st PLB of the 2nd row in this group is connected with output I/O interface.
From the PLB being positioned at left border of this row
1start, along the wherein 1 root line that moves towards eastwards across 4 PLB units to PLB
5, from PLB
5start again across 4 units to PLB
9, connect other PLB of colleague successively, until PLB
17; Because from PLB
17start to walk around PLB across during 4 units again
19, and PLB
19octal line in be provided with loopback structure, so from PLB
17start across 4 unit loopbacks to PLB
18; Then from PLB
18start, connect each PLB successively, until PLB
2; Because from PLB
2start to walk around PLB across during 4 units again
1, and PLB
1octal line in be provided with loopback structure, so from PLB
2start across 4 unit loopbacks to PLB
3; Then from PLB
3start, connect each PLB successively, until rap around to PLB
1; Finally remaining 6 root lines are carried out identical connection successively, until all sub-lines connect complete;
Be now PLB at current starting point PLB(
1) adjacent PLB and PLB of the next one
2in do not exist from PLB
2start across 4 units to PLB
6the wiring of octal line style when connecting, the length according to presetting is the interconnection line of 1, preferably, this interconnection line to be length be 1 triple-t molded line, by PLB
1be connected to PLB
2.Then from PLB
2start, to PLB
2do and PLB
1same wiring operations.Complete PLB
2all sub-line wiring operations after, judge with the current PLB completing wiring
2adjacent PLB
3middle existence is from PLB
3start across 4 units to PLB
7octal line style wiring connect, circulation wiring operations terminates; Via the triple-t molded line that length is 1, to PLB
2with PLB
1connect, the operation of this row wiring terminates; PLB in 1st row
1again with the PLB in the 2nd row of this group
1connect; Wherein, each PLB connected mode in the 2nd row is identical with the 1st row; Because this group only comprises two row PLB, so after completing the connection to each PLB in two row, this group wiring operations terminates.To on chip all the other 15 groups do same wiring operations.
Fig. 8 to be length be 8 the octal line wiring diagram of being expert on PLB.In Fig. 8, length be 8 octal line be expert at wire laying mode on PLB and length be 4 the octal line wire laying mode of being expert on PLB similar, the wiring matrix of each PLB in the horizontal length be 8 octal line comprise 7 root lines, unlike the PLB of span 8 units of front starting point PLB PLB adjacent with the next one.
Fig. 9 to be length be 3 the triple-m molded line wiring diagram of being expert on PLB.In Fig. 9, length be 3 triple-m line be expert at wire laying mode on PLB and length be 4 the octal line wire laying mode of being expert on PLB similar, the wiring matrix of each PLB in the horizontal length be 3 triple-m line comprise 4 root lines, unlike the PLB of span 3 units of front starting point PLB PLB adjacent with the next one.Length be 3 triple-t line comprise 6 root lines in the horizontal, its wire laying mode is identical with triple-m line.
Figure 10 to be length be 2 the triple-m molded line wiring diagram of being expert on PLB.In Figure 10, length be 2 triple-m line be expert at wire laying mode on PLB and length be 4 the octal line wire laying mode of being expert on PLB similar, the wiring matrix of each PLB in the horizontal length be 2 triple-m line comprise 4 root lines, unlike the PLB of span 2 units of front starting point PLB PLB adjacent with the next one.Length be 2 triple-t line comprise 6 root lines in the horizontal, its wire laying mode is identical with triple-m line.
Get back to Fig. 1, it should be noted that, also can first perform step 104 to step 106, perform step 101 again to step 103, namely can first divide into groups to row and connect up, then divide into groups to row and connect up, both priority execution sequences can not affect the execution of test process.
Step 107, to two row PLB of arbitrary neighborhood on fpga chip, is arranged in the PLB of 1 row in left side
1be connected with input interface; Be arranged in the PLB of 1 row on right side
1be connected with output interface; Two PLB on a diagonal line in two row of arbitrary neighborhood are connected successively according to broken line.
In step 107, the PLB in arbitrary neighborhood two row on a diagonal line all needs to be connected by broken line.Figure 11 is the wiring diagram of broken line on adjacent two row PLB, and in figure, often arranging PLB has 32 PLB, is followed successively by PLB from afterbody to top
1, PLB
2..., PLB
32, wherein the interconnection line of wiring matrix on diagonally opposing corner direction of each PLB comprises 3 root lines, afterbody border PLB
1with top boundary PLB
32each interconnection line in be provided with loopback structure; Be arranged in the PLB of 1 row in left side
1be connected with input interface; Be arranged in the PLB of 1 row on right side
1be connected with output interface.
From 1 PLB arranged being arranged in left side
1start, the wherein 1 root line along broken line connects the PLB of 1 row being arranged in right side
2; Be arranged in the PLB of 1 row on right side
2the PLB of 1 row being arranged in left side is connected by this sub-line
3, connect successively, arrive PLB
32loopback structure afterwards by arranging in the interconnection line that is connected with self returns; Then the PLB arranged from right side 1
32start, connect the PLB of 1 row being arranged in left side along this sub-line
31; Be arranged in the PLB of 1 row in left side
31the PLB of 1 row being arranged in right side is connected by this sub-line
30, connect successively, until rap around to the PLB of 1 row being arranged in left side
1; Then remaining two root lines are carried out identical connection successively, until all sub-lines connect complete.
Be arranged in the PLB of 1 row in left side
1the interconnection line being 1 by length connects the PLB of 1 row being arranged in right side
1, preferably, this interconnection line to be length be 1 triple-t molded line.From 1 PLB arranged being arranged in right side
1start, the wherein 1 root line along broken line connects the PLB of 1 row being arranged in left side
2; Be arranged in the PLB of 1 row in left side
2the PLB of 1 row being arranged in right side is connected by this sub-line
3, connect successively, arrive PLB
32loopback structure afterwards by arranging in the interconnection line that is connected with self returns; Then the PLB arranged from left side 1
32start, connect the PLB of 1 row being arranged in right side along this sub-line
31; Be arranged in the PLB of 1 row on right side
31the PLB of 1 row being arranged in left side is connected by this sub-line
30, connect successively, until rap around to the PLB of 1 row being arranged in right side
1; Then remaining two root lines are carried out identical connection successively, until all sub-lines connect complete.
In step 107, broken line comprises the sub-broken line of diagonal line diagonal, every two length be 1 the sub-broken line of diagonal be 1 root line.Figure 12 is the wiring diagram of the sub-broken line of diagonal on adjacent three row PLB, and in figure, the xbar being positioned at middle column is PLB
twiring matrix, this PLB
tthe 3 root lines along broken line connect the PLB of 1 row being arranged in right side
t+1, be implemented as, this PLB
tby 1 sub-broken line of diagonal and the PLB being positioned at same column
t+1connect, the PLB of same column
t+1pLB in being arranged by 1 sub-broken line of diagonal and right side 1
t+1connect; This PLBt is by two sub-broken lines of diagonal and the PLB being positioned at right side of going together simultaneously
tconnect, be positioned at the PLB on colleague right side
tpLB in being arranged by two sub-broken lines of diagonal and right side 1
t+1connect.
This PLB
tthe 3 root lines along broken line connect the PLB of 1 row being arranged in right side
t-1, be implemented as, this PLB
tby two sub-broken lines of diagonal and the PLB being positioned at same column
t-1connect, the PLB of same column
t-1pLB in being arranged by two sub-broken lines of diagonal and right side 1
t-1connect; This PLB simultaneously
tby 1 sub-broken line of diagonal and the PLB being positioned at right side of going together
tconnect, be positioned at the PLB on colleague right side
tpLB in being arranged by 1 sub-broken line of diagonal and right side 1
t-1connect.
This PLB
tthe 3 root lines along broken line connect the PLB of 1 row being arranged in left side
t+1, be implemented as, this PLB
tby two sub-broken lines of diagonal and the PLB being positioned at same column
t+1connect, the PLB of same column
t+1pLB in being arranged by two sub-broken lines of diagonal and left side 1
t+1connect; This PLB simultaneously
tby 1 sub-broken line of diagonal and the PLB being positioned at left side of going together
tconnect, be positioned at the PLB in colleague left side
tpLB in being arranged by 1 sub-broken line of diagonal and left side 1
t+1connect.
This PLB
tthe 3 root lines along broken line connect the PLB of 1 row being arranged in left side
t-1, be implemented as, this PLB
tby 1 sub-broken line of diagonal and the PLB being positioned at same column
t-1connect, the PLB of same column
t-1pLB in being arranged by 1 sub-broken line of diagonal and left side 1
t-1connect; This PLB simultaneously
tby two sub-broken lines of diagonal and the PLB being positioned at left side of going together
tconnect, be positioned at the PLB in colleague left side
tpLB in being arranged by two sub-broken lines of diagonal and left side 1
t-1connect.
Step 108, according to the type and the length that connect the interconnection line of each PLB in each group of PLB, by the input interface of each group of PLB, simultaneously to each group of PLB binary load on described fpga chip according to stream.
In step 108, to the wiring between each PLB completed according to step 103 and 106, each group of PLB with identical type of wiring and length can test simultaneously, such as, when Octal line (as shown in Fig. 3 and Fig. 7) that length is 4 is to the wiring of row and column, can test simultaneously; When Octal line (as shown in Fig. 4 and Fig. 8) that length is 8 is to the wiring of row and column, can test simultaneously; When triple-m molded line (as shown in Fig. 5 and Fig. 9) that length is 3 is to the wiring of row and column, can test simultaneously; When triple-m molded line (as shown in Fig. 6 and Figure 10) that length is 2 is to the wiring of row and column, can test simultaneously.Be implemented as, to there is each PLB of identical type of wiring and length by columns and rows grouping, by the input interface of each group of PLB, simultaneously to each group of continuous binary load of PLB according to stream, be exemplified as: 010111001.To the wiring between each PLB completed according to step 107, the PLB of two row of arbitrary neighborhood is connected by broken line, inconsistent with the connected mode of pressing each PLB in row and column, needs to test separately.The same input port binary load arranged by arbitrary neighborhood two, according to stream, is exemplified as: 010111001.
Step 109, determines the PLB grouping of breaking down according to Output rusults.
In step 109, to the binary data stream according to input in step 108, if the octal line in each group between each PLB connects normal, the output interface so respectively organizing PLB can export and input consistent binary data stream.If there is persistent fault in the octal line between a certain group of PLB, this persistent fault comprise fault, interconnection line that interconnection line is fixed as 0 be fixed as 1 fault and interconnection line be the fault of open circuit.In a kind of specific embodiment, divide into groups to each PLB on fpga chip, each is classified as one group, and often group comprises 32 PLB, every two behavior one group, and often group comprises 38 PLB, is connected by row with the octal line being 4 by length between each PLB of column split; Wherein, by the PLB of the 1st group of column split
5with PLB
9between there is persistent fault 0, so by the input interface of each group of PLB, when inputting 010111001 continuously to each group of PLB, the Output rusults of the 1st group is fixed as 000000000 simultaneously, and other group Output rusults with input consistent.Finally, compare according to by constrained input, the 1st group of PLB can be oriented and break down, and then orient the particular location broken down in the 1st group further.
It should be noted that, according to the method for testing provided in step 109, also can to by row with being connected each PLB by the length octal line that is 8 and testing simultaneously of column split, also can to by row with being connected each PLB by the length triple-m molded line that is 3 and testing simultaneously of column split; Also can to by row with being connected each PLB by the length triple-m molded line that is 2 and testing simultaneously of column split; Also can to by row with being connected each PLB by the length triple-t molded line that is 3 and testing simultaneously of column split; Also can to by row with being connected each PLB by the length triple-t molded line that is 2 and testing simultaneously of column split; Its method of testing with in step 109 to by row with column split to connect the method for testing of each PLB by the length Octal line that is 4 identical.
To sum up, first PLB on chip divides into groups according to row and column by the present invention, the order of packets of row and column does not limit, each row after having divided into groups are connected by the interconnection line of designated length with the PLB in each row, the 1st PLB often organizing the 1st row or the 1st row is connected with input port, the 1st PLB often organizing last 1 row or last 1 row is connected with delivery outlet; Then by broken line, each PLB that two of arbitrary neighborhood are listed on same diagonal line is connected; Finally, to the interconnection line between PLB each on chip, select corresponding test case to test respectively according to the type of interconnection line and length, detect and orient location of fault.Thus achieving only needs little test case just can reach to reach the coverage rate of 100% to the detection of interconnection line between matrix, and is easy to orient detected location of fault.
Professional should recognize further, in conjunction with unit and the algorithm steps of each example of embodiment disclosed herein description, can realize with electronic hardware, computer software or the combination of the two, in order to the interchangeability of hardware and software is clearly described, generally describe composition and the step of each example in the above description according to function.These functions perform with hardware or software mode actually, depend on application-specific and the design constraint of technical scheme.Professional and technical personnel can use distinct methods to realize described function to each specifically should being used for, but this realization should not thought and exceeds scope of the present invention.
The software module that the method described in conjunction with embodiment disclosed herein or the step of algorithm can use hardware, processor to perform, or the combination of the two is implemented.Software module can be placed in the storage medium of other form any known in random access memory (RAM), internal memory, ROM (read-only memory) (ROM), electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM or technical field.
Above-described embodiment; object of the present invention, technical scheme and beneficial effect are further described; be understood that; the foregoing is only the specific embodiment of the present invention; the protection domain be not intended to limit the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. a method of testing for field programmable gate array interconnection line persistent fault, is characterized in that,
Programmed logical module PLB on field programmable gate array fpga chip is divided into M group by row, and often group comprises the PLB of m row, and wherein, M, m are natural number;
All be connected often organizing PLB with the input interface on described chip and output interface;
Be each PLB that the interconnection line of L1 connects in described M group successively according to the length preset; Wherein, the interconnection line of the marginal portion often in row is provided with loopback structure, after interconnection line reaches top boundary or afterbody border, is returned by described loopback structure;
According to the length connecting the interconnection line of each PLB in each group of PLB, by the input interface of each group of PLB, to each group of PLB binary load on described fpga chip according to stream; The PLB grouping of breaking down is determined according to Output rusults.
2. method according to claim 1, is characterized in that, the method also comprises:
Often arrange PLB and comprise a PLB, be followed successively by PLB from afterbody to top
1, PLB
2..., PLB
a;
Length according to presetting is L
3interconnection line connect the PLB of each row in every group successively
1.
3. method according to claim 1, is characterized in that, the method also comprises:
PLB on fpga chip is divided into N group by row, and often group comprises the capable PLB of n, and wherein, N, n are natural number;
All be connected often organizing PLB with the input interface on described chip and output interface;
Length according to presetting is L
2interconnection line connect each PLB in described N group successively; Wherein, the interconnection line of the marginal portion often in row is provided with loopback structure, after interconnection line reaches right side boundary or left border, is returned by described loopback structure.
4. method according to claim 3, is characterized in that, the method also comprises:
Often row PLB comprises b PLB, is followed successively by PLB from left side to right side
1, PLB
2..., PLB
b;
Length according to presetting is L
3interconnection line connect the PLB of each row in every group successively
1.
5. a method of testing for field programmable gate array interconnection line persistent fault, is characterized in that,
PLB on fpga chip is divided into N group by row, and often group comprises the capable PLB of n, and wherein, N, n are natural number;
All be connected often organizing PLB with the input interface on described chip and output interface;
Be each PLB that the interconnection line of L2 connects in described N group successively according to the length preset; Wherein, the interconnection line of the marginal portion often in row is provided with loopback structure, after interconnection line reaches right side boundary or left border, is returned by described loopback structure;
According to the length connecting the interconnection line of each PLB in each group of PLB, by the input interface of each group of PLB, to each group of PLB binary load on described fpga chip according to stream;
The PLB grouping of breaking down is determined according to Output rusults.
6. method according to claim 5, is characterized in that, the method also comprises:
Often row PLB comprises b PLB, is followed successively by PLB from left side to right side
1, PLB
2..., PLB
b;
Length according to presetting is L
3interconnection line connect the PLB of each row in every group successively
1.
7. method according to claim 5, is characterized in that, the method also comprises:
PLB on fpga chip is divided into M group by row, and often group comprises the PLB of m row, and wherein, M, m are natural number;
All be connected often organizing PLB with the input interface on described chip and output interface;
Length according to presetting is L
1interconnection line connect each PLB in described M group successively; Wherein, the interconnection line of the marginal portion often in row is provided with loopback structure, after interconnection line reaches top boundary or afterbody border, is returned by described loopback structure.
8. method according to claim 7, is characterized in that, the method also comprises:
Often arrange PLB and comprise a PLB, be followed successively by PLB from afterbody to top
1, PLB
2..., PLB
a;
Length according to presetting is L
3interconnection line connect the PLB of each row in every group successively
1.
9. method according to claim 1 or 5, it is characterized in that, the method comprises further:
To two row PLB of arbitrary neighborhood on fpga chip, described two row PLB are connected with input interface and output interface, connect two PLB on a diagonal line in two row of arbitrary neighborhood according to broken line successively; Wherein, the interconnection line of the marginal portion often in row is provided with loopback structure, after broken line arrives top boundary or afterbody border, is returned by described loopback structure.
10. method according to claim 1 or 5, it is characterized in that, the method comprises further:
Often arrange PLB and comprise a PLB, be followed successively by PLB from afterbody to top
1, PLB
2..., PLB
a;
Length according to presetting is L
3interconnection line connect two row PLB in PLB
1.
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