CN101038324A - Testing method capable of configuring FPGA interconnection resource with four times - Google Patents
Testing method capable of configuring FPGA interconnection resource with four times Download PDFInfo
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- CN101038324A CN101038324A CN 200710063889 CN200710063889A CN101038324A CN 101038324 A CN101038324 A CN 101038324A CN 200710063889 CN200710063889 CN 200710063889 CN 200710063889 A CN200710063889 A CN 200710063889A CN 101038324 A CN101038324 A CN 101038324A
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Abstract
The present invention provides a testing method of the FPGA interconnecting resources completed by four times of configuring. The characteristics reside in: the switch matrixes are divided into four kinds: the level, the upright, the left oblique and the right oblique according to the connection direction. In each configuring, the testing circuit is designed according to one connection direction. The switch matrixes are concatenated to form snake shaped testing accesses and each access is added with a testing vector of walk step -1. In the present invention, the testing of the FPGA interconnecting resources is completed effectively, and the a 100% testing coverage rate is achieved, and the connection is easy to realize, also, the times of configuration testing and the testing cost are greatly reduced.
Description
Technical field
The present invention relates to a kind of method of testing of fpga chip, particularly only just finish the method for testing of FPGA interconnect resource with four configurations.
Background technology
The prerequisite that FPGA is tested is that it is configured, and designs multiple test circuit and could realize Validity Test FPGA through the process of repeatedly configuration-test.And the time cost of disposing a FPGA is more much more than applying a test vector, is to reduce configured number under the prerequisite that guarantees test coverage so improve the key of FPGA testing efficiency as far as possible.
In the practical application of FPGA, fault betides the probability of interconnect resource much larger than the probability that betides other logic functions, and the method for testing of therefore studying interconnect resource is significant to the yield rate that improves FPGA.Abroad the test problem of FPGA interconnect resource is studied, proposed six configurations and finished the method for interconnect resource test, and to apply with the counting sequence be the test vector of pattern.This method test configurations number of times is more, and the annexation design is complicated, and the test vector of counting sequence can not effectively be located the position of breaking down in actual test process.And domesticly still being in the starting stage in FPGA measurement direction research, relevant achievement is less.
Summary of the invention
Technology of the present invention is dealt with problems and is: reach at the interconnect resource test coverage under 100% the prerequisite, reduce the test configurations number of times as far as possible, provide a kind of four configurations to finish the method for testing of FPGA interconnect resource, this method is by coming to realize respectively that from four direction the interconnection resources level is linked to be snake net with four kinds of configurations, and apply walking-1 test vector, the test configurations that has overcome previous methods often, switch connects complicated, test vector can not effectively be distinguished the shortcoming of abort situation.
Technical solution of the present invention is: the method for testing of FPGA interconnect resource is finished in four configurations, and configuration for the first time comprises the following steps:
(1) with the direction level switch gating of each switch matrix.
(2) each gating switch of cascade, each path forms the snakelike test channel of level.
(3) snake net that connection is finished applies walking-1 test vector.
The switch of each switch matrix institute gating is WE switch (12) in the described step (1).
Cascade mode is a headtotail in the described step (2), and the test channel of crawling covers all horizontal interconnect line segments in order.
Walking-1 vector is applied on each test channel simultaneously in the described step (3).
Configuration for the second time comprises the following steps:
(1) with the vertical direction switching gate of each switch matrix.
(2) each gating switch of cascade, each path forms a vertical snakelike test channel.
(3) snake net that connection is finished applies walking-1 test vector.
The switch of each switch matrix institute gating is SN switch (14) in the described step (1).
Cascade mode is a headtotail in the described step (2), and the test channel of crawling covers all perpendicular interconnection line segments in order.
Walking-1 vector is applied on each test channel simultaneously in the described step (3)
Configuration for the third time comprises the following steps:
(1) with the left tilted direction switching gate of each switch matrix.
(2) each gating switch of cascade, each path forms the oblique snakelike test channel in a left side.
(3) snake net that connection is finished applies walking-1 test vector.
The switch of each switch matrix institute gating is WS switch (11) and EN switch (15) in the described step (1).
Cascade mode is a headtotail in the described step (2), and the test channel of crawling covers tiltedly interconnect line segment of all left sides in order.
Walking-1 vector is applied on each test channel simultaneously in the described step (3)
The 4th configuration comprises the following steps:
(1) with the right tilted direction switching gate of each switch matrix.
(2) each gating switch of cascade, each path forms the oblique snakelike test channel in the right side.
(3) snake net that connection is finished applies walking-1 test vector.
The switch of each switch matrix institute gating is ES switch (16) and WN switch (13) in the described step (1).
Cascade mode is a headtotail in the described step (2), and the test channel of crawling covers all right tiltedly interconnect line segment in order.
Walking-1 vector is applied on each test channel simultaneously in the described step (3)
The present invention's beneficial effect compared with prior art is:
(1) the present invention has reduced FPGA test configurations number of times owing to realize the snakelike test network of cascade by level, vertical, left oblique, right tiltedly four direction, has improved testing efficiency.
(2) the present invention has effectively improved measuring resolution because each snakelike test channel has been applied walking-1 test vector.
(3) the present invention has avoided problems such as test repeats, test omission, and has simplified annexation owing to press direction cascaded switch pipe clocklike, makes test coverage reach 100%.
Description of drawings
Fig. 1 is the basic structure synoptic diagram of FPGA;
Fig. 2 is the basic structure synoptic diagram of switch matrix;
Fig. 3 is the snakelike test structure synoptic diagram of horizontal direction among the present invention;
Fig. 4 is the snakelike test structure synoptic diagram of vertical direction among the present invention;
Fig. 5 is the snakelike test structure synoptic diagram of left tilted direction among the present invention;
Fig. 6 is the snakelike test structure synoptic diagram of right tilted direction among the present invention;
Fig. 7 is the walking-1 test vector synoptic diagram among the present invention.
Embodiment
FPGA basic structure as shown in Figure 1, its basic structure is by programmed logical module CLB1, programmable switch matrix SM2 and interconnect line segment 3 are formed.Switch matrix SM2 and interconnect line segment 3 form reticulate texture around FPGA (Field Programmable Gate Array), have realized programmability flexibly.
The structure of switch matrix SM2 as shown in Figure 2, it is divided into West, South, East and North totally 4 types switch, by the West-East direction switch with switch matrix SM2 is that WE switch 12, South-North direction switch are that SN switch 14, West-North direction switch are that WN switch 13, West-South direction switch are that WS switch 11, East-North direction switch are that EN switch 15 and East-South direction switch are the method for ES switch 16 by division equidirectional cascade, forms snakelike test channel and tests.The test that is applied among the present invention in for walking-1 test vector, its principle as shown in Figure 7, in all k test channel, each vector can only have one 1 simultaneously, other all are 0, this vector 1 is finished test to all passages by order " walking " displacement in k test channel, so be called walking-1 test vector.
Below the present invention is described in more detail.
The present invention divides 4 steps to finish test to the FPGA interconnect resources.
Configuration for the first time may further comprise the steps:
(1) with direction level switch pipe WE switch 12 gating of each switch matrix.
(2) as shown in Figure 3, each gating switch of cascade in order, the end of each path takes back next bar path, forms the snakelike test channel of a level.
(3) serpentine channel input end in1 that connection is finished and in2 are exerted into walking-1 test vector as shown in Figure 7, in output terminal out1 and out2 observation test result.Horizontal direction can have many test channel according to the FPGA scale, generally can be 8～12 test channel, and each passage is finished test respectively.
Configuration for the second time may further comprise the steps:
(1) with vertical direction switching tube SN switch 14 gating of each switch matrix.
(2) as shown in Figure 4, each gating switch of cascade in order, the end of each path takes back next bar path, forms a vertical snakelike test channel.
(3) serpentine channel input end in1 and the in2 that connection is finished is exerted into walking shown in Figure 7-1 test vector, in output terminal out1 and out2 observation test result, vertical direction can have many test channel according to the FPGA scale, generally can be 8～12 test channel, each passage is finished test respectively.
Configuration for the third time may further comprise the steps:
(1) with the left tilted direction switching tube WS switch 11 and EN switch 15 gating of each switch matrix.
(2) as shown in Figure 5, each gating switch of cascade in order, the end of each path takes back next bar path, forms a snakelike test channel that a left side is oblique.
(3) serpentine channel input end in1 and the in2 that connection is finished is exerted into walking shown in Figure 7-1 test vector, in output terminal out1 and out2 observation test result, left side tilted direction can have many test channel according to the FPGA scale, generally can be 8～12 test channel, each passage is finished test respectively.
The 4th configuration may further comprise the steps:
(1) with the right tilted direction switching tube ES switch 16 and WN switch 13 gating of each switch matrix.
(2) as shown in Figure 6, each gating switch of cascade in order, the end of each path takes back next bar path, forms a snakelike test channel that the right side is oblique.
(3) serpentine channel input end in1 and the in2 that connection is finished is exerted into walking shown in Figure 7-1 test vector, in output terminal out1 and out2 observation test result, right tilted direction can have many test channel according to the FPGA scale, generally can be 8～12 test channel, each passage is finished test respectively.
Claims (9)
1, the method for testing of FPGA interconnect resource is finished in four configurations, it is characterized in that comprising four configurations, and wherein configuration step is as follows for the first time:
(1) with the direction level switch gating of each switch matrix, i.e. WE switch (12);
(2) each gating switch of cascade, each path forms the snakelike test channel of level;
(3) snake net that connection is finished applies test vector;
Configuration step is as follows for the second time:
(4) with the vertical direction switching gate of each switch matrix, i.e. SN switch (14);
(5) each gating switch of cascade, each path forms a vertical snakelike test channel;
(6) snake net that connection is finished applies test vector;
Configuration step is as follows for the third time:
(7) with the left tilted direction switching gate of each switch matrix, i.e. WS switch (11) and EN switch (15);
(8) each gating switch of cascade, each path forms the oblique snakelike test channel in a left side;
(9) snake net that connection is finished applies test vector;
The 4th time configuration step is as follows:
(10) with the right tilted direction switching gate of each switch matrix, i.e. ES switch (16) and WN switch (13);
(11) each gating switch of cascade, each path forms the oblique snakelike test channel in the right side;
(12) snake net that connection is finished applies test vector.
2, the method for testing of FPGA interconnect resource is finished in four configurations according to claim 1, and it is characterized in that: cascade mode is a headtotail in the described step (2), and the test channel of crawling covers all horizontal interconnect line segments in order.
3, the method for testing of FPGA interconnect resource is finished in four configurations according to claim 1, and it is characterized in that: test vector is walking-1 vector in the described step (3), and is applied to simultaneously on each test channel.
4, the method for testing of FPGA interconnect resource is finished in four configurations according to claim 1, and it is characterized in that: cascade mode is a headtotail in the described step (5), and the test channel of crawling covers all perpendicular interconnection line segments in order.
5, the method for testing of FPGA interconnect resource is finished in four configurations according to claim 1, and it is characterized in that: test vector is walking-1 vector in the described step (6), and is applied to simultaneously on each test channel
6, the method for testing of FPGA interconnect resource is finished in four configurations according to claim 1, and it is characterized in that: cascade mode is a headtotail in the described step (8), and the test channel of crawling covers tiltedly interconnect line segment of all left sides in order.
7, the method for testing of FPGA interconnect resource is finished in four configurations according to claim 1, and it is characterized in that: test vector is walking-1 vector in the described step (9), and is applied to simultaneously on each test channel.
8, the method for testing of FPGA interconnect resource is finished in four configurations according to claim 1, and it is characterized in that: cascade mode is a headtotail in the described step (11), and the test channel of crawling covers all right tiltedly interconnect line segment in order.
9, the method for testing of FPGA interconnect resource is finished in four configurations according to claim 1, and it is characterized in that: test vector is walking-1 vector in the described step (12), and is applied to simultaneously on each test channel.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102116841A (en) * | 2011-01-04 | 2011-07-06 | 复旦大学 | Method for evaluating FPGA (Field Programmable Gata Array) interconnection structure based on quantization of model |
| CN102809711A (en) * | 2011-12-01 | 2012-12-05 | 中国电子科技集团公司第五十八研究所 | Wire spreading method for testing FPGA (Field Programmable Gata Array) single long line and linked switch |
| CN106841894A (en) * | 2016-12-23 | 2017-06-13 | 深圳市国微电子有限公司 | FPGA interconnects wire testing method and device |
| CN107064783A (en) * | 2016-12-08 | 2017-08-18 | 中国空间技术研究院 | The detection circuit and detection method of look-up table in a kind of fpga chip |
| CN107452426A (en) * | 2017-07-24 | 2017-12-08 | 中国空间技术研究院 | The detection circuit and detection method of memory element in a kind of fpga chip |
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2007
- 2007-02-14 CN CNB2007100638898A patent/CN100495058C/en active Active
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102116841A (en) * | 2011-01-04 | 2011-07-06 | 复旦大学 | Method for evaluating FPGA (Field Programmable Gata Array) interconnection structure based on quantization of model |
| CN102116841B (en) * | 2011-01-04 | 2014-09-03 | 复旦大学 | Method for evaluating FPGA (Field Programmable Gata Array) interconnection structure based on quantization of model |
| CN102809711A (en) * | 2011-12-01 | 2012-12-05 | 中国电子科技集团公司第五十八研究所 | Wire spreading method for testing FPGA (Field Programmable Gata Array) single long line and linked switch |
| CN102809711B (en) * | 2011-12-01 | 2014-07-02 | 中国电子科技集团公司第五十八研究所 | Wire spreading method for testing FPGA (Field Programmable Gata Array) single long line and linked switch |
| CN107064783A (en) * | 2016-12-08 | 2017-08-18 | 中国空间技术研究院 | The detection circuit and detection method of look-up table in a kind of fpga chip |
| CN107064783B (en) * | 2016-12-08 | 2019-10-29 | 中国空间技术研究院 | The detection circuit and detection method of look-up table in a kind of fpga chip |
| CN106841894A (en) * | 2016-12-23 | 2017-06-13 | 深圳市国微电子有限公司 | FPGA interconnects wire testing method and device |
| CN106841894B (en) * | 2016-12-23 | 2020-02-11 | 深圳市国微电子有限公司 | FPGA interconnection line testing method and device |
| CN107452426A (en) * | 2017-07-24 | 2017-12-08 | 中国空间技术研究院 | The detection circuit and detection method of memory element in a kind of fpga chip |
| CN107452426B (en) * | 2017-07-24 | 2020-04-07 | 中国空间技术研究院 | Detection circuit and detection method for storage element in FPGA chip |
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