CN106782387A - GOA drive circuits - Google Patents
GOA drive circuits Download PDFInfo
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- CN106782387A CN106782387A CN201611254809.2A CN201611254809A CN106782387A CN 106782387 A CN106782387 A CN 106782387A CN 201611254809 A CN201611254809 A CN 201611254809A CN 106782387 A CN106782387 A CN 106782387A
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- output channel
- goa
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention discloses a kind of GOA drive circuits, including the mutually multistage GOA unit of cascade, it is used to drive one-row pixels unit per one-level GOA unit, the GOA unit is with the first output channel, the second output channel and time-sequence control module：First output channel is used to receive and transmit the scanning voltage signal of setting；Second output channel is used to receive and transmit the time delay voltage signal of setting；The time-sequence control module is used to be switched on or off individually first output channel and the second output channel in different time ordered intervals, generates the line scan signals of the GOA unit with the time delay voltage signal of the setting with the scanning voltage signal according to the setting.The mistake that the GOA drive circuits solve the liquid crystal display data-signal of GOA frameworks fills problem, improves the display effect of product, improves the quality of product.And the GOA drive circuit low production costs, be conducive to being lifted the competitiveness of product.
Description
Technical field
The invention belongs to technical field of liquid crystal display, more particularly to a kind of GOA drive circuits.
Background technology
Liquid crystal display TFT-LCD (Thin Film Transistor Liquid Crystal Display) is current
One of principal item of FPD, has become important display platform in modern IT, video product.In recent years, it is full
The demand of sufficient ultra-narrow frame and reduces cost, GOA (Gate On Array) technology is developed rapidly.
The liquid crystal display as shown in figure 1, mainly including raster data model on array base palte of framework is driven based on GOA
Circuit integrated region (Gate Driver integrated on Array) a1, viewing area (Display Area) a2 and
Fan-out area (Fan Out Area) a3, in addition, the pcb board for being provided with peripheral drive circuit passes through flexible package S-COF1~S-
COF4 is connected with array base palte.
Line scan signals of the liquid crystal display of framework in real work are driven as shown in Fig. 2 Input [N] based on GOA
What is represented is the line scan signals of the line n pixel cell of drive circuit Gate sides output, and what Input [N+1] was represented is to drive
The line scan signals of the (n+1)th row pixel cell of circuit Gate sides output.Because the electric capacity of panel itself, resistance are to the shadow of signal
Ring, when above-mentioned line scan signals are transmitted to scan line end via scan line, its signal waveform will occur as shown in Figure 2
Change, referring specifically to signal End [N] in figure and End [N+1], wherein, what End [N] was represented be transmit to scan line end
The line scan signals of line n pixel cell, the (n+1)th row pixel cell for being transferred to scan line end that End [N+1] is represented
Line scan signals.As can be seen that compared to the signal Input [N] and Input [N+1], End of the just output of drive circuit Gate sides
[N] and End [N+1] there occurs serious distorted signals, and due to distorted signals so that there is lap in signal, this will lead
Causing adjacent rows pixel cell can be unlocked simultaneously, in turn result in mistake and fill phenomenon, by the data signal transmission of mistake to pixel list
Unit, influences the display of liquid crystal display.
The content of the invention
One of technical problems to be solved by the invention are solved due to the data of pixel cell caused by distorted signals
The problem of signal transmission errors.
In order to solve the above-mentioned technical problem, embodiments herein provide firstly a kind of GOA drive circuits, including mutual
The multistage GOA unit of cascade, is used to drive one-row pixels unit per one-level GOA unit, and the GOA unit is logical with the first output
Road, the second output channel and time-sequence control module：First output channel is used to receive and transmit the scanning voltage of setting
Signal；Second output channel is used to receive and transmit the time delay voltage signal of setting；The time-sequence control module is used for
First output channel and the second output channel are switched on or off individually in different time ordered intervals, with according to the setting
Scanning voltage signal generates the line scan signals of the GOA unit with the time delay voltage signal of the setting.
Preferably, the time-sequence control module is configured as：Rear stage GOA is closed in the corresponding time ordered interval of crossover region
First output channel of unit, and open the second output channel of the rear stage GOA unit；In addition to the crossover region
The first output channel of rear stage GOA unit is opened in time ordered interval, and it is logical to close the second output of the rear stage GOA unit
Road；Wherein, the scanning voltage signal of the setting of adjacent two-stage GOA unit is corresponded respectively to, when scan line end is reached
Form the crossover region.
Preferably, the time-sequence control module is configured as：Line scan signals according to previous stage GOA unit are generated and defeated
Go out control signal, the control signal be used to being switched on or off individually in different time ordered intervals first output channel with
Second output channel.
Preferably, the time-sequence control module is configured as：When the line scan signals of previous stage GOA unit are cut from high voltage
When being changed to low-voltage, first output channel is closed, and open second output channel；When closing, first output is logical
Road is simultaneously opened after second output channel reaches the delay time of setting, opens first output channel, and close described
Second output channel.
Preferably, scanning voltage signal of the delay time of the setting according to the setting of adjacent two-stage GOA unit
The crossover region formed when scan line end is reached determines.
Preferably, first output channel includes first switch element, and its input connects the scanning electricity of the setting
Pressure signal, its control end connects the control signal；Second output channel includes second switch element, the connection of its input
The time delay voltage signal of the setting, its control end connects the control signal；The first switch element and second switch unit
The output end of part is coupled together, used as the line scan signals output end of the GOA unit.
Preferably, the first switch element is P-type TFT, and the second switch element is N-type film crystal
Pipe.
Preferably, the time delay voltage signal of the setting includes fixed low voltage signal.
Preferably, the time-sequence control module is arranged between the arbitrary neighborhood two-stage GOA unit of GOA drive circuits side
Fan-out area in.
Compared with prior art, one or more embodiments in such scheme can have the following advantages that or beneficial effect
Really：
The crossover region between line scan signals is adjusted by using the GOA unit with time-sequence control module, is solved
The mistake of data-signal of liquid crystal display of GOA frameworks of having determined fills problem, improves the display effect of product, improves product
Quality.And the GOA drive circuit low production costs, be conducive to being lifted the competitiveness of product.
Other advantages of the invention, target, and feature will be illustrated in the following description to a certain extent, and
And to a certain extent, based on being will be apparent to those skilled in the art to investigating hereafter, Huo Zheke
To be instructed from the practice of the present invention.Target of the invention and other advantages can be wanted by following specification, right
Specifically noted structure in book, and accompanying drawing is asked to realize and obtain.
Brief description of the drawings
Accompanying drawing is used for providing to the technical scheme of the application or further understanding for prior art, and constitutes specification
A part.Wherein, the accompanying drawing of expression the embodiment of the present application is used to explain the technical side of the application together with embodiments herein
Case, but do not constitute the limitation to technical scheme.
Fig. 1 is the structural representation of the liquid crystal display for driving framework based on GOA in the prior art；
Fig. 2 is that the waveform of line scan signals in the prior art occurs the schematic diagram of distortion；
Fig. 3 is the structural representation of the GOA drive circuits according to first embodiment of the invention；
Fig. 4 is the structural representation of the GOA drive circuits according to second embodiment of the invention；
Fig. 5 is the timing diagram of the GOA drive circuits according to second embodiment of the invention.
Specific embodiment
Describe embodiments of the present invention in detail below with reference to drawings and Examples, how the present invention is applied whereby
Technological means solves technical problem, and reaches the implementation process of relevant art effect and can fully understand and implement according to this.This Shen
Each feature that please be in embodiment and embodiment, can be combined with each other under the premise of not colliding, the technical scheme for being formed
Within protection scope of the present invention.
First embodiment：
Fig. 3 is the structural representation of the GOA drive circuits according to first embodiment of the invention, and the GOA of the embodiment drives
Circuit includes the GOA unit of multistage mutually cascade, it is used to drive one-row pixels unit per one-level GOA unit, Fig. 3 is illustrated that
The N grades of structural representation of GOA unit.As illustrated, the GOA unit has the first output channel 31, the second output channel 32
And time-sequence control module 33.
First output channel 31 receives what drive circuit Gate sides exported, that is, scanning voltage signal Input [N] for setting,
And can be after first output channel 31 unlatching, the scanning voltage signal transmission that will be set to output end Output [N].
Second output channel 32 receives the output of drive circuit Gate sides, that is, the time delay voltage signal VGL for setting, it is possible to
After second output channel 32 unlatching, the time delay voltage signal VGL of setting is transmitted to output end Output [N].
Time-sequence control module 33 is connected with the first output channel 31 with the second output channel 32 respectively, for different
The first output channel 31 and the second output channel 32 are switched on or off individually in time ordered interval.
The common output end Output [N] of the first output channel 31 and the second output channel 32 is used as the GOA unit
Row sweeps signal output part, and the line scan signals of its output are the setting exported by the first output channel 31 in different time ordered intervals
Scanning voltage signal Input [N] generated jointly with the time delay voltage signal VGL of the setting exported by the second output channel 32.
Further, the crossover region that time-sequence control module 33 can be produced according to line scan signals due to distortion is come to
One output channel 31 is controlled with the second output channel 32.
As shown in Fig. 2 due to distorted signals, causing there is crossover region T between signal End [N] and signal End [N+1].
Because in crossover region T, signal End [N] and signal End [N+1] is high level signal, therefore, by data signals
Mistake rushes phenomenon.In the present embodiment, in the crossover region signal is not exported, then can eliminate signal End [N] with letter
Overlapping phenomenon between number End [N+1].
In a specific embodiment of the invention, rear stage can be closed in the corresponding time ordered interval of crossover region
First output channel 31 of GOA unit (N+1 grades), and the second output channel 32 of rear stage GOA unit is opened, make rear stage
GOA unit can not export the scanning voltage signal of setting.And, in the time ordered interval in addition to crossover region, open rear stage
First output channel 31 of GOA unit, and the second output channel 32 of rear stage GOA unit is closed, make rear stage GOA unit just
The scanning voltage signal of often output setting.
By setting time-sequence control module 33, and sweeping according to the setting of adjacent two-stage GOA unit in every grade of GOA unit
Retouch the voltage signal output of the crossover region that is formed to GOA unit when scan line end is reached to be controlled, eliminate adjacent
It is overlapping between line scan signals, the mistake of data signals can be avoided to fill problem.
Second embodiment：
Fig. 4 is the structural representation of the GOA drive circuits according to second embodiment of the invention, as illustrated, in the present invention
In embodiment, the line scan signals according to previous stage GOA unit are controlled to each output channel of rear stage GOA unit, tool
Body is that time-sequence control module 33 is generated and export control according to the line scan signals (N grades of Output [N]) of previous stage GOA unit
Signal OE processed, control signal OE are defeated with second for being switched on or off individually the first output channel 31 in different time ordered intervals
Go out passage 32.Illustrated with reference to Fig. 4.
First output channel 31 is made up of P-type TFT A1, and source electrode and the scanning voltage of GOA unit setting of A1 are believed
Number Input [N+1] is connected, and as the output end of line scan signals, its grid is connected with control signal OE for its drain electrode.
Second output channel 32 is made up of N-type TFT A2, the time delay voltage signal VGL phases of the source electrode of A2 and setting
Connection, its output end drained as line scan signals, its grid is connected with control signal OE.
Wherein, VGL is generally the low voltage signal of a fixation, preferably can be invalid with the scanning voltage signal of setting
The corresponding low voltage signal of sweep interval, i.e. low level.
The drain electrode of thin film transistor (TFT) A1 and A2 is coupled together, and exports the line scan signals Output [N+1] of GOA unit.
When control signal OE is high level signal, A1 is closed, and A2 is opened, and VGL is via A2 outputs to Output [N+
1], when control signal OE is low level signal, A1 is opened, and A2 is closed, and Input [N] is via A1 outputs to Output [N+
1], i.e., being turned on and off for the first output channel 31 and the second output channel 32 is controlled by control signal OE.
Further, time-sequence control module 33 receives (N grades) line scan signals Output of output of previous stage GOA unit
[N], and it is the GOA according to second embodiment of the invention to generate control signal OE, Fig. 5 according to line scan signals Output [N]
The timing diagram of drive circuit, illustrates with reference to Fig. 5.
When the line scan signals Output [N] of previous stage GOA unit switches to low-voltage from high voltage, SECO mould
Block 33 exports a control signal OE for direct impulse, and the high voltage of control signal OE closes P-type TFT A1, will
N-type TFT A2 is opened, then this grade of low potential of output end Output [N+1] the outputs VGL of GOA unit.Now, this level
The normal output that GOA unit is used for the scanning voltage signal of the setting of the valid interval for forming line scan signals is forced shut-off,
The generation and the line scan signals Output [N] of previous stage GOA unit between can be avoided overlapping.
After the high voltage of control signal OE continues the delay time of a setting, control signal OE drops to low-voltage, this
When P-type TFT A1 open, and N-type TFT A2 is closed, and Output [N+1] can normally export the scanning of setting
Voltage signal Input [N+1].
By closing P-type TFT A1 (i.e. the first output channel 31) in specific time ordered interval, realize
Interval between Output [N] and Output [N+1] so that Output [N] and Output [N+1] is transmitted to scan line end
When, non-overlapping area between signal End [N] and End [N+1] eliminates mistake and fills phenomenon, as shown in Figure 5.
The delay time of control signal OE lasting setting can be according to the scanning of the setting of adjacent two-stage GOA unit electricity
Press the crossover region that signal is formed when scan line end is reached to determine, referring specifically to first embodiment, here is omitted.
Further, since the situation of different display panels is different, thus the specific effect of control signal OE time with
And delay time (i.e. the width of pulse) can be adjusted according to actually used situation.Can be in time-sequence control module 33
The delay time of design initial stage just lasting to control signal OE setting sets, after the completion of setting, it is not necessary to it is extra again
The other control signals of addition can just utilize the line scan signals of previous stage GOA unit output to be controlled OE.
The embodiment of the present invention is arranged on being fanned out between the two-stage GOA unit of the arbitrary neighborhood of GOA drive circuits side
In region, therefore can be defeated in the GOA of each grid in the fan-out area of the Gate sides on the panel of traditional GOA frameworks
Going out end increases extra structure to realize, circuit structure is simple, advantageously reduces control cost.
It should be noted that being readily appreciated that, first order GOA unit is in the absence of time-sequence control module corresponding thereto.
Although disclosed herein implementation method as above, described content is only to facilitate understanding the present invention and adopting
Implementation method, is not limited to the present invention.Any those skilled in the art to which this invention pertains, are not departing from this
On the premise of the disclosed spirit and scope of invention, any modification and change can be made in the formal and details implemented,
But scope of patent protection of the invention, must be still defined by the scope of which is defined in the appended claims.
Claims (9)
1. a kind of GOA drive circuits, including the mutually multistage GOA unit of cascade, are used to drive one-row pixels per one-level GOA unit
Unit, the GOA unit has the first output channel, the second output channel and time-sequence control module：
First output channel is used to receive and transmit the scanning voltage signal of setting；
Second output channel is used to receive and transmit the time delay voltage signal of setting；
The time-sequence control module is used to be switched on or off individually first output channel and the in different time ordered intervals
Two output channels, generate the GOA mono- with the scanning voltage signal according to the setting and the time delay voltage signal of the setting
The line scan signals of unit.
2. GOA drive circuits according to claim 1, it is characterised in that the time-sequence control module is configured as：
The first output channel of rear stage GOA unit is closed in the corresponding time ordered interval of crossover region, and opens the rear stage
Second output channel of GOA unit；
The first output channel of rear stage GOA unit is opened in the time ordered interval in addition to the crossover region, and is closed described
Second output channel of rear stage GOA unit；
Wherein, the scanning voltage signal of the setting of adjacent two-stage GOA unit is corresponded respectively to, when scan line end is reached
Form the crossover region.
3. GOA drive circuits according to claim 1, it is characterised in that the time-sequence control module is configured as：
Line scan signals generation and output control signal according to previous stage GOA unit, the control signal are used for different
First output channel and the second output channel are switched on or off individually in time ordered interval.
4. GOA drive circuits according to claim 3, it is characterised in that the time-sequence control module is configured as：
When the line scan signals of previous stage GOA unit switch to low-voltage from high voltage, first output channel is closed, and
Open second output channel；
After closing first output channel and opening second output channel and reach the delay time of setting, open described
First output channel, and close second output channel.
5. GOA drive circuits according to claim 4, it is characterised in that the delay time of the setting is according to adjacent two
The crossover region that the scanning voltage signal of the setting of level GOA unit is formed when scan line end is reached determines.
6. GOA drive circuits according to claim 3, it is characterised in that
First output channel includes first switch element, and its input connects the scanning voltage signal of the setting, its control
End processed connects the control signal；
Second output channel includes second switch element, and its input connects the time delay voltage signal of the setting, its control
End processed connects the control signal；
The first switch element is coupled together with the output end of second switch element, used as the row scanning of the GOA unit
Signal output part.
7. GOA drive circuits according to claim 6, it is characterised in that the first switch element is p-type film crystal
Pipe, the second switch element is N-type TFT.
8. GOA drive circuits according to claim 1, it is characterised in that the time delay voltage signal of the setting includes solid
Fixed low voltage signal.
9. GOA drive circuits according to claim 1, it is characterised in that the time-sequence control module is arranged on GOA drivings
In fan-out area between the arbitrary neighborhood two-stage GOA unit of circuit side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611254809.2A CN106782387B (en) | 2016-12-30 | 2016-12-30 | GOA driving circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611254809.2A CN106782387B (en) | 2016-12-30 | 2016-12-30 | GOA driving circuit |
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| CN106782387A true CN106782387A (en) | 2017-05-31 |
| CN106782387B CN106782387B (en) | 2019-11-05 |
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| CN201611254809.2A Active CN106782387B (en) | 2016-12-30 | 2016-12-30 | GOA driving circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109637407A (en) * | 2019-01-09 | 2019-04-16 | 惠科股份有限公司 | A kind of driving method of method, apparatus that repairing display panel and display panel |
| CN110992868A (en) * | 2019-12-20 | 2020-04-10 | 京东方科技集团股份有限公司 | Display substrate driving method and device and display device |
| CN113380168A (en) * | 2021-05-20 | 2021-09-10 | 北海惠科光电技术有限公司 | Shift register, gate drive circuit and display panel |
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| CN105304044A (en) * | 2015-11-16 | 2016-02-03 | 深圳市华星光电技术有限公司 | Liquid crystal display device and GOA circuit |
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| JPH0879053A (en) * | 1994-09-06 | 1996-03-22 | Toshiba Corp | Level shift circuit |
| KR20050039183A (en) * | 2003-10-24 | 2005-04-29 | 엘지.필립스 엘시디 주식회사 | Apparatus of driving liquid crystal display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109637407A (en) * | 2019-01-09 | 2019-04-16 | 惠科股份有限公司 | A kind of driving method of method, apparatus that repairing display panel and display panel |
| CN110992868A (en) * | 2019-12-20 | 2020-04-10 | 京东方科技集团股份有限公司 | Display substrate driving method and device and display device |
| CN110992868B (en) * | 2019-12-20 | 2022-08-16 | 京东方科技集团股份有限公司 | Display substrate driving method and device and display device |
| CN113380168A (en) * | 2021-05-20 | 2021-09-10 | 北海惠科光电技术有限公司 | Shift register, gate drive circuit and display panel |
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| CN106782387B (en) | 2019-11-05 |
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