CN101127199A - Gate driver for outputting superposition-free scanning signal, liquid crystal display and method - Google Patents
Gate driver for outputting superposition-free scanning signal, liquid crystal display and method Download PDFInfo
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- CN101127199A CN101127199A CNA2007101487378A CN200710148737A CN101127199A CN 101127199 A CN101127199 A CN 101127199A CN A2007101487378 A CNA2007101487378 A CN A2007101487378A CN 200710148737 A CN200710148737 A CN 200710148737A CN 101127199 A CN101127199 A CN 101127199A
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Abstract
The utility model provides an associated grid driver and method, and an LCD (liquid crystal display) outputting zero overlapping scanning signals, comprising multilevel grid drive circuits, wherein, the grid drive circuits are coupled with each other, and used to output a plurality of scanning signals; each level of grid drive circuit comprises a shift register and an obstruction circuit, wherein, the shift register is used to generate a scanning signal in light of a frequency signal and the scanning signals of a previous grid driver circuit; the obstruction circuit is coupled with the shift register, and used to block the scanning signals output by the shift register for a pre-arranged period, so as to generate a plurality of scanning signals without overlapping time sequences between the adjacent levels of the grid drive circuits, and improve image qualities of the LCD (liquid crystal display).
Description
Technical field
The present invention relates to a kind of LCD and driving circuit, particularly relate to an obstruct circuit and a sequential regulate and control method in the gate drivers (GateDriver).
Background technology
Fig. 4 A is the structure calcspar of conventional liquid crystal.Please refer to Fig. 4 A, LCD 400 comprises gate drivers 410, a data driver (Data Driver) 420, picture element matrix (PixelMatrix) 430 and time schedule controller (Timing Controller) 440.Picture element matrix 430 comprises many gate lines 104, many data lines 106, a plurality of pixel 107 and pixel capacitances 108.Gate line 104 and data line 106 all are arranged on the substrate 402 and are interlaced with each other.Each pixel 107 comprises a thin film transistor (TFT) 109, is coupled to gate line 104 and data line 106.Pixel capacitance 108 is coupled to thin film transistor (TFT) 109.Gate drivers 410 comprise first shift register 411, second shift register 411 ... and N shift register 411, wherein N is the positive integer greater than 1.(shift register 411 of 1≤p≤N) is according to frequency signal (Clock) CLK of time schedule controller 440 outputs and opens beginning signal (StartPulse) STP p, or sweep signal S (p-1) (wherein p＞1), and output scanning signal Sp, with the p row pixel of on-pixel matrix 430, and then receive the pixel data signal that data driver 420 is exported.
Please be simultaneously with reference to Fig. 4 B and Fig. 4 C, Fig. 4 B is the wiring diagram that couples of the gate drivers 410 of conventional liquid crystal among Fig. 4 A and picture element matrix 430 (TFT with the PMOS framework is an example); Fig. 4 C is the sequential chart of the output scanning signal S of gate drivers institute (p-1), Sp and S (p+1) and frequency signal CLK among Fig. 4 B.Frequency signal CLK according to time schedule controller 440 outputs, when entering sequential period T (p-1), sweep signal S (p-1) will be low voltage level Low (～VSS) output, and the no signal output still of p shift register 411 and (p+1) shift register 411, also be sweep signal Sp and S (p+1) all be high-voltage level High (～VDD); When sequential period T p, p shift register 411 will and be in the sweep signal S (p-1) of low voltage level Low according to frequency signal CLK, and the sweep signal Sp of output LOW voltage level Low, at this moment, then (p-1) shift register 411 will be in closed condition; By that analogy, when sequential period T (p+1), (p+1) shift register 411 is also with the sweep signal S (p+1) of the same manner output LOW voltage level Low.
Yet, because the component characteristic of switch module in the shift register, when accepting the triggering of frequency signal CLK, to cause the sweep signal S (p-1) of (p-1) shift register 411 outputs when Tp finishes, still to be in low voltage level Low, be that the rising frequency edges of sweep signal S (p-1) is not when being triggered as yet, the sweep signal Sp of p shift register 411 outputs promptly is converted into low voltage level Low by high-voltage level High, and make (p-1) row will be in opening simultaneously a certain period with p row gate line, so with deterioration picture display quality.
The situation that the gate terminal sweep signal that is taken place on same sequential for adjacent two-stage shift register is interfered, United States Patent (USP) No. 5818412, No. 5963188 and No. 6670943, and U.S. Patent Application Publication No. 20050156859,20060248421 and 20070030239 etc., the method for improving is also proposed; Its signal that is next to shift register that utilizes gate drivers to comprise intercepts circuit, the rising frequency edges that reaches (p-1) level early triggers than the droping frequency edge of p level, to provide non-overlapping sweep signal to the corresponding gate line of adjacent two-stage shift register.Yet, the signal that aforementioned patent and patented claim open file are disclosed intercepts comparatively complexity of circuit design, the logic switching circuit that all comprises a plurality of complexity, therefore can't use single driving component of planting of NMOS or PMOS framework to put into practice this design, simplify manufacture process and cost-effective target and be difficult to reach.
Summary of the invention
The invention provides a kind of gate drivers of exportable superposition-free scanning signal, comprise the multistage gate driver circuit that couples mutually, in order to export a plurality of sweep signals.Each grade gate driver circuit comprises that a shift register and intercepts circuit, wherein shift register produces the one scan signal in order to the sweep signal according to a frequency signal and previous stage gate driver circuit, intercept circuit and be coupled to shift register, reach a scheduled time slot in order to the sweep signal that intercepts shift register output.
In gate drivers, this obstruct circuit comprises the controlled switch assembly of a N type passage and a P type passage.
In gate drivers, this obstruct circuit comprises: the controlled switch assembly of one the one N type passage, comprise an one source pole and a drain electrode, the source electrode of the controlled switch assembly of a N type passage is coupled to this gate line, and the drain electrode of the controlled switch assembly of a N type passage is coupled to this shift register; And the controlled switch assembly of one the 2nd N type passage, comprising a drain electrode and an one source pole, the drain electrode of the controlled switch assembly of the 2nd N type passage is coupled to this gate line, and the source electrode of the controlled switch assembly of the 2nd N type passage is coupled to a low level voltage source.
In gate drivers, this obstruct circuit comprises: the controlled switch assembly of one the one P type passage, comprise a drain electrode and an one source pole, the drain electrode of the controlled switch assembly of a P type passage is coupled to this gate line, and the source electrode of the controlled switch assembly of a P type passage is coupled to this shift register; And the controlled switch assembly of one the 2nd P type passage, comprising a drain electrode and an one source pole, the drain electrode of the controlled switch assembly of the 2nd P type passage is coupled to this gate line, and the source electrode of the controlled switch assembly of the 2nd P type passage is coupled to a high level voltage source.
The present invention provides a kind of LCD in addition, and it comprises substrate, picture element matrix, gate drivers and data driver.Picture element matrix comprises many gate lines, many data lines vertical with gate line, a plurality of pixel and pixel capacitances.Aforementioned gate line and data line all are arranged on the substrate; Each pixel comprises a thin film transistor (TFT), is coupled to a data line and a gate line; Pixel capacitance is coupled to thin film transistor (TFT).Data driver is in order to export a plurality of pixel datas to data line.Gate drivers comprises the multistage gate driver circuit that couples mutually, in order to export a plurality of sweep signals, each grade gate driver circuit comprises: a shift register produces the one scan signal in order to the sweep signal according to a frequency signal and previous stage gate driver circuit; And one intercept circuit, is coupled to this shift register, reaches a scheduled time slot in order to the sweep signal that intercepts this shift register output.
In this LCD, this obstruct circuit comprises the controlled switch assembly of a N type passage and a P type passage.
In this LCD, this obstruct circuit comprises: the controlled switch assembly of one the one N type passage, comprise an one source pole and a drain electrode, the source electrode of the controlled switch assembly of the one N type passage is coupled to this gate line, and the drain electrode of the controlled switch assembly of a N type passage is coupled to this shift register; And the controlled switch assembly of one the 2nd N type passage, comprising a drain electrode and an one source pole, the drain electrode of the controlled switch assembly of the 2nd N type passage is coupled to this gate line, and the source electrode of the controlled switch assembly of the 2nd N type passage is coupled to a low level voltage source.
In this LCD, this obstruct circuit comprises: the controlled switch assembly of one the one P type passage, comprise a drain electrode and an one source pole, the drain electrode of the controlled switch assembly of the one P type passage is coupled to this gate line, and the source electrode of the controlled switch assembly of a P type passage is coupled to this shift register; And the controlled switch assembly of one the 2nd P type passage, comprising a drain electrode and an one source pole, the drain electrode of the controlled switch assembly of the 2nd P type passage is coupled to this gate line, and the source electrode of the controlled switch assembly of the 2nd P type passage is coupled to a high level voltage source.
In this LCD, this data driver produces control, and this intercepts the control signal of circuit.
The present invention provides a kind of method of LCD outputting superposition-free scanning signal in addition, comprising: a shift register produces the one scan signal according to the sweep signal of a frequency signal and previous stage gate driver circuit; And when the sweep signal of this shift register output reaches a working hour, use control signal control to be coupled to the obstruct circuit of this shift register, the sweep signal that intercepts this shift register output reaches a scheduled time slot.
In said method, this obstruct circuit comprises the controlled switch assembly of one the one P type passage, its source electrode is coupled to this shift register, and the controlled switch assembly of one the 2nd N type passage, its source electrode is coupled to a low level voltage source, wherein this control signal is mutual same phase, synchronously controls the controlled switch assembly of this N type passage and this P type passage, reaches this scheduled time slot with the sweep signal that intercepts this shift register output.
In said method, this obstruct circuit comprises the controlled switch assembly of one the one N type passage, its drain electrode is coupled to this shift register, and the controlled switch assembly of one the 2nd P type passage, its source electrode is coupled to a high level voltage source, wherein this control signal is mutual same phase, synchronously controls the controlled switch assembly of this N type passage and this P type passage, reaches this scheduled time slot with the sweep signal that intercepts this shift register output.
In said method, this obstruct circuit comprises the controlled switch assembly of one the one N type passage, its drain electrode is coupled to this shift register, and the controlled switch assembly of one the 2nd N type passage, its source electrode is coupled to a low level voltage source, wherein this control signal is mutual opposite phase, synchronously controls the controlled switch assembly of this two N type passage, reaches this scheduled time slot with the sweep signal that intercepts this shift register output.
In said method, this obstruct circuit comprises the controlled switch assembly of one the one P type passage, its source electrode is coupled to this shift register, and the controlled switch assembly of one the 2nd P type passage, its source electrode is coupled to a high level voltage source, wherein this control signal is mutual opposite phase, synchronously controls the controlled switch assembly of this two P type passage, reaches this scheduled time slot with the sweep signal that intercepts this shift register output.
Thereby according to the LCD and the method thereof of outputting superposition-free scanning signal of the present invention, can reach and simplify manufacture process and cost-effective target, improve the image quality of LCD.
Description of drawings
Figure 1A is the structure calcspar of first embodiment of LCD of the present invention.
Figure 1B is first line block diagram of (p-1), p and (p+1) stage drive circuit among Figure 1A.
Fig. 1 C is first sequential chart of (p-1) level among Figure 1A, p level and (p+1) level gate driver circuit.
Fig. 1 D is second line block diagram of (p-1), p and (p+1) stage drive circuit among Figure 1A.
Fig. 1 E is second sequential chart of (p-1) level among Figure 1A, p level and (p+1) level gate driver circuit.
Fig. 1 F for having (p-1) level of controlled switch assemblies and the tertiary circuit calcspars of p level gate driver circuit organized more among Figure 1A.
Fig. 1 G for having (p-1) level of controlled switch assemblies and the 4th line block diagrams of p level gate driver circuit organized more among Figure 1A.
Fig. 2 A is the line block diagram of the second embodiment of the invention be made up of the NMOS framework.
Fig. 2 B is the sequential chart of the second embodiment of the invention be made up of the NMOS framework.
Fig. 3 A is the line block diagram of the third embodiment of the invention be made up of the PMOS framework.
Fig. 3 B is the sequential chart of the third embodiment of the invention be made up of the PMOS framework.
Fig. 4 A is a conventional liquid crystal structure calcspar.
Fig. 4 B is the wiring diagram that couples of the gate drivers of conventional liquid crystal among Fig. 4 A and picture element matrix (TFT with the PMOS framework is an example).
Fig. 4 C is the sequential chart of the output scanning signal S of gate drivers institute (p-1), Sp and S (p+1) and frequency signal CLK among Fig. 4 B.
And each description of reference numerals in the above-mentioned accompanying drawing is as follows:
100,400: LCD
102: substrate
104: gate line
106: data line
107: pixel
108: pixel capacitance
109: thin film transistor (TFT)
110,410: gate drivers
111: gate driver circuit
112,113,114,115,212,312: intercept circuit
116,117,118,119,200,202,300,302: the controlled switch assembly
120,420: data driver
130,430: picture element matrix
140,440: time schedule controller
411: shift register
Embodiment
Please refer to Figure 1A, it is the structure calcspar of first embodiment of LCD of the present invention.LCD 100 comprises a substrate 102, a picture element matrix 130, a gate drivers 110, a data driver 120 and time schedule controller 140, wherein LCD 100 periphery circuit design are mainly the CMOS framework, and the thin film transistor (TFT) of picture element matrix 130 is the NMOS framework and is arranged on the substrate 102.Picture element matrix 130 comprises many gate lines 104, many data lines 106, a plurality of pixel 107 and pixel capacitances 108.Gate line 104 all is arranged on the substrate 102 with data line 106, and both are interlaced with each other.Each pixel 107 comprises a thin film transistor (TFT) 109, is coupled to a gate line 104 and a data line 106.Pixel capacitance 108 is coupled to thin film transistor (TFT) 109.Gate drivers 110 comprises the N level gate driver circuit 111 that couples mutually, respectively in order to export N sweep signal S1～Sn in regular turn, with each row pixel of on-pixel matrix 130, and then receive pixel data signal D1～Dm that data driver 120 is exported, wherein m, n are the positive integer greater than 1.P (gate driver circuit 111 of 1≤p≤N) is according to the frequency signal CLK of time schedule controller 140 outputs and open beginning signal STP, or sweep signal S (p-1) (wherein p＞1), and output scanning signal Sp, with the p row pixel of on-pixel matrix 130.
Please refer to Figure 1B and Fig. 1 C, it is first line block diagram and the sequential chart of (p-1) level among Figure 1A, p level and (p+1) level gate driver circuit 111, the obstruct circuit 112 of wherein arbitrary gate driver circuit 111 comprises the controlled switch assembly 116 of one the one P type passage, its source electrode is coupled to shift register 411, and the controlled switch assembly 118 of one the 2nd N type passage, its source electrode is coupled to a low level voltage source (VSS), and drain electrode is coupled to the drain electrode of the controlled switch assembly 116 of a P type passage.Frequency signal CLK according to time schedule controller 140 outputs, when sequential period T (p-1) finishes, (p-1) level gate driver circuit 111 is with output HIGH voltage level High (～VDD) sweep signal S (p-1), and sequential period T p finish for the previous period in, two control signal OE1 and OE2 all be set at simultaneously High (～VDD), so that the rising frequency edges of p level than (p-1) level the droping frequency edge be triggered evening, just utilize the controlled switch assembly 116 of the obstruct circuit 112 of gate drivers 110,118 and control signal OE1, the frequency regulation and control of OE2, when the sweep signal of shift register 411 outputs reaches a working hour, use control signal OE1, OE2 control is coupled to the obstruct circuit 112 of shift register 411, the sweep signal that intercepts shift register 411 outputs reaches a scheduled time slot, to provide non-overlapping sweep signal to adjacent 111 corresponding gate lines of two-stage gate driver circuit.By that analogy, when sequential period T (p+1) and T (p+2), (p+1) gate driver circuit 111 is also with the same manner output scanning signal S (p+1).
Please refer to Fig. 1 D and Fig. 1 E, it is second line block diagram and the sequential chart of (p-1) level among Figure 1A, p level and (p+1) level gate driver circuit, wherein the obstruct circuit 113 of arbitrary gate driver circuit comprises the controlled switch assembly 117 of one the one N type passage, its drain electrode is coupled to shift register 411, and the controlled switch assembly 119 of one the 2nd P type passage, its source electrode is coupled to a high level voltage source (VDD), and drain electrode is coupled to the source electrode of the controlled switch assembly 117 of a N type passage.Frequency signal CLK according to time schedule controller 140 outputs, when sequential period T (p-1) finishes, (p-1) level gate driver circuit 111 is with output HIGH voltage level High (～VDD) sweep signal S (p-1), and sequential period T p finish for the previous period in, two control signal XOE1 and XOE2 all be set at simultaneously Low (～VSS), so that the rising frequency edges of p level than (p-1) level the droping frequency edge be triggered evening, just utilize the controlled switch assembly 117 of the obstruct circuit 113 of gate drivers 110,119 and control signal XOE1, the frequency regulation and control of XOE2, when the sweep signal of shift register 411 outputs reaches a working hour, use control signal XOE1, XOE2 control is coupled to the obstruct circuit 113 of shift register 411, the sweep signal that intercepts shift register 411 outputs reaches a scheduled time slot, to provide non-overlapping sweep signal to adjacent 111 corresponding gate lines of two-stage gate driver circuit.By that analogy, when sequential period T (p+1) and T (p+2), (p+1) gate driver circuit 111 is also with the same manner output scanning signal S (p+1).
Please refer to Fig. 1 F, it for having (p-1) level of controlled switch assemblies and the tertiary circuit calcspars of p level gate driver circuit organized more among Figure 1A, wherein the obstruct circuit 114 of arbitrary gate driver circuit comprises the controlled switch assembly of one the one P type passage, its source electrode is coupled to this shift register, and the controlled switch assembly of one the 2nd N type passage, its source electrode is coupled to a low level voltage source (VSS).In view of thin-film transistor component design in response to various different breadth length ratios (Aspect Ratio), obstruct circuit of the present invention also can utilize a plurality of synchronous control signal (OEa1...OEaM, OEb1...OEbN), and corresponding a plurality of controlled switch assemblies, when the sweep signal of shift register 411 outputs reaches a working hour, use control signal (OEa1...OEaM, OEb1...OEbN) control is coupled to the obstruct circuit 114 of shift register 411, the sweep signal that intercepts shift register 411 outputs reaches a scheduled time slot, and provides non-overlapping sweep signal to the corresponding gate line of adjacent two-stage gate driver circuit.
Please refer to Fig. 1 G, it for having (p-1) level of controlled switch elements and the 4th line block diagrams of p level gate driver circuit organized more among Figure 1A, wherein the obstruct circuit 115 of arbitrary gate driver circuit comprises the controlled switch assembly of one the one N type passage, its drain electrode is coupled to shift register 411, and the controlled switch assembly of one the 2nd P type passage, its source electrode is coupled to a high level voltage source (VDD).In view of thin-film transistor component design in response to various different breadth length ratios (Aspect Ratio), obstruct circuit of the present invention also can utilize a plurality of synchronous control signal (XOEa1...XOEaM, XOEb1...XOEbN), and corresponding a plurality of controlled switch assemblies, when the sweep signal of shift register 411 outputs reaches a working hour, use control signal (XOEa1...XOEaM, XOEb1...XOEbN) control is coupled to the obstruct circuit 115 of shift register 411, the sweep signal that intercepts shift register 115 outputs reaches a scheduled time slot, and provides non-overlapping sweep signal to the corresponding gate line of adjacent two-stage gate driver circuit.
Please refer to Fig. 2 A and Fig. 2 B, its second embodiment of the invention for being formed by the NMOS framework, disclose the line block diagram and the sequential chart of (p-1) level, p level and (p+1) level gate driver circuit, wherein intercept circuit 212 and comprise the controlled switch assembly 200 of one the one N type passage, its drain electrode is coupled to shift register 411, and the controlled switch assembly 202 of one the 2nd N type passage, its source electrode is coupled to a low level voltage source, and drain electrode is coupled to the source electrode of the controlled switch assembly 200 of a N type passage; Wherein control signal OE and XOE are mutual opposite phase, synchronously control the controlled switch assembly 200,202 of two N type passages, reach a scheduled time slot with the sweep signal that intercepts shift register 411 outputs.Be mainly with the different place of first embodiment: the LCD periphery circuit design of second embodiment and the thin film transistor (TFT) of picture element matrix 230 are the NMOS framework, and both are the NMOS framework, for saving the best approach of manufacturing step and cost; In addition, the design uses a plurality of control signals that have an inverted phases at least to come synchro control to intercept circuit 212, to provide non-overlapping sweep signal to the adjacent corresponding gate line of two-stage gate driver circuit.
When sequential period T (p-1) when closing to an end, (～VDD) sweep signal S (p-1) before with output HIGH voltage level High for (p-1) level gate driver circuit, control signal OE and inverted phases XOE thereof also be set at respectively High (～VDD) and Low (～VSS), and keep this state when sequential period T p+1 begins, and the rising frequency edges that makes the p level is triggered than the droping frequency edge of (p-1) level evening, just utilize the controlled switch assembly 200 that intercepts circuit 212,202 and control signal OE, the frequency regulation and control of XOE are to provide non-overlapping sweep signal to the corresponding gate line of adjacent two-stage gate driver circuit.By that analogy, when sequential period T (p+1) and T (p+2), (p+1) gate driver circuit is also exported the sweep signal S (p+1) of high level with the same manner.
Please refer to Fig. 3 A and Fig. 3 B, its third embodiment of the invention for being formed by the PMOS framework, disclose the line block diagram and the sequential chart of (p-1) level, p level and (p+1) level gate driver circuit, wherein intercept circuit 312 and comprise the controlled switch assembly 300 of one the one P type passage, its source electrode is coupled to shift register 411, and the controlled switch assembly 302 of one the 2nd P type passage, its source electrode is coupled to a high level voltage source (VDD), and drain electrode is coupled to the drain electrode of the controlled switch assembly 300 of a P type passage.With the difference of first embodiment, being mainly the panel periphery circuit design of second embodiment and the thin film transistor (TFT) of picture element matrix 330 is the PMOS framework, and both are the PMOS framework, for saving the best approach of manufacturing step and cost; In addition, the design uses a plurality of control signal OE, the XOE that have an inverted phases at least to control and intercepts circuit 312, to provide non-overlapping sweep signal to the adjacent corresponding gate line of two-stage gate driver circuit.
When sequential period T p closes to an end, p level gate driver circuit is with output LOW voltage level Low (before～VSS) the sweep signal Sp, control signal OE and inverted phases XOE thereof also will be respectively and synchronously be set at H (～VDD) and L (～VSS), and keep this state when sequential period T p begins, and make the droping frequency edge of p level be triggered evening than the rising frequency edges of (p-1) level, to provide non-overlapping sweep signal to the corresponding gate line of adjacent two-stage gate driver circuit.By that analogy, when sequential period T (p+1) and T (p+2), (p+1) gate driver circuit is also with the sweep signal S (p+1) of the same manner output low level.
So, LCD and method thereof according to outputting superposition-free scanning signal of the present invention, the design of gate drivers is suitable for and is CMOS, NMOS and PMOS framework, all can provide non-overlapping sweep signal to the corresponding gate line of adjacent level gate driver circuit, and improve the image quality of LCD.
By the above detailed description of preferred embodiments, clear more description feature of the present invention and spirit, and be not to come the scope of protection of present invention is limited with the above-mentioned preferred embodiment that is disclosed.On the contrary, its objective is that hope can contain being arranged in the present invention's claim scope required for protection of various changes and tool equality.The foregoing description only is illustrative principle of the present invention and effect thereof, but not is used to limit the present invention.Any those skilled in the art all can be under the situation of know-why of the present invention and spirit, and the foregoing description is made amendment and changed, and all should belong to covering scope of the present invention.
Claims (14)
1. the gate drivers of an exportable superposition-free scanning signal comprises the multistage gate driver circuit that couples mutually, and in order to export a plurality of sweep signals, each grade gate driver circuit comprises:
One shift register produces the one scan signal in order to the sweep signal according to a frequency signal and previous stage gate driver circuit; And
One intercepts circuit, is coupled to this shift register, reaches a scheduled time slot in order to the sweep signal that intercepts this shift register output.
2. gate drivers as claimed in claim 1, wherein this obstruct circuit comprises the controlled switch assembly of a N type passage and a P type passage.
3. gate drivers as claimed in claim 1, wherein this obstruct circuit comprises:
The controlled switch assembly of one the one N type passage comprises an one source pole and a drain electrode, and the source electrode of the controlled switch assembly of a N type passage is coupled to this gate line, and the drain electrode of the controlled switch assembly of a N type passage is coupled to this shift register; And
The controlled switch assembly of one the 2nd N type passage comprises a drain electrode and an one source pole, and the drain electrode of the controlled switch assembly of the 2nd N type passage is coupled to this gate line, and the source electrode of the controlled switch assembly of the 2nd N type passage is coupled to a low level voltage source.
4. gate drivers as claimed in claim 1, wherein this obstruct circuit comprises:
The controlled switch assembly of one the one P type passage comprises a drain electrode and an one source pole, and the drain electrode of the controlled switch assembly of a P type passage is coupled to this gate line, and the source electrode of the controlled switch assembly of a P type passage is coupled to this shift register; And
The controlled switch assembly of one the 2nd P type passage comprises a drain electrode and an one source pole, and the drain electrode of the controlled switch assembly of the 2nd P type passage is coupled to this gate line, and the source electrode of the controlled switch assembly of the 2nd P type passage is coupled to a high level voltage source.
5. the LCD of an exportable superposition-free scanning signal comprises:
One substrate;
Many gate lines are arranged on this substrate;
Many data lines are arranged on this substrate, and staggered with described many gate lines;
A plurality of pixels, each pixel comprise a thin film transistor (TFT) and a pixel capacitance, and this thin film transistor (TFT) is coupled to a data line and a gate line, and this pixel capacitance is coupled to this thin film transistor (TFT);
One data driver is in order to export a plurality of pixel datas to described many data lines; And
One gate drivers comprises the multistage gate driver circuit that couples mutually, and in order to export a plurality of sweep signals, each grade gate driver circuit comprises:
One shift register produces the one scan signal in order to the sweep signal according to a frequency signal and previous stage gate driver circuit; And
One intercepts circuit, is coupled to this shift register, reaches a scheduled time slot in order to the sweep signal that intercepts this shift register output.
6. LCD as claimed in claim 5, wherein this obstruct circuit comprises the controlled switch assembly of a N type passage and a P type passage.
7. LCD as claimed in claim 5, wherein this obstruct circuit comprises:
The controlled switch assembly of one the one N type passage comprises an one source pole and a drain electrode, and the source electrode of the controlled switch assembly of a N type passage is coupled to this gate line, and the drain electrode of the controlled switch assembly of a N type passage is coupled to this shift register; And
The controlled switch assembly of one the 2nd N type passage comprises a drain electrode and an one source pole, and the drain electrode of the controlled switch assembly of the 2nd N type passage is coupled to this gate line, and the source electrode of the controlled switch assembly of the 2nd N type passage is coupled to a low level voltage source.
8. LCD as claimed in claim 5, wherein this obstruct circuit comprises:
The controlled switch assembly of one the one P type passage comprises a drain electrode and an one source pole, and the drain electrode of the controlled switch assembly of a P type passage is coupled to this gate line, and the source electrode of the controlled switch assembly of a P type passage is coupled to this shift register; And
The controlled switch assembly of one the 2nd P type passage comprises a drain electrode and an one source pole, and the drain electrode of the controlled switch assembly of the 2nd P type passage is coupled to this gate line, and the source electrode of the controlled switch assembly of the 2nd P type passage is coupled to a high level voltage source.
9. LCD as claimed in claim 5, wherein this data driver produces the control signal of this obstruct circuit of control.
10. the method for a LCD outputting superposition-free scanning signal comprises:
One shift register produces the one scan signal according to the sweep signal of a frequency signal and previous stage gate driver circuit; And
When the sweep signal of this shift register output reaches a working hour, use control signal control to be coupled to the obstruct circuit of this shift register, the sweep signal that intercepts this shift register output reaches a scheduled time slot.
11. method as claimed in claim 10, wherein this obstruct circuit comprises the controlled switch assembly of one the one P type passage, its source electrode is coupled to this shift register, and the controlled switch assembly of one the 2nd N type passage, its source electrode is coupled to a low level voltage source, wherein this control signal is mutual same phase, synchronously controls the controlled switch assembly of this N type passage and this P type passage, reaches this scheduled time slot with the sweep signal that intercepts this shift register output.
12. method as claimed in claim 10, wherein this obstruct circuit comprises the controlled switch assembly of one the one N type passage, its drain electrode is coupled to this shift register, and the controlled switch assembly of one the 2nd P type passage, its source electrode is coupled to a high level voltage source, wherein this control signal is mutual same phase, synchronously controls the controlled switch assembly of this N type passage and this P type passage, reaches this scheduled time slot with the sweep signal that intercepts this shift register output.
13. method as claimed in claim 10, wherein this obstruct circuit comprises the controlled switch assembly of one the one N type passage, its drain electrode is coupled to this shift register, and the controlled switch assembly of one the 2nd N type passage, its source electrode is coupled to a low level voltage source, wherein this control signal is mutual opposite phase, synchronously controls the controlled switch assembly of this two N type passage, reaches this scheduled time slot with the sweep signal that intercepts this shift register output.
14. method as claimed in claim 10, wherein this obstruct circuit comprises the controlled switch assembly of one the one P type passage, its source electrode is coupled to this shift register, and the controlled switch assembly of one the 2nd P type passage, its source electrode is coupled to a high level voltage source, wherein this control signal is mutual opposite phase, synchronously controls the controlled switch assembly of this two P type passage, reaches this scheduled time slot with the sweep signal that intercepts this shift register output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101487378A CN101127199B (en) | 2007-09-06 | 2007-09-06 | Gate driver for outputting superposition-free scanning signal, liquid crystal display and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101487378A CN101127199B (en) | 2007-09-06 | 2007-09-06 | Gate driver for outputting superposition-free scanning signal, liquid crystal display and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101127199A true CN101127199A (en) | 2008-02-20 |
| CN101127199B CN101127199B (en) | 2010-06-02 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2007101487378A Active CN101127199B (en) | 2007-09-06 | 2007-09-06 | Gate driver for outputting superposition-free scanning signal, liquid crystal display and method |
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| CN102034452A (en) * | 2010-04-09 | 2011-04-27 | 友达光电股份有限公司 | Gate drive circuit, liquid crystal display and method for modifying scanning signal |
| CN101685606B (en) * | 2008-09-26 | 2012-02-08 | 联合聚晶股份有限公司 | Method for regulating and generating scanning signal as well as driving device applying same |
| CN101599254B (en) * | 2009-05-05 | 2012-12-19 | 华映光电股份有限公司 | Adjustment device and adjustment method for output enable signal |
| WO2014082329A1 (en) * | 2012-11-30 | 2014-06-05 | 深圳市华星光电技术有限公司 | Drive method and drive circuit for liquid crystal panel and liquid crystal display device |
| US9111502B2 (en) | 2012-11-30 | 2015-08-18 | Shenzhen China Star Optoelectronics Technology Co., Ltd | Driving circuit and LCD device having data monitoring module |
| CN105204249A (en) * | 2015-10-29 | 2015-12-30 | 深圳市华星光电技术有限公司 | Scanning drive circuit on array substrate and array substrate |
| WO2016119467A1 (en) * | 2015-01-26 | 2016-08-04 | 京东方科技集团股份有限公司 | Drive circuit and drive method therefor, and display device |
| CN106782387A (en) * | 2016-12-30 | 2017-05-31 | 深圳市华星光电技术有限公司 | GOA drive circuits |
| WO2018028195A1 (en) * | 2016-08-12 | 2018-02-15 | Boe Technology Group Co., Ltd. | Shift register, gate integrated driving circuit, and display apparatus |
| WO2021189492A1 (en) * | 2020-03-27 | 2021-09-30 | 京东方科技集团股份有限公司 | Gate drive circuit, driving method therefor, and display panel |
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| CN100385478C (en) * | 2003-12-27 | 2008-04-30 | Lg.菲利浦Lcd株式会社 | Driving circuit including shift register and flat panel display device using the same |
| CN100587770C (en) * | 2005-04-26 | 2010-02-03 | 佳能株式会社 | Scanning circuit, scanning device, image display apparatus and television apparatus |
| KR100645700B1 (en) * | 2005-04-28 | 2006-11-14 | 삼성에스디아이 주식회사 | Scan Driver and Driving Method of Light Emitting Display Using the Same |
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| CN101685606B (en) * | 2008-09-26 | 2012-02-08 | 联合聚晶股份有限公司 | Method for regulating and generating scanning signal as well as driving device applying same |
| CN101599254B (en) * | 2009-05-05 | 2012-12-19 | 华映光电股份有限公司 | Adjustment device and adjustment method for output enable signal |
| CN102034452A (en) * | 2010-04-09 | 2011-04-27 | 友达光电股份有限公司 | Gate drive circuit, liquid crystal display and method for modifying scanning signal |
| WO2014082329A1 (en) * | 2012-11-30 | 2014-06-05 | 深圳市华星光电技术有限公司 | Drive method and drive circuit for liquid crystal panel and liquid crystal display device |
| US9111502B2 (en) | 2012-11-30 | 2015-08-18 | Shenzhen China Star Optoelectronics Technology Co., Ltd | Driving circuit and LCD device having data monitoring module |
| WO2016119467A1 (en) * | 2015-01-26 | 2016-08-04 | 京东方科技集团股份有限公司 | Drive circuit and drive method therefor, and display device |
| CN105204249A (en) * | 2015-10-29 | 2015-12-30 | 深圳市华星光电技术有限公司 | Scanning drive circuit on array substrate and array substrate |
| CN105204249B (en) * | 2015-10-29 | 2018-07-17 | 深圳市华星光电技术有限公司 | Scan drive circuit in array substrate and array substrate |
| WO2018028195A1 (en) * | 2016-08-12 | 2018-02-15 | Boe Technology Group Co., Ltd. | Shift register, gate integrated driving circuit, and display apparatus |
| US10614768B2 (en) | 2016-08-12 | 2020-04-07 | Boe Technology Group Co., Ltd. | Shift register, gate integrated driving circuit, and display apparatus |
| CN106782387A (en) * | 2016-12-30 | 2017-05-31 | 深圳市华星光电技术有限公司 | GOA drive circuits |
| CN106782387B (en) * | 2016-12-30 | 2019-11-05 | 深圳市华星光电技术有限公司 | GOA driving circuit |
| WO2021189492A1 (en) * | 2020-03-27 | 2021-09-30 | 京东方科技集团股份有限公司 | Gate drive circuit, driving method therefor, and display panel |
| CN113906492A (en) * | 2020-03-27 | 2022-01-07 | 京东方科技集团股份有限公司 | Gate drive circuit, drive method thereof and display panel |
| CN113906492B (en) * | 2020-03-27 | 2023-04-28 | 京东方科技集团股份有限公司 | Gate driving circuit, driving method thereof and display panel |
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