CN106773426A - Array base palte test circuit and preparation method thereof, display panel - Google Patents
Array base palte test circuit and preparation method thereof, display panel Download PDFInfo
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- CN106773426A CN106773426A CN201710121073.XA CN201710121073A CN106773426A CN 106773426 A CN106773426 A CN 106773426A CN 201710121073 A CN201710121073 A CN 201710121073A CN 106773426 A CN106773426 A CN 106773426A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
- G01R31/2825—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere in household appliances or professional audio/video equipment
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136254—Checking; Testing
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/136295—Materials; Compositions; Manufacture processes
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- General Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Geometry (AREA)
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The present invention discloses a kind of array base palte test circuit and preparation method thereof, display panel.Array base palte test circuit is arranged on substrate, substrate includes at least two display units, at least two display unit includes first and second display unit, first and second display unit includes array test electrode district and tests electrode district into box, being corresponded with the array test electrode of the second display unit into box test electrode for first display unit is electrically connected, with by the first display unit the output that electrode district drives display signal is tested into box, the generation for reduce coupling, leaking electricity and wound problem, so as to reach the purpose of lifting display panel production yield.
Description
Technical field
It is more particularly to a kind of array base palte test circuit and preparation method thereof, aobvious the present invention relates to display technology field
Show panel.
Background technology
LTPS (Low temperature Poly Silicon, low temperature polycrystalline silicon) TFT LCD (Thin Film
Transistor Liquid Crystal Display, Thin Film Transistor-LCD) obtained on mobile phone in recent years extensively
Using the advantage of its circuit integrated characteristic high and low cost has absolute advantage in the application of small-medium size display panel.
LTPS TFT LCD have the advantages that high-resolution, reaction speed be fast, high brightness, high aperture, by by peripheral drive circuit
Make on the glass substrate simultaneously, reach the cost of target, save space and the driving chip of system combination.
Array process in LTPS TFT LCD is that uniform sequential arrangement forms one on one piece of very big glass substrate
Individual array circuit, the glass substrate by array test project and it is up to standard after, by subsequently into the cut length quilt of box processing procedure
The display unit of a collection of small pieces is cut into, each display unit has an independent array circuit, for controlling final finished
The display of LCD.
LTPS TFT LCDs are wherein in a kind of array line structure design, for single display unit (such as
Shown in Fig. 1 and Fig. 2), (it is referred to as array base palte to test by several longitudinal metal cablings through the viewing area left and right sides
Cabling), the array test circuit coherent signal being located above viewing area is connected to being surveyed into box below viewing area
In examination circuit, the output of longitudinal display signal is driven to borrow into the part circuit of box test circuit, so as to complete array
Test event.This several transverse metal cabling perpendicular friendships all the time of the array base palte test cablings and viewing area edge of longitudinal direction
Wrong position relationship, in into box test event, this position relationship staggeredly makes horizontal display signal be subject to coupling influence,
Cause the display difference of the display panel left and right sides；Other intervening portion it can also happen that electric leakage, or even can produce wound etc. it is different
Chang Wenti, makes the yield of display panel be affected.
The content of the invention
The present invention solves the technical problem of a kind of array base palte test circuit of offer and its method, display panel,
Avoid array base palte from testing cabling and produced with the metal routing at viewing area edge to interlock, reduce and couple, leak electricity and wound problem
Generation, so as to reach lifting display panel production yield purpose.
In order to solve the above technical problems, one aspect of the present invention is：A kind of array base palte test electricity is provided
Road, the array base palte test circuit is arranged on substrate, and the substrate includes at least two display units, described at least two
Display unit includes the first display unit and the second display unit, and described first and second display unit includes array test electricity
Polar region and into box test electrode district, the array test electrode district include some array test electrodes, it is described into box test electrode
Area includes some into box test electrode, the array that electrode and second display unit are tested into box of first display unit
Test electrode corresponds electrical connection, and the defeated of display signal is driven to test electrode district into box by first display unit
Go out.
In order to solve the above technical problems, another technical solution used in the present invention is：A kind of display panel is provided, it is described
Display panel includes array base palte test circuit, and the array base palte test circuit is arranged on substrate, and the substrate is included extremely
Few two display units, at least two display unit includes the first display unit and the second display unit, described first and
Second display unit includes array test electrode district and tests electrode district into box, and the array test electrode district includes some battle arrays
Row test electrode, it is described into box test electrode district include it is some into box test electrode, first display unit into box test
The array test electrode of electrode and second display unit is corresponded and electrically connected, with by first display unit into
Box test electrode district drives the output of display signal.
In order to solve the above technical problems, another technical solution used in the present invention is：A kind of array base palte test is provided
The preparation method of circuit, methods described includes：
One substrate is provided；
At least two display units are set on the substrate, and at least two display unit includes the first display unit
And second display unit；
Array test electrode district is respectively provided with described first and second display unit and electrode district, the battle array is tested into box
Row test electrode district includes some array test electrodes, described to test electrode into box including some into box test electrode district；And
By first display unit into box test electrode and second display unit array test electrode one by one
Correspondence electrical connection, the output that electrode district drives display signal is tested with by first display unit into box.
The beneficial effects of the invention are as follows：It is different from the situation of prior art, the array base palte test circuit of the invention
Shown by the way that the first display unit at least two display unit is electrically connected into described second into box test electrode
Show that cellular array tests electrode, to avoid longitudinal array test cabling from being produced with the transverse metal cabling at viewing area edge
Position relationship staggeredly, the output that electrode controls display signal is tested with this by first display unit into box, so that
Complete to the described first aobvious cellular array test event, the generation for reduce coupling, leaking electricity and wound problem, so as to reach lifting
The purpose of display panel production yield.
Brief description of the drawings
Fig. 1 is a structural representation for display unit of prior art；
Fig. 2 is the structural representation of the array base palte test circuit of prior art；
Fig. 3 is the structural representation of the first embodiment of array base palte test circuit of the invention；
Fig. 4 is the structural representation of the second embodiment of array base palte test circuit of the invention；
Fig. 5 is the structural representation of the 3rd embodiment of array base palte test circuit of the invention；
Fig. 6 is the structural representation of display panel of the invention；
Fig. 7 is the schematic flow sheet of the preparation method of array base palte test circuit of the invention.
Specific embodiment
Fig. 1 and Fig. 2 is referred to, is the structural representation of the array base palte test circuit of display unit in the prior art.Fig. 1
In be located at each display unit viewing area above some array test electrodes, such as four array test electrodes 1 pass through respectively
It is connected respectively under the viewing area of same display unit by the longitudinal metal cabling 3 through the viewing area left and right sides
Side four into box test electrode 2, this four wires 3 (i.e. array base palte test cabling) all with the transverse direction at viewing area edge
Metal routing (not shown) it is perpendicular staggeredly position relationship, in into box test event, it is this staggeredly position relationship make
Horizontal display signal is subject to coupling influence, causes the display difference of the display panel left and right sides, and intervening portion is likely in addition
Leak electricity, or even can produce and the abnormal problem such as wound, the yield of display panel is affected.
Fig. 3 is refer to, is the structural representation of the first embodiment of array base palte test circuit of the invention.The array
Substrate test circuit is arranged on substrate 20, and the substrate 20 includes at least two display units 10, at least two display
Unit 10 includes the first display unit and the second display unit, and described first and second display unit includes array test electrode
Area 11 and into box test electrode district 12, the area of array test electrode 11 include some array test electrodes 111, it is described into box survey
Examination electrode district 12 include it is some into box test electrode 121, first display unit tests electrode 121 and described second into box
The array test electrode 111 of display unit corresponds electrical connection, and electrode is tested into box with by first display unit
Area 12 drives the output of display signal.
Specifically, first display unit and second display unit include viewing area 13, and the array is surveyed
Examination electrode district 11 is located at the top of the viewing area 13, described to be located under the viewing area 13 into box test electrode district 12
Side.Wherein, in all embodiments of the invention, viewing area 13 refers to area of array base palte when into box on the inside of fluid sealant
Domain, this region is used for filling liquid crystal with display image.The other elements and function of first and second display unit with it is existing
Technology is identical, will not be repeated here.
Wherein, in all embodiments of the invention, the array test electrode district 11 includes four array test electrodes
111, it is described to include that four are tested electrode 121, in other embodiments, the array test electrode into box into box electrode district 12
111 and into box test electrode 121 quantity can be configured as needed.
In the present embodiment, second display unit is located at the underface of first display unit.
By the array test electrode that electrode 121 and second display unit are tested into box of first display unit
The 111 array test cablings 14 for corresponding electrical connection are fully shut off in processing procedure is cut, to ensure array test project just
On the premise of often completing, longitudinal array test cabling 14 display signal horizontal for viewing area edge is not only avoided that
Influence (including electric leakage and the problem that wound of intervening portion), and can effectively eliminate array test in follow-up cutting process
The damage by static electricity that region produces is for the influence that is caused into box test event.
The array base palte test circuit is by by the first display unit at least two display unit into box
Test electrode is electrically connected to the array test electrode of second display unit, to avoid longitudinal array test cabling and show
Show that the transverse metal cabling of edges of regions produces position relationship staggeredly, tested into box by first display unit with this
The output of electrode control display signal, so as to complete to the described first aobvious cellular array test event, reduce coupling, electric leakage and
The generation of problem is wound, so as to reach the purpose of lifting display panel production yield.
Fig. 4 is referred to, is the structural representation of the second embodiment of array base palte test circuit of the invention.The array
It is in place of the second embodiment of substrate test circuit and the difference of above-mentioned first embodiment：Second display unit is located at institute
State the right side of the first display unit.
In other embodiments, second display unit may be alternatively located at the left side of first display unit, its connection
Relation and operation principle are same as the previously described embodiments, will not be repeated here.
Fig. 5 is referred to, is the structural representation of the 3rd embodiment of array base palte test circuit of the invention.The array
It is in place of the 3rd embodiment of substrate test circuit and the difference of above-mentioned first or second embodiments：Second display unit
Positioned at the lower left of first display unit.
In other embodiments, second display unit may be alternatively located at the lower right of first display unit, its company
Connect relation and operation principle is same as the previously described embodiments, will not be repeated here.
In other embodiments electricity is tested according to array test electrode 111 in described first and second display unit and into box
The difference of the set location of pole 121, the particular location of first and second display unit will change, specifically with the first display
Unit into box test electrode 121 be electrically connected to second display unit array test electrode 111 cabling for it is most short,
And subsequently first display unit can be electrically connected to described second into box test electrode 121 into box test event
The cabling of the array test electrode 111 of display unit is cut to most preferably, thus first and second display unit specific position
The relation of putting is not limited to embodiments of the invention, and those skilled in the art can according to specific needs be changed and be set.
Fig. 6 is referred to, is a kind of structural representation of display panel of the invention.The display panel includes foregoing array
Substrate test circuit, other devices and function in the display panel are same with the device and function phase of existing display panel,
This is repeated no more.
Fig. 7 is referred to, is the schematic flow sheet of the preparation method of array base palte test circuit of the invention.Methods described bag
Include：
Step S1：One substrate 20 is provided.
Specifically, the substrate 20 is glass substrate, the base of other devices and function and prior art on the substrate
Plate is identical, will not be repeated here.
Step S2：At least two display units 10 are set on the substrate 20, and at least two display unit includes
First display unit and the second display unit.
Step S3：Array test electrode district 11 is respectively provided with described first and second display unit and electrode is tested into box
Area 12, the array test electrode district 11 includes some array test electrodes 111, described to test electrode district 12 including some into box
Electrode 121 is tested into box.
Specifically, second display unit is located at the underface of first display unit, or second display
Unit is located at the left side or right side of first display unit；Or second display unit is located at first display unit
Lower left or lower right.
Wherein, array test electrode district 11 is respectively provided with described first and second display unit and electrode district is tested into box
12 the step of is specially first display unit and second display unit includes viewing area 13, the array test
Electrode district 11 is located at the top of the viewing area 13, described to be located under the viewing area 13 into box test electrode district 12
Side.
Step S4：By being surveyed with the array of second display unit into box test electrode 121 for first display unit
Examination electrode 111 corresponds electrical connection, and display signal is driven to test electrode district 12 into box by first display unit
Output.
The array base palte test circuit is by by the first display unit at least two display unit into box
Test electrode is electrically connected to the array test electrode of second display unit, to avoid longitudinal array test cabling and show
Show that the transverse metal cabling of edges of regions produces position relationship staggeredly, tested into box by first display unit with this
The output of electrode control display signal, so as to complete to the described first aobvious cellular array test event, reduce coupling, electric leakage and
The generation of problem is wound, so as to reach the purpose of lifting display panel production yield.
Embodiments of the present invention are the foregoing is only, the scope of the claims of the invention is not thereby limited, it is every using this
Equivalent structure or equivalent flow conversion that description of the invention and accompanying drawing content are made, or directly or indirectly it is used in other correlations
Technical field, is included within the scope of the present invention.
Claims (10)
1. a kind of array base palte test circuit, it is characterised in that the array base palte test circuit is arranged on substrate, the base
Plate includes at least two display units, and at least two display unit includes the first display unit and the second display unit, institute
Stating first and second display unit includes array test electrode district and tests electrode district, the array test electrode district bag into box
Some array test electrodes are included, it is described to test electrode into box including some into box test electrode district, first display unit
Corresponded with the array test electrode of second display unit into box test electrode and electrically connected, shown with by described first
The output that display signal is driven into box test electrode district of unit.
2. array base palte test circuit according to claim 1, it is characterised in that second display unit is located at described
The underface of the first display unit.
3. array base palte test circuit according to claim 1, it is characterised in that second display unit is located at described
The left side or right side of the first display unit, or second display unit are located at the lower left or the right side of first display unit
Lower section.
4. array base palte test circuit according to claim 1, it is characterised in that first display unit and described
Two display units include viewing area, and the array test electrode district is located at the top of the viewing area, described to be surveyed into box
Examination electrode district is located at the lower section of the viewing area.
5. a kind of display panel, it is characterised in that the display panel includes array base palte test circuit, the array base palte is surveyed
Examination circuit is arranged on substrate, and the substrate includes at least two display units, and at least two display unit includes first
Display unit and the second display unit, described first and second display unit include array test electrode district and test electricity into box
Polar region, the array test electrode district includes some array test electrodes, described to be surveyed into box including some into box test electrode district
Examination electrode, the array test electrode one-to-one corresponding that electrode and second display unit are tested into box of first display unit
Electrical connection, the output that electrode district drives display signal is tested with by first display unit into box.
6. display panel according to claim 5, it is characterised in that second display unit is located at the described first display
The underface of unit, or second display unit is located at the left side or right side of first display unit, or described the
Two display units are located at the lower left or lower right of first display unit.
7. display panel according to claim 1, it is characterised in that first display unit and second display are single
Unit includes viewing area, and the array test electrode district is located at the top of the viewing area, described to test electrode district into box
Positioned at the lower section of the viewing area.
8. a kind of preparation method of array base palte test circuit, it is characterised in that methods described includes：
One substrate is provided；
At least two display units are set on the substrate, and at least two display unit includes the first display unit and the
Two display units；
Array test electrode district is respectively provided with described first and second display unit and electrode district is tested into box, the array is surveyed
Examination electrode district includes some array test electrodes, described to test electrode into box including some into box test electrode district；And
By being corresponded with the array test electrode of second display unit into box test electrode for first display unit
Electrical connection, the output that electrode district drives display signal is tested with by first display unit into box.
9. the preparation method of array base palte test circuit according to claim 8, it is characterised in that described in the substrate
At least two display units of upper setting, at least two display unit includes the first display unit and the second display unit bag
Include：Second display unit is located at the underface of first display unit, or second display unit positioned at described
The left side or right side of the first display unit, or second display unit be located at first display unit lower left or
Lower right.
10. the preparation method of array base palte test circuit according to claim 8, it is characterised in that described described
One and second array test electrode district is respectively provided with display unit and is included into box test electrode district：First display unit and
Second display unit includes viewing area, and the array test electrode district is located at the top of the viewing area, described
The lower section of the viewing area is located at into box test electrode district.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710121073.XA CN106773426A (en) | 2017-03-02 | 2017-03-02 | Array base palte test circuit and preparation method thereof, display panel |
| PCT/CN2017/079441 WO2018157438A1 (en) | 2017-03-02 | 2017-04-05 | Array substrate test circuit and manufacturing method therefor, and display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710121073.XA CN106773426A (en) | 2017-03-02 | 2017-03-02 | Array base palte test circuit and preparation method thereof, display panel |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106773426A true CN106773426A (en) | 2017-05-31 |
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ID=58960650
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710121073.XA Pending CN106773426A (en) | 2017-03-02 | 2017-03-02 | Array base palte test circuit and preparation method thereof, display panel |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN106773426A (en) |
| WO (1) | WO2018157438A1 (en) |
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| CN107065364A (en) * | 2017-06-15 | 2017-08-18 | 厦门天马微电子有限公司 | Array base palte, display panel, display device, big plate and method of testing |
| CN109212799A (en) * | 2018-10-26 | 2019-01-15 | 深圳市华星光电技术有限公司 | The peripheral circuit structure and motherboard of liquid crystal display of liquid crystal display panel |
| CN109633302A (en) * | 2018-12-05 | 2019-04-16 | 武汉华星光电半导体显示技术有限公司 | Testing impedance structure |
| CN110444117A (en) * | 2019-07-24 | 2019-11-12 | 昆山维信诺科技有限公司 | The preparation method of package substrate and display panel |
| CN110716357A (en) * | 2018-07-13 | 2020-01-21 | 株式会社日本显示器 | Display device and substrate of display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107065364A (en) * | 2017-06-15 | 2017-08-18 | 厦门天马微电子有限公司 | Array base palte, display panel, display device, big plate and method of testing |
| CN110716357A (en) * | 2018-07-13 | 2020-01-21 | 株式会社日本显示器 | Display device and substrate of display device |
| CN110716357B (en) * | 2018-07-13 | 2022-04-12 | 株式会社日本显示器 | Display device and substrate of display device |
| CN109212799A (en) * | 2018-10-26 | 2019-01-15 | 深圳市华星光电技术有限公司 | The peripheral circuit structure and motherboard of liquid crystal display of liquid crystal display panel |
| CN109212799B (en) * | 2018-10-26 | 2021-10-29 | Tcl华星光电技术有限公司 | Peripheral circuit structure of liquid crystal panel and liquid crystal display mother board |
| CN109633302A (en) * | 2018-12-05 | 2019-04-16 | 武汉华星光电半导体显示技术有限公司 | Testing impedance structure |
| CN110444117A (en) * | 2019-07-24 | 2019-11-12 | 昆山维信诺科技有限公司 | The preparation method of package substrate and display panel |
| CN110444117B (en) * | 2019-07-24 | 2021-09-28 | 苏州清越光电科技股份有限公司 | Preparation method of packaging substrate and display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2018157438A1 (en) | 2018-09-07 |
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