CN103681692A - Array substrate, production method thereof and display device - Google Patents
Array substrate, production method thereof and display device Download PDFInfo
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- CN103681692A CN103681692A CN201310632256.XA CN201310632256A CN103681692A CN 103681692 A CN103681692 A CN 103681692A CN 201310632256 A CN201310632256 A CN 201310632256A CN 103681692 A CN103681692 A CN 103681692A
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Abstract
The invention provides an array substrate, a production method thereof and a display device, relates to the technical field of display, and solves the problem that voltage fluctuation of data wires on existing array substrates affects display of pixel electrodes. The array substrate comprises a substrate body, a grid metal layer, a source-drain metal layer, a transparent conducting layer and first conducting patterns. The grid metal layer, the source-drain metal layer and the transparent conducting layer are arranged on the substrate body. The grid metal layer comprises common electric wires. The source-drain metal layer comprises data wires. The transparent conducting layer comprises pixel electrodes. The first conducting patterns correspond to the data wires in terms of position, and form vertical electric fields with the data wires at least on portions, corresponding to the pixel electrodes, of the data wires.
Description
Technical field
The present invention relates to Display Technique field, relate in particular to a kind of array base palte and preparation method thereof, display unit.
Background technology
Existing display panels, comprise array base palte, color membrane substrates and be arranged on array base palte and color membrane substrates between liquid crystal.
To be applied to TN (Twist Nematic, twisted-nematic) array base palte in type liquid crystal display is example, array base palte comprises: many grid lines and many data wires, a plurality of pixel cells of the crisscross formation of grid line and data wire wherein, as shown in Figure 1, described in each, pixel cell correspondence is provided with a thin-film transistor 3 and a pixel electrode 5, wherein, thin-film transistor 3 comprises grid 31, source electrode 32 and drain electrode 33, grid 31 is connected with grid line 1, source electrode 32 is connected with data wire 2, and drain electrode 33 is connected with pixel electrode 5.And described array base palte is also provided with public electrode wire 4, it is electrically connected to the public electrode being arranged on color membrane substrates, and common electric voltage is provided.
Shown in Fig. 1, its operation principle is, when grid line 1 provides sweep signal to grid 31, data wire 2 provides data-signal to source electrode 32, corresponding drain electrode 33 conductings, to pixel electrode transmission voltage signal, the public electrode of pixel electrode and color membrane substrates forms electric field, to drive liquid crystal to realize, shows.But when grid stops providing sweep signal, due to liquid crystal capacitance and storage capacitance, as shown in Figure 2, pixel electrode 5 can keep certain voltage to next cycle, now data wire 2 can continue to provide data-signal to the pixel cell of other row, signal on data wire 2 constantly converts, and then can affect the demonstration of pixel electrode 5, affects display effect.
Summary of the invention
Embodiments of the invention provide a kind of array base palte and preparation method thereof, display unit, and the change in voltage of the data wire on described array base palte can not affect the voltage of pixel electrode, has promoted display effect.
For achieving the above object, embodiments of the invention adopt following technical scheme:
The embodiment of the present invention provides a kind of array base palte, comprising: metal level and transparency conducting layer are leaked in grid metal level, source that substrate is arranged on described substrate; Wherein, described grid metal level comprises: public electrode wire, and described source is leaked metal level and is comprised: data wire; Transparency conducting layer comprises: pixel electrode; Wherein, array base palte also comprises: the first conductive pattern, described the first conductive pattern is corresponding with linear position data, and at least in the part of data wire respective pixel electrode, forms vertical electric field with data wire.
Optionally, described the first conductive pattern and data wire form vertical electric field.
Optionally, described the first conductive pattern is electrically connected to public electrode wire.
Optionally, described grid metal level also comprises: the first conductive pattern, and described the first conductive pattern directly contacts electrical connection with public electrode wire.
Optionally, described transparency conducting layer also comprises: the first conductive pattern, and described the first conductive pattern is electrically connected to by via hole with described public electrode wire.
Optionally, described array base palte also comprises between grid metal level and the first conductive pattern: gate insulation layer and passivation layer, and the dielectric constant of described gate insulation layer and/or described passivation layer is below 7.
Optionally, the width of described the first conductive pattern is greater than the width of described data wire.
The embodiment of the present invention provides a kind of manufacture method of array base palte, comprising: on substrate, form grid metal level, wherein, described grid metal level comprises: public electrode wire; On substrate, metal level is leaked in formation source, and wherein, described source is leaked metal level and comprised: data wire; On substrate, form transparency conducting layer, wherein, described transparency conducting layer comprises: pixel electrode: also comprise: at least in the corresponding position of substrate and data wire respective pixel electrode, form the first conductive pattern.
Optionally, in the position corresponding with data wire of substrate, form the first conductive pattern.
Optionally, form described grid metal level and specifically comprise formation public electrode wire and the first conductive pattern, and described the first conductive pattern directly contacts electrical connection with public electrode wire.
Optionally, form described transparency conducting layer and comprise: form pixel electrode and the first conductive pattern, and described the first conductive pattern is electrically connected to by via hole with described public electrode wire.
The embodiment of the present invention provides a kind of display unit, comprises arbitrary described array base palte that the embodiment of the present invention provides.
A kind of array base palte that the embodiment of the present invention provides and preparation method thereof, display unit, on described array base palte, be also provided with the first conductive pattern, described the first conductive pattern is corresponding with the position of data wire, and at least the part at data wire respective pixel electrode forms vertical electric field with data wire, data line voltage changes very little on the impact of pixel electrode, reduce the voltage fluctuation of pixel electrode, and then can promote display effect.
Accompanying drawing explanation
Fig. 1 is existing array base palte plan structure schematic diagram;
Fig. 2 is the sectional structure schematic diagram of array base palte shown in Fig. 1;
A kind of array base palte plan structure schematic diagram that Fig. 3 provides for the embodiment of the present invention;
Fig. 4 is the sectional structure schematic diagram of array base palte shown in Fig. 3;
The another kind of array base palte plan structure schematic diagram that Fig. 5 provides for the embodiment of the present invention;
The manufacture method schematic diagram of a kind of array base palte that Fig. 6 provides for the embodiment of the present invention.
Reference numeral:
1) grid line; 2) data wire; 3) thin-film transistor; 31) grid; 32) source electrode; 33) drain electrode; 4) public electrode wire; 5) pixel electrode; 6) the first conductive pattern; 7) passivation layer; 8) gate insulation layer; 10) transparency carrier.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.
In all embodiment of the present invention, need to illustrate the definition of " layer " and " pattern ", and between relation.Wherein, institute's " layer " is by the thin film of a composition technique formation, and it can comprise at least one film " pattern ".
The embodiment of the present invention provides a kind of array base palte, comprising: metal level and transparency conducting layer are leaked in substrate, the grid metal level, the source that are arranged on described substrate; Wherein, described grid metal level comprises: public electrode wire, and described source is leaked metal level and is comprised: data wire; Transparency conducting layer comprises: pixel electrode; Wherein, array base palte also comprises: the first conductive pattern, described the first conductive pattern is corresponding with linear position data, and at least in the part of data wire respective pixel electrode, forms vertical electric field with data wire.
It should be noted that, described grid metal level can also comprise grid line and grid, and metal level is leaked in described source can also comprise source class and drain electrode.Described the first conductive pattern is for forming vertical electric field with data wire, and described the first conductive pattern insulate in vertical direction.And described the first conductive pattern can be arranged on described source leak metal level above, also can be arranged on described source leak metal level below.Described the first conductive pattern at least forms vertical electric field in the part of data wire respective pixel electrode with data wire, and the first conductive pattern can be as shown in Figure 3, and only the part at data wire respective pixel electrode forms vertical electric field with the first conductive pattern.Described substrate can be transparency carrier, can also be on transparency carrier, to be provided with other films or layer structure etc., the embodiment of the present invention be take described substrate and is elaborated as transparency carrier as example.
Concrete, as shown in Figure 3, Figure 4, described array base palte comprises transparency carrier 10 and is arranged on described transparency carrier 10 grid metal level, source leakage metal level and transparency conducting layer above; Wherein said grid metal level comprises: grid line 1, grid 31 and public electrode wire 4; Source is leaked metal level and is comprised: data wire 2, source electrode 32 and drain electrode 33; Transparency conducting layer comprises: pixel electrode 5; And array base palte also comprises the first conductive pattern 6, as shown in Figure 4, described the first conductive pattern 6 is arranged on the top of described data wire 2, at part and the data wire 2 formation vertical electric fields of data wire 2 respective pixel electrodes.
It should be noted that, array base palte also comprises other films or layer structure, for example, at the last layer of grid metal level, is also provided with gate insulation layer, in source, leaks between metal level and transparency conducting layer passivation layer etc. can also be set.The embodiment of the present invention is only enumerated the film relevant to inventive point of the present invention or layer structure.
A kind of array base palte that the embodiment of the present invention provides, on described array base palte, be also provided with the first conductive pattern, described the first conductive pattern is corresponding with the position of data wire, and at least the part at data wire respective pixel electrode forms vertical electric field with data wire, data line voltage changes very little on the impact of pixel electrode, reduce the voltage fluctuation of pixel electrode, and then can promote display effect.
Optionally, described the first conductive pattern and data wire form vertical electric field.Be the many rows of described the first conductive pattern formation corresponding to data wire, corresponding first conductive pattern of each data wire.Can further reduce like this impact of whole piece data line voltage fluctuation on pixel electrode.
Optionally, described the first conductive pattern is electrically connected to public electrode wire.Concrete, as shown in Figure 4, the first conductive pattern 6 is electrically connected to public electrode wire 4, thereby provides voltage and data wire 2 to form vertical electric field by public electrode wire 4.
Optionally, described grid metal level also comprises: the first conductive pattern, and described the first conductive pattern directly contacts electrical connection with public electrode wire.Concrete, as shown in Figure 5, described grid metal level comprises the first conductive pattern 6, and described the first conductive pattern 6 directly contacts electrical connection with described public electrode 4.
Optionally, described transparency conducting layer also comprises: the first conductive pattern, and described the first conductive pattern is electrically connected to by via hole with described public electrode wire.Concrete, as shown in Figure 4, described transparency conducting layer comprises: pixel electrode 5 and the first conductive pattern 6, and described the first conductive pattern 6 and described pixel electrode 5 insulation, the first conductive pattern 6 is electrically connected to public electrode wire 4 by via hole.
Optionally, described array base palte also comprises between grid metal level and the first conductive pattern: gate insulation layer and passivation layer, and the dielectric constant of described gate insulation layer and/or described passivation layer is below 7.Concrete, as shown in Figure 4, between grid metal level and the first conductive pattern 6, also comprising gate insulation layer 8 and passivation layer 9, described the first conductive pattern 6 is electrically connected to public electrode wire 4 by the via hole on gate insulation layer 8 and passivation layer 7 with described public electrode wire 4.And the dielectric constant of gate insulation layer and/or described passivation layer is below 7, and the dielectric constant of gate insulation layer and/or described passivation layer comprises 7, and the electric field that further like this first conductive pattern and data wire form is less, less on the impact of pixel electrode.
Optionally, the thickness of described gate insulation layer is
as shown in Figure 4, the thickness of described gate insulation layer is
by increasing the thickness of gate insulation layer, increased the distance of data wire and pixel electrode, can further reduce the impact of data line voltage on pixel electrode.
Optionally, the thickness of described passivation layer is
as shown in Figure 4, the thickness of described passivation layer is
by increasing the thickness of passivation layer, increased the distance of data wire and pixel electrode, can further reduce the impact of data line voltage on pixel electrode.
Optionally, the width of described the first conductive pattern is greater than the width of described data wire.As shown in Figure 4, Figure 5, the first conductive pattern forming like this wraps up described data wire, to mask its signal intensity, pixel electrode is affected.
In all embodiment of the present invention, need to illustrate the definition of " layer " and " pattern ", and between relation.Wherein, " layer " refers to the thin film that utilizes a certain material to utilize deposition or other techniques to produce on substrate.Can also be to adopt composition technique to make it comprise at least one film " pattern " to this " film ".In the embodiment of the present invention " on ", the sequencing of D score during with manufacturing array substrate be as the criterion, and for example, at upper pattern, refers to relatively the pattern in rear formation, under pattern refer to the pattern relatively formerly forming.
The embodiment of the present invention provides a kind of manufacture method of array base palte, as shown in Figure 6, comprising:
Step 101, on substrate, form grid metal level.
Wherein, described substrate can be transparency carrier, and the described grid metal level that forms on substrate forms grid metal level on transparency carrier.Wherein, described grid metal level comprises: public electrode wire.Can also comprise grid line and grid etc.
Step 102, on substrate, metal level is leaked in formation source.
Wherein, described substrate is formed with the transparency carrier of grid metal level, described on substrate formation source leak metal level on described grid metal level formation source leak metal level.Wherein, described source leakage metal level comprises: data wire.Can also comprise source class and drain electrode etc.
Step 103, on substrate, form transparency conducting layer.
Wherein, described substrate is formed with the transparency carrier of grid metal level and source leakage metal level, and the described transparency conducting layer that forms on substrate forms transparency conducting layer on metal level is leaked in source.Wherein, described transparency conducting layer comprises: pixel electrode.
Step 104, at least in the corresponding position of substrate and data wire respective pixel electrode, form the first conductive pattern.
Be that described the first conductive pattern at least forms vertical electric field in the part of data wire respective pixel electrode with data wire.And the width that preferably makes described the first conductive pattern is greater than the width of described data wire.As shown in Figure 4, Figure 5, the first conductive pattern forming like this wraps up described data wire, to mask its signal intensity, pixel electrode is affected.
It should be noted that, by above-mentioned steps, form described the first conductive pattern, described the first conductive pattern can be to form by a composition technique.
In addition, described the first conductive pattern also can form by other steps.And described the first conductive pattern is for forming vertical electric field with data wire, and described the first conductive pattern insulate in vertical direction.Described the first conductive pattern can be to form before metal level is leaked in making source, described the first conductive pattern be arranged on described source leak metal level below; Can also be to make described the first conductive pattern after metal level is leaked in making source, described the first conductive pattern be arranged on described source leakage metal level above.Described the first conductive pattern at least forms vertical electric field in the part of data wire respective pixel electrode with data wire, and the first conductive pattern can be as shown in Figure 3, and only the part at data wire respective pixel electrode forms the first conductive pattern.
It should be noted that, array base palte can also comprise other films or layer structure, and the manufacture method of array base palte is also not limited only to above-mentioned steps.The embodiment of the present invention only be take the making step relevant to inventive point of the present invention and the manufacture method of the first conductive pattern is described as example.
Optionally, in the position corresponding with data wire of substrate, form the first conductive pattern.Be that described the first conductive pattern and data wire form vertical electric field.The many rows of such the first conductive pattern formation corresponding to data wire, can further reduce the impact of whole piece data line voltage fluctuation on pixel electrode.
Optionally, form described grid metal level and specifically comprise formation public electrode wire and the first conductive pattern, and described the first conductive pattern directly contacts electrical connection with public electrode wire.Without above-mentioned steps 104, when forming described grid metal level, step 101 forms described the first conductive pattern in the position of grid metal level respective data lines.And described grid metal level comprises the first conductive pattern and public electrode wire, can be so that described the first conductive pattern directly contact electrical connection with public electrode wire, thus by the first conductive pattern described in public electrode alignment, provide voltage.
Optionally, form described transparency conducting layer and comprise: form pixel electrode and the first conductive pattern, and described the first conductive pattern is electrically connected to by via hole with described public electrode wire.Without above-mentioned steps 104, when forming described transparency conducting layer, step 103 in the position of transparency conducting layer respective data lines, forms described the first conductive pattern, and described transparency conducting layer comprises that the first conductive pattern need to be electrically connected to the public electrode wire of grid metal level by via hole being set at source leakage metal level, provides voltage by the first conductive pattern described in public electrode alignment.
The embodiment of the present invention provides a kind of display unit, comprises arbitrary described array base palte that the embodiment of the present invention provides.Described display unit can be the display devices such as liquid crystal display and any product or the parts with Presentation Function such as TV, digital camera, mobile phone, panel computer that comprise these display devices.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited to this, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; the variation that can expect easily or replacement, within all should being encompassed in protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of described claim.
Claims (12)
1. an array base palte, comprising: metal level and transparency conducting layer are leaked in substrate, the grid metal level, the source that are arranged on described substrate; Wherein, described grid metal level comprises: public electrode wire, and described source is leaked metal level and is comprised: data wire; Transparency conducting layer comprises: pixel electrode; It is characterized in that, array base palte also comprises: the first conductive pattern, described the first conductive pattern is corresponding with linear position data, and at least in the part of data wire respective pixel electrode, forms vertical electric field with data wire.
2. array base palte according to claim 1, is characterized in that, described the first conductive pattern and data wire form vertical electric field.
3. array base palte according to claim 1, is characterized in that, described the first conductive pattern is electrically connected to public electrode wire.
4. array base palte according to claim 3, is characterized in that, described grid metal level also comprises: the first conductive pattern, and described the first conductive pattern directly contacts electrical connection with public electrode wire.
5. array base palte according to claim 3, is characterized in that, described transparency conducting layer also comprises: the first conductive pattern, and described the first conductive pattern is electrically connected to by via hole with described public electrode wire.
6. array base palte according to claim 5, is characterized in that, described array base palte also comprises between grid metal level and the first conductive pattern: gate insulation layer and passivation layer, and the dielectric constant of described gate insulation layer and/or described passivation layer is below 7.
7. according to the array base palte described in claim 1-6 any one, it is characterized in that, the width of described the first conductive pattern is greater than the width of described data wire.
8. a manufacture method for array base palte, comprising: on substrate, form grid metal level, wherein, described grid metal level comprises: public electrode wire; On substrate, metal level is leaked in formation source, and wherein, described source is leaked metal level and comprised: data wire; On substrate, form transparency conducting layer, wherein, described transparency conducting layer comprises: pixel electrode; It is characterized in that, also comprise:
At least in the corresponding position of substrate and data wire respective pixel electrode, form the first conductive pattern.
9. manufacture method according to claim 8, is characterized in that, in the substrate position corresponding with data wire, forms the first conductive pattern.
10. manufacture method according to claim 8, is characterized in that, form described grid metal level and specifically comprise formation public electrode wire and the first conductive pattern, and described the first conductive pattern directly contacts electrical connection with public electrode wire.
11. manufacture methods according to claim 8, is characterized in that, form described transparency conducting layer and comprise: form pixel electrode and the first conductive pattern, and described the first conductive pattern is electrically connected to by via hole with described public electrode wire.
12. 1 kinds of display unit, is characterized in that, comprise the array base palte described in claim 1-7 any one.
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| CN107358900A (en) * | 2017-09-15 | 2017-11-17 | 京东方科技集团股份有限公司 | Test display panel and its driving method and preparation method |
| CN107797321A (en) * | 2015-05-08 | 2018-03-13 | 厦门天马微电子有限公司 | Array base palte, liquid crystal display panel and liquid crystal display device |
| CN108231850A (en) * | 2018-01-03 | 2018-06-29 | 京东方科技集团股份有限公司 | Array substrate and preparation method thereof, display panel |
| CN110187578A (en) * | 2019-06-27 | 2019-08-30 | 京东方科技集团股份有限公司 | Display base plate and preparation method thereof, display device |
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