CN106684038B - 用于4m制程制备tft的光罩及4m制程tft阵列制备方法 - Google Patents
用于4m制程制备tft的光罩及4m制程tft阵列制备方法 Download PDFInfo
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Abstract
本发明提供一种用于4M制程制备TFT的光罩及4M制程TFT阵列制备方法。本发明用于4M制程制备TFT的光罩,其中,在该光罩的TFT版图结构中,邻近TFT图案外缘设有沿TFT图案外缘走向设置的线条图案。本发明还提供了相应的4M制程TFT阵列制备方法,使用本发明的光罩作为第二道光罩制程的光罩。本发明用于4M制程制备TFT的光罩通过改变光罩的边缘曝光实现边缘偏薄的结构,进而使得该结构比较易于等离子体刻蚀,从而减少第二层金属边缘有不定形硅和重掺杂硅残留问题;本发明的4M制程TFT阵列制备方法,将本发明的光罩结合匹配的4M制程,减少第二层金属边缘有不定形硅和重掺杂硅残留问题。
Description
技术领域
本发明涉及液晶显示器领域,尤其涉及一种用于4M制程制备TFT的光罩及4M制程TFT阵列制备方法。
背景技术
液晶显示器(LCD)等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点,而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品,成为显示装置中的主流。
为了降低成本、提高良率,各家显示阵列基板制备和研究厂商和机构不断开发新的制程工艺和技术,其中,4M(四道光罩)代替5M(五道光罩)为业内研发和制程趋势。在4M制程中存在第二层金属边缘有不定形硅和重掺杂硅残留问题,第二层金属即源漏极层金属。该问题影响TFT(薄膜晶体管)光学稳定性和电学性能,开口率,功耗和可靠性,这是由于其采用HTM(半色调光罩)或GTM(灰阶光罩)曝光图形化过程引起。
参见图1,其为现有4M制程中第二道光罩制程的TFT版图结构示意图。版图中的TFT图案1对应于面板上的源漏极区域,在第二道光罩制程中在光刻胶层上曝光显影。
参见图2,其为现有4M制程示意图,显示了现有4M制程中的第二道光罩制程。现有4M制程一般包括:
在第一道光罩制程中,在玻璃基板11上制备栅极层12,并图形化栅极层12;然后制备栅极绝缘层13、有源层、源漏极层16、光刻胶层17,有源层可以包括沟道层14、接触层15;
在第二道光罩制程中,此示例中第二道光罩为灰阶光罩,对光刻胶层17进行曝光显影;第一次湿刻,图形化源漏极层16,形成源漏极区域和有源区域的金属导线结构;第一次干刻,形成有源层岛状结构,也就是图形化沟道层14、接触层15;氧气灰化,降低光刻胶层17厚度以露出沟道区域的源漏极层16;第二次湿刻,图形化源漏极;第二次干刻,刻蚀有源层,也就是刻蚀开沟道层14、接触层15,形成薄膜晶体管结构;
在第三道光罩制程中,制备钝化层,并图案化钝化层;
在第四道光罩制程中,制备透明电极层,并图案化透明电极层。
发明内容
本发明的目的在于提供一种用于4M制程制备TFT的光罩,减少或消除第二层金属边缘有不定形硅和重掺杂硅残留的问题。
本发明的另一目的在于提供一种4M制程TFT阵列制备方法,减少或消除第二层金属边缘有不定形硅和重掺杂硅残留的问题。
为实现上述目的,本发明提供一种用于4M制程制备TFT的光罩,在该光罩的TFT版图结构中,邻近TFT图案外缘设有沿TFT图案外缘走向设置的线条图案。
其中,所述线条图案与TFT图案不交汇,或者所述线条图案与TFT图案交汇。
本发明还提供了一种4M制程TFT阵列制备方法,使用上述的光罩作为第二道光罩制程的光罩。
该4M制程TFT阵列制备方法包括:
步骤10、在第一道光罩制程中,在玻璃基板上制备栅极层,并图形化栅极层;然后制备栅极绝缘层、有源层、源漏极层、光刻胶层;
步骤20、在第二道光罩制程中,对光刻胶层进行曝光显影;第一次湿刻,图形化源漏极层,形成源漏极区域和有源区域的金属导线结构;第一次干刻,形成有源层岛状结构;氧气灰化,降低光刻胶层厚度以露出沟道区域的源漏极层;第二次湿刻,图形化源漏极;第二次干刻,刻蚀有源层,形成薄膜晶体管结构;
步骤30、在第三道光罩制程中,制备钝化层,并图案化钝化层;
步骤40、在第四道光罩制程中,制备透明电极层,并图案化透明电极层。
其中,所述步骤20还包括两次氧气灰化,具体为:在第二道光罩制程中,对光刻胶层进行曝光显影;第一次湿刻,图形化源漏极层,形成源漏极区域和有源区域的金属导线结构;第一次氧气灰化,减少源漏金属层边的有源层拖尾大小;第一次干刻,形成有源层岛状结构;第二次氧气灰化,降低光刻胶层厚度以露出沟道区域的源漏极层;第二次湿刻,图形化源漏极;第三次氧气灰化,减少接触层拖尾;第二次干刻,刻蚀有源层,形成薄膜晶体管结构。
其中,所述TFT阵列为显示区或GOA电路区的TFT阵列。
其中,该第二道光罩为灰阶光罩或半色调光罩。
其中,通过溅射,溶胶凝胶,原子层沉积,蒸发,或者打印方式制备所述栅极层。
其中,所述栅极层的材料为Cu,Cu/Mo,Mo/Cu/Mo,MoNb/Cu/MoNb,Ti/Cu/Ti,Al,Al/Mo,或者Mo/Al/Mo。
其中,通过等离子体化学气相沉积,常压化学气相沉积,或者溅射制备所述栅绝缘层。
其中,所述栅绝缘层的材料为氮化硅,氧化硅,氮氧化硅,氧化铝,或者氧化铪。
其中,所述有源层包括沟道层和接触层。
其中,所述沟道层和接触层通过沉积硅基,溅射金属氧化物半导体层,或者原子层沉积金属氧化物半导体层形成。
其中,所述金属氧化物为IGZO,IZO,或者ITZO。
综上,本发明用于4M制程制备TFT的光罩通过改变光罩的边缘曝光实现边缘偏薄的结构,进而使得该结构比较易于等离子体刻蚀,从而减少第二层金属边缘有不定形硅和重掺杂硅残留问题;本发明的4M制程TFT阵列制备方法,将本发明的光罩结合匹配的4M制程,减少第二层金属边缘有不定形硅和重掺杂硅残留问题。
附图说明
下面结合附图,通过对本发明的具体实施方式详细描述,将使本发明的技术方案及其他有益效果显而易见。
附图中,
图1为现有4M制程中第二道光罩制程的TFT版图结构示意图;
图2为现有4M制程示意图;
图3为本发明4M制程TFT阵列制备方法一较佳实施例的制程示意图;
图4为使用现有光罩的4M制程示意图;
图5为使用本发明用于4M制程制备TFT的光罩的4M制程示意图;
图6和图7,其为本发明用于4M制程制备TFT的光罩第一较佳实施例和第二较佳实施例的TFT版图结构示意图;
图8为使用现有光罩制备的TFT结构照片;
图9为使用本发明用于4M制程制备TFT的光罩的制备的TFT结构照片。
具体实施方式
参见图6和图7,其为本发明用于4M制程制备TFT的光罩第一较佳实施例和第二较佳实施例的TFT版图结构示意图。本发明所提供的用于4M制程制备TFT的光罩,在该光罩的TFT版图结构中,邻近TFT图案61外缘设有沿TFT图案61外缘走向设置的线条图案62,邻近TFT图案71外缘设有沿TFT图案71外缘走向设置的线条图案72。图6中,线条图案62与TFT图案61不交汇,图7中,线条图案72与TFT图案71交汇。在图6和图7对应为两种不同的补值设计方法,以达到更均匀的器件结构设计。
参见图4和图5,图4为使用现有光罩的4M制程示意图,图5为使用本发明用于4M制程制备TFT的光罩的4M制程示意图,比较光刻胶层47和光刻胶层57可知本发明光罩的作用。本发明通过改变光罩的边缘曝光实现边缘偏薄的结构,进而使得该结构比较易于等离子体刻蚀,从而达到减少第二层金属边缘有不定形硅和重掺杂硅残留问题。具体设计涉及改变光罩(Mask)上,薄膜晶体管(TFT)和第二层金属的***金属线宽和金属线距离来到达最佳的消除不定型硅和重掺杂硅残留问题。
参见图8和图9,图8为使用现有光罩制备的TFT结构照片,图9为使用本发明用于4M制程制备TFT的光罩的制备的TFT结构照片。比较图8和图9可知,本发明的光罩可达到提高TFT光学稳定性和电学性能,开口率,可靠性以及减低功耗目的,提高阵列基板的整体性能,可以在原制程基础上成功在沟道区减少重掺杂残留,减少约0.5um,如果结合匹配制程,效果将更加明显。
本发明用于4M制程制备TFT的光罩可以减少或消除第二层金属边缘有不定形硅和重掺杂硅残留问题,将该光罩应用于现有4M制程可以得到相应的4M制程TFT阵列制备方法,可以在原4M制程基础上,不改变制程前提下,成功在第二层金属外侧消除重掺杂残留,而且如果配合新的制程,效果将更加显著。
参见图3,其为本发明4M制程TFT阵列制备方法一较佳实施例的制程示意图,将光罩配合新的制程使用,显示了第二道光罩制程,也就是对现有制程优化的部分。
该较佳实施例的4M制程TFT阵列制备方法主要包括:
步骤10、在第一道光罩制程中,在玻璃基板上制备栅极层,并图形化栅极层;然后制备栅极绝缘层、有源层、源漏极层、光刻胶层;
在第二道光罩制程前的第一道光罩制程中,在玻璃基板21上制备栅极层22,并图形化栅极层22;然后制备栅极绝缘层23、有源层、源漏极层26、光刻胶层27,有源层可以包括沟道层24、接触层25。
步骤20、然后,在应用灰阶光罩的第二道光罩制程中:
应用灰阶光罩,对光刻胶层27进行曝光显影;
第一次湿刻,图形化源漏极层26,形成源漏极区域和有源区域的金属导线结构;
第一次氧气灰化,减少源漏金属层26边的有源层拖尾大小;增加此次氧气灰化主要作用是减少不定形硅残留;
第一次干刻,形成有源层岛状结构,也就是图形化沟道层24、接触层25;
第二次氧气灰化,降低光刻胶层27厚度以露出沟道区域的源漏极层16;
第二次湿刻,图形化源漏极;
第三次氧气灰化,减少接触层拖尾;增加此次氧气灰化主要作用为减少重掺杂硅残留;
第二次干刻,刻蚀有源层,也就是刻蚀开沟道层24、接触层25,形成薄膜晶体管结构。
步骤30、在第三道光罩制程中,制备钝化层,并图案化钝化层。
步骤40、在第四道光罩制程中,制备透明电极层,并图案化透明电极层。
本发明的4M制程TFT阵列制备方法具体涉及一种优化的4M制程工艺背板开发,可用于包括显示区和GOA电路区TFT阵列开发和显示以及电路性能优化。本发明包括栅电极制备,可通过溅射,溶胶凝胶,原子层沉积,蒸发,打印等方式制备Cu,Cu/Mo,Mo/Cu/Mo,MoNb/Cu/MoNb,Ti/Cu/Ti,Al,Al/Mo,Mo/Al/Mo等电极材料,并图形化。本发明包括栅绝缘层制备,具体包括等离子体化学气相沉积,常压化学气相沉积,溅射等制备的氮化硅,氧化硅,氮氧化硅,氧化铝,氧化铪等介质材料。本发明包括沉积硅基,溅射和原子层沉积金属氧化物半导体层,如IGZO,IZO,ITZO等做为沟道层和接触层。第二道光罩可采用灰阶光罩或半色调光罩。步骤30及40中钝化层沉积,接触孔刻蚀,和透明电极如ITO引出等,可采用现有技术,在此不再赘述。
综上,本发明用于4M制程制备TFT的光罩通过改变光罩的边缘曝光实现边缘偏薄的结构,进而使得该结构比较易于等离子体刻蚀,从而减少第二层金属边缘有不定形硅和重掺杂硅残留问题,提高阵列基板的整体性能,可以在原4M制程基础上,不改变制程前提下,成功在第二层金属外侧消除重掺杂残留,如果配合新的工艺,效果将更加显著;本发明的4M制程TFT阵列制备方法,将本发明的光罩结合匹配的4M制程,减少第二层金属边缘有不定形硅和重掺杂硅残留问题。
以上所述,对于本领域的普通技术人员来说,可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形,而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。
Claims (10)
1.一种4M制程TFT阵列制备方法,所述4M指代四道光罩,其特征在于,使用光罩作为第二道光罩制程的光罩;在该光罩的TFT版图结构中,邻近TFT图案外缘设有沿TFT图案外缘走向设置的线条图案;
所述线条图案与TFT图案不交汇,或者所述线条图案与TFT图案交汇;
所述4M制程TFT阵列制备方法包括:
步骤10、在第一道光罩制程中,在玻璃基板上制备栅极层,并图形化栅极层;然后制备栅极绝缘层、有源层、源漏极层、光刻胶层;
步骤20、在第二道光罩制程中,对光刻胶层进行曝光显影;第一次湿刻,图形化源漏极层,形成源漏极区域和有源区域的金属导线结构;第一次干刻,形成有源层岛状结构;氧气灰化,降低光刻胶层厚度以露出沟道区域的源漏极层;第二次湿刻,图形化源漏极;第二次干刻,刻蚀有源层,形成薄膜晶体管结构;
步骤30、在第三道光罩制程中,制备钝化层,并图案化钝化层;
步骤40、在第四道光罩制程中,制备透明电极层,并图案化透明电极层;
所述步骤20还包括两次氧气灰化,具体为:在第二道光罩制程中,对光刻胶层进行曝光显影;第一次湿刻,图形化源漏极层,形成源漏极区域和有源区域的金属导线结构;第一次氧气灰化,减少源漏金属层边的有源层拖尾大小;第一次干刻,形成有源层岛状结构;第二次氧气灰化,降低光刻胶层厚度以露出沟道区域的源漏极层;第二次湿刻,图形化源漏极;第三次氧气灰化,减少接触层拖尾;第二次干刻,刻蚀有源层,形成薄膜晶体管结构。
2.如权利要求1所述的4M制程TFT阵列制备方法,其特征在于,所述TFT阵列为显示区或GOA电路区的TFT阵列。
3.如权利要求1所述的4M制程TFT阵列制备方法,其特征在于,该第二道光罩为灰阶光罩或半色调光罩。
4.如权利要求1所述的4M制程TFT阵列制备方法,其特征在于,通过溅射,溶胶凝胶,原子层沉积,蒸发,或者打印方式制备所述栅极层。
5.如权利要求4所述的4M制程TFT阵列制备方法,其特征在于,所述栅极层的材料为Cu,Cu/Mo,Mo/Cu/Mo,MoNb/Cu/MoNb,Ti/Cu/Ti,Al,Al/Mo,或者Mo/Al/Mo。
6.如权利要求1所述的4M制程TFT阵列制备方法,其特征在于,通过等离子体化学气相沉积,常压化学气相沉积,或者溅射制备所述栅极绝缘层。
7.如权利要求6所述的4M制程TFT阵列制备方法,其特征在于,所述栅极绝缘层的材料为氮化硅,氧化硅,氮氧化硅,氧化铝,或者氧化铪。
8.如权利要求1所述的4M制程TFT阵列制备方法,其特征在于,所述有源层包括沟道层和接触层。
9.如权利要求8所述的4M制程TFT阵列制备方法,其特征在于,所述沟道层和接触层通过沉积硅基,溅射金属氧化物半导体层,或者原子层沉积金属氧化物半导体层形成。
10.如权利要求9所述的4M制程TFT阵列制备方法,其特征在于,所述金属氧化物为IGZO,IZO,或者ITZO。
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CN102148259A (zh) * | 2010-10-12 | 2011-08-10 | 京东方科技集团股份有限公司 | 薄膜晶体管、阵列基板及其制造方法和液晶显示器 |
CN104485420A (zh) * | 2014-12-24 | 2015-04-01 | 京东方科技集团股份有限公司 | 一种有机薄膜晶体管及其制备方法 |
CN105448938A (zh) * | 2016-01-28 | 2016-03-30 | 深圳市华星光电技术有限公司 | 薄膜晶体管基板及其制造方法 |
CN105702742A (zh) * | 2016-02-25 | 2016-06-22 | 深圳市华星光电技术有限公司 | 氧化物薄膜晶体管及其制备方法 |
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CN105448938A (zh) * | 2016-01-28 | 2016-03-30 | 深圳市华星光电技术有限公司 | 薄膜晶体管基板及其制造方法 |
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