CN106649142A - High-speed memorizer with outage renew function - Google Patents
High-speed memorizer with outage renew function Download PDFInfo
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- CN106649142A CN106649142A CN201611102026.2A CN201611102026A CN106649142A CN 106649142 A CN106649142 A CN 106649142A CN 201611102026 A CN201611102026 A CN 201611102026A CN 106649142 A CN106649142 A CN 106649142A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
- G06F12/0868—Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/16—Protection against loss of memory contents
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Abstract
Provided is a high-speed memorizer with outage renew function. The memorizer comprises three memory boards, wherein two memory boards are a back-up to each other, and used for storing data after framing of a collector and ground testing system control instructions relayed through an interface controller, and the third memory board is used for storing external system backup data and the ground testing system control instructions relayed though the interface controller. The high-speed memorizer with the outage renew function conducts double-face read-write operation on two CEs of an NAND Flash chip simultaneously through an FPGA unit, which improves the read-write speed of the memorizer compared with the traditional single CE single-face operation. Besides, after power on reset is completed, the high-speed memorizer with the outage renew function can detect and store the block address written last time, which achieves the outage renew function, renews behind existing data, supports multiple times of outage operation during ground testing and aircraft flight, improves the reliability of the system, and meets the special usage requirements of the system.
Description
Technical field
The present invention relates to a kind of high-speed memory that function is renewed with power-off, belongs to the recovery remote measurement neck of high-speed aircraft
Domain.
Background technology
Telemetry system mainly complete aircraft in flight course various mechanics, calorifics and other ambient parameters and other
Measurement, storage and the off-line data processing work of data.It is one of main remote mode of high-speed aircraft to reclaim remote measurement, is deposited
Reservoir and data processing technique are the nucleus equipments and technology for reclaiming remote measurement.
Telemetry system is typically made up of equipment such as sampler and coder, interface controller and memorizeies on aircraft.Sampler and coder is used for
Analog signalses are acquired, are encoded, framing, and by LVDS interface send framing after data to memorizer.Interface control
Device processed is used to receive external system Backup Data and ground testing system instructs and be transmitted to memorizer, from memorizer downloading data simultaneously
It is transmitted to ground testing system.
Memorizer is typically using Flash chip as core memory chip.It is general to adopt when memorizer carries out storage operation
Single CE single-sided operations, memory rate is relatively low, and demand of the current telemetry system to high-speed data processing cannot have been met.And tradition
When memorizer in telemetry system is stored, instructions control memory start recording is typically adopted, after power-off is powered back up, no
Record can be automatically begun to.And every time from first address start recording, it is impossible to renew from behind data with existing.
The content of the invention
It is an object of the invention to overcome the drawbacks described above of prior art, there is provided a kind of high speed that function is renewed with power-off
Memorizer, using two-sided read-write operation, with power-off function is renewed, and improves the read-write speed and system reliability of memorizer
Property.
What the above-mentioned purpose of the present invention was mainly achieved by following technical solution：One kind renews function with power-off
High-speed memory, including three pieces of memory planes, wherein two pieces of memory planes backup each other, for storing sampler and coder framing after data
With the ground testing system control instruction of interface controller forwarding；3rd piece of memory plane is used for the outer of memory interface controller forwarding
System backup data and ground testing system control instruction；
Three pieces of memory planes composition is identical, including two pieces of NAND Flash chips, FPGA unit, RS422 interface chips,
LVDS receiver, LVDS transmitters and power module；
LVDS receiver on mutually redundant two pieces of memory planes is used to receive the data after sampler and coder framing, and export to
FPGA unit；LVDS receiver on 3rd piece of memory plane is used for the external system Backup Data of receiving interface controller forwarding, and
Export to FPGA unit；
RS422 interface chips be used for receiving interface controller forwarding ground testing system control instruction, and export to
FPGA unit；
FPGA unit receives the data from LVDS receiver, if do not received in the delay time section being pre-designed
Ground testing system control instruction, then simultaneously write the data for receiving in two pieces of NAND Flash chips, otherwise according to ground
Test system control instruction is wiped or down operation two pieces of NAND Flash chips, and the data downloaded are sent out by LVDS
Device is sent to export to ground testing system, the ground testing system control instruction includes erasing, downloads, stops downloading；
Power module is that each device on memory plane is powered.
Also include golden finger on every piece of memory plane, for the pin of two pieces of NAND Flash chips to be drawn, depositing
When storage on board supply module, FPGA unit or LVDS transmitters fail, golden finger can be passed through from outside to NAND Flash cores
Piece is write, is wiped or down operation.
The FPGA unit includes that clock generation module, reset signal generation module, top layer control module, data receiver delay
Storing module, command reception module, Flash control modules and data output control module；
Clock generation module：Clock signal needed for for producing the operation of global and modules, can be according to outside input
Clock selection signal select local crystal oscillator or external clock；
Reset signal generation module：Global reset signal is produced, when the clock signal that clock generation module is produced is effective,
Global reset signal is set to into low level, for by other module resets in addition to itself and clock generation module, keeping one
Global reset signal is set to into high level after the section time；
Top layer control module：After global reset signal is high level, produces configuration and enable signal to except itself is with timely
Other modules beyond clock generation module, reset signal generation module are configured, after the completion of configuration, the control of top layer control module
FPGA unit enters running status；
Data receiver cache module：After the completion of configuration, the data from LVDS receiver are received, and the data for receiving are divided
In not being buffered in two independent FIFO；
Command reception module：For receiving and parsing through the control instruction from RS422 interface chips, export and give Flash controls
Molding block；
Flash control modules：NAND Flash chips are resetted when upper electric, configured and upper electro-detection；If pre-
The control instruction for receiving control module output is not received in the delay time section for first designing, then by the number in two independent FIFO
According to being written in corresponding NAND Flash chips, if received, correspondence NAND is completed according to the control instruction for receiving
The erasing of Flash chip or down operation；Data output control module is given by the data is activation downloaded；
Data output control module：Ping-pong buffer operation carried out to the data that Flash control modules send, it is encoded after
Exported to ground by LVDS transmitters.
The Flash control modules include Flash reset submodules, Flash configuration submodules, upper electro-detection of Flash
Module, Flash erasing submodules, Flash write submodule and Flash reading submodules；
Flash reset submodules：After electrification reset, the reset operation of two pieces of NAND Flash chips is completed so as to can
Normal work；
Flash configures submodule：After the completion of reset, the mode of operation of NAND Flash chips is configured；
The upper electro-detection submodules of Flash：After the completion of configuration, the block ground that the bad block and last time to NAND Flash chips is write
Location is detected, defect block addresses is written in bad block table, in the block address write depositor that last time is write；
Flash wipes submodule：Before writing to NAND Flash chips, if receiving command reception module
The erasing instruction of output, then carry out erasing operation to the position beyond two pieces of NAND Flash chip bad blocks simultaneously, if good block is wiped
Except unsuccessful, then need to be marked as bad block and be written in bad block table；
Flash writes submodule：The block address that reading last time writes from depositor, using double-side operation, by two independences
The data correspondence cached in FIFO is written in the good block that two pieces of NAND Flash chip last time are write after block address；
Flash reads submodule：Using double-side operation, one piece of NAND is selected according to the control instruction of command reception module output
Flash chip, from good block therein data are read, and are sent to data output control module.
It is described adopt double-side operation to one piece of NAND Flash chip carry out the implementation method of write operation for：
(5.1) from FIFO it is data cached in be successively read four groups of data, every group of data are 8KB；
(5.2) first group of data is written to first face of first CE of NAND Flash chips, second group of data is write
Enter the second face to first CE, the 3rd group of data are written to into first face of second CE, the 4th group of data are written to into
Second face of two CE, and four groups of data write simultaneously, the address of write is last time and writes N number of block address after block address
Place, N=2,3 or 4；
(5.3) after the completion of the write of every group of data, in the corresponding free area of this group of data write-in block write labelling is made；
(5.4) said process is repeated, the data cached in FIFO is written in NAND Flash chips.
It is described adopt the implementation method that double-side operation carries out read operation to one piece of NAND Flash chip for：
(6.1) successively from first face of first CE, second face of first CE, first face of second CE, second
One group of data is read in second face of CE, and every group of data are 8KB；
(6.2) repeat step (6.1), complete the reading of data in NAND Flash chips；
(6.3) by the data of reading, according to reading, sequence integration is into data flow and exports.
The realization side that electro-detection module is detected to the block address that NAND Flash chip last time writes on the Flash
Method is：
The upper electro-detection modules of Flash read the labelling of NAND Flash chips free area, and last is write in four CE faces
Enter the block address that the corresponding write block address of labelling is NAND Flash chip last time and writes.
Ground receiver is proceeded as follows to after the data of memorizer：
(8.1) ground detects to receiving data, when L " FF " is detected, then it is assumed that be different power-up twice
The data that not homogeneous is powered up are saved as respectively different data files by data, for the data processing that not homogeneous powers up test
And interpretation；Wherein L<=4*NM；
(8.2) maximum of each telemetry parameter, minima and average every time plus in the time history of electrical testing, are being calculated
Value；
(8.3) interpretation is carried out according to maximum, minima and meansigma methodss criterion that each telemetry parameter pre-sets, works as meter
When maximum, minima and the meansigma methodss for obtaining are satisfied by the telemetry parameter maximum, minima and meansigma methodss criterion, this is distant
Survey parameter interpretation reasonable.
The present invention has the advantages that compared with prior art：
(1), memorizer of the present invention carries out two-sided read-write behaviour simultaneously by FPGA unit to two CE of NAND Flash chips
Make, relative to traditional single CE single-sided operations, improve the read-write speed of memorizer.
(2), electro-detection module after the completion of electrification reset, can be entered to the block address that last time writes on Flash of the present invention
Row detection and preservation, realize power-off and renew function, can renew from behind data with existing, in ground test and aircraft flight
During, support repeatedly to add power operation, system reliability is improve, meet system Special use requirement.
(3), present invention logging software version number in the frame format of memory storage, realizes the online prison of software version
Survey and management design, design, debugging and test process in can real-time monitoring or afterwards interpretation programming in equipment
Software version number, it is to avoid software version programming mistake, improves designed reliability.
(4), ground receiver, can be automatically by the data for receiving according to not homogeneous power-up condition to after the data of memorizer
Multiple files are divided into, are easy to adding electrical test data to carry out interpretation and analysis every time.Remote measurement to receiving every time simultaneously is joined
Number statistics maximum, minima and meansigma methodss, according to criterion automatic interpretation is carried out, and improves efficiency and the intellectuality of data interpretation
Degree.
Description of the drawings
Fig. 1 is that memorizer of the present invention constitutes sketch；
Fig. 2 implements block diagram for memory inside of the present invention；
Fig. 3 is FPGA unit composition frame chart；
Fig. 4 is the two-sided write operation sequential charts of Flash；
Fig. 5 is the two-sided read operation sequential charts of Flash.
Specific embodiment
Below in conjunction with the accompanying drawings further detailed description is done to the present invention with specific embodiment：
As shown in figure 1, the present invention proposes a kind of high-speed memory for renewing function with power-off, including memory plane C1, deposit
Storage plate C2 and memory plane C3, wherein memory plane C1 and memory plane C2 backups each other, for storing sampler and coder framing after data and
The ground testing system control instruction of interface controller forwarding.The external system that memory plane C3 is used for the forwarding of memory interface controller is standby
Number evidence and ground testing system control instruction.
Memory plane C1, memory plane C2 are identical with memory plane C3 compositions, as shown in Fig. 2 including two pieces of NAND Flash cores
Piece, FPGA unit, RS422 interface chips, golden finger, LVDS receiver, LVDS transmitters and power module.
LVDS receiver on mutually redundant C1 and C2 is used to receive the data after sampler and coder framing, and exports to FPGA
Unit, the LVDS receiver on the 3rd piece of memory plane is used for the external system Backup Data of receiving interface controller forwarding, and exports
To FPGA unit.
Data frame format after the sampler and coder framing stored in memorizer is made up of 128 bytes, including 108 words
The memory plane status word of the telemetry parameter of section and 9 bytes.
The status word of memory plane C1 is Sta13, Sta12 and Sta11, the status word of memory plane C2 be Sta23, Sta22 and
The status word of Sta21, memory plane C3 is Sta33, Sta32 and Sta31.Wherein Sta13, Sta23, Sta33 are " CC " interval scale
Memory plane C1, memory plane C2, memory plane C3 are working properly, otherwise, represent operation irregularity.Latter two byte " XXXX " of status word
It is at one's leisure " 00 "+memory plane version number, memory plane version number is a byte；For " 1XXX ", (XXX is in erase process
The block address wiped), erasing is finished and is changed into " 1000 "；It is that " 8XXX " (XXX is the block ground for recording in recording process
Location).
With the instruction CMD also sent including the ground testing system that memorizer is received in time frame format, the main bag of instruction
Include erasing instruction, P1 download instruction, P2 download instruction and stop download instruction.Two pieces of NAND Flash chips in each memory plane
It is designated as P1 and P2.
Also include the software version number of sampler and coder and interface controller in frame format.In device software debugging process, meeting
Multiple software version number are produced, is monitored on-line for ease of software version number and is managed, in frame format of gathering and editing software version is increased
Number, during system test, can be with real-time monitoring, it is also possible to the software version number in interpretation programming to equipment afterwards, it is to avoid software
Edition programming mistake.
The also layout in frame format has frame swynchronization code, such as realizes a whole frame as frame swynchronization code using EB90146F
Frame synchronization, for post-flight data interpretation and process.
One data channel of data and state word multiplex of memorizer, transfer rate is 240Mbps.Pass after electrification reset
Status word is sent, only memory data is just passed down after download instruction is received, other times transmit status word.
The external system Backup Data frame format stored in memorizer is made up of 136 bytes.Wherein the first two byte is frame head,
3rd～6 byte is frame count, is started counting up from 0, after meter is full again from the beginning of 0.7th～134 byte is external system significant figure
According to.Most latter two byte is postamble.
RS422 interface chips be used for receiving interface controller forwarding ground testing system control instruction, and export to
FPGA unit.The instruction of the frame head of one byte and a byte constitutes a coding line, and coding line repeats three times and constitutes one
Control instruction frame.
FPGA unit receives the data from LVDS receiver, if do not received in the delay time section being pre-designed
Ground testing system control instruction, then simultaneously write the data for receiving in two pieces of NAND Flash chips, otherwise according to ground
Test system control instruction is wiped or down operation two pieces of NAND Flash chips, and the data downloaded are sent out by LVDS
Device is sent outwards to export.Ground testing system control instruction includes erasing, downloads, stops downloading.
Memory plane C1 and memory plane C2 backup each other.Two pieces of NAND Flash chips P1, P2 also backup each other in memory plane.
Power module is that each device on memory plane is powered.
Golden finger is used to draw the pin of two pieces of NAND Flash chips, power module, FPGA unit on memory plane
Or LVDS transmitters or other related devices are when failing, NAND Flash chips can be write from outside, wipe or under
Carry operation.
As shown in figure 3, FPGA unit includes clock generation module, reset signal generation module, top layer control module, data
Order caching module, command reception module, Flash control modules and data output control module.
Clock generation module is used to produce clock signal needed for the operation of global and modules, can be according to outside input
Clock selection signal selects local crystal oscillator or external clock.
Reset signal generation module produces global reset signal, when the clock signal that clock generation module is produced is effective,
Global reset signal is set to into low level, for by other module resets in addition to clock generation module, being kept for a period of time
Afterwards global reset signal is set to into high level.
After global reset signal is high level, top layer control module produces configuration and enables signal to except clock produces mould
Other modules beyond block, reset signal generation module are configured, after the completion of configuration, top layer control module control FPGA unit
Into running status, the reception of instruction and data is proceeded by, and perform corresponding operation.
Data receiver cache module after configuration is complete, receives the data from LVDS receiver, and the data that will be received
In being buffered in two independent FIFO respectively.
Command reception module is used to receive and parse through the control instruction from RS422 interface chips, exports and gives Flash controls
Module.The instruction of reception has " erasing ", " download " and " stopping downloading ", is respectively completed memory chip erasing, downloads and accordingly deposit
The function of memory data is downloaded in storage module data and stopping.Instruction need to be made decisions, judgement effectively just starts to perform accordingly
Action, instruction judgement mode sentences two modes using three to be carried out.
Command reception module mainly sentences two modules and order solution by Serial data receiving module, synchronous processing module, three
Analysis module composition, parses according to corresponding instruction and enable accordingly signal.Serial data receiving module is used to receive instruction, and
Export to synchronous processing module；Synchronous processing module is used to for the instruction for receiving to synchronize process, exports to three after process
Sentence two modules；The instruction that three sentence two modules is used for receiving carries out three and sentences two process；Command analysis module is used to sentence two by three
Instruction after process is parsed, and signal is enabled accordingly.
Two pieces of NAND Flash chips are resetted, is configured and upper electro-detection during electricity in Flash control modules；If
The control instruction for receiving control module output is not received in the delay time section being pre-designed, then by two independent FIFO
Data correspondence is written in two pieces of NAND Flash chips, if received, according to the control instruction for receiving two pieces is completed
The erasing of NAND Flash chips or down operation；Data output control module is given by the data is activation downloaded.
Data output control module carries out ping-pong buffer operation to the data that Flash control modules send, it is encoded after
Outwards exported by LVDS transmitters.
Flash control modules include Flash reset submodules, Flash configuration submodule, the upper electro-detection submodules of Flash,
Flash erasing submodules, Flash write submodule and Flash reads submodule.Each module is described as follows：
Flash reseting modules：After electrification reset, the reset operation of two pieces of NAND Flash chips is completed so as to Neng Gouzheng
Often work.Flash configuration modules：After the completion of reset, the mode of operation of NAND Flash chips is configured.
The upper electro-detection modules of Flash：After the completion of configuration, the block address that the bad block and last time to NAND Flash chips is write
Detected, defect block addresses are written in bad block table, in the block address write depositor that last time is write.
On memorizer after electricity time delay for a period of time as after 30s automatically into recording status, during start recording, from depositor
Read the block address write of last time, in order to reliability and off-line data processing it is convenient, the block address write from last time it is rear N number of
At block address, i.e., start recording at the block address+N blocks that last time writes.It is achieved thereby that power-off renews function.Power up twice simultaneously
Data between there is 4*NM (4*N million) individual " FF ".In order to prevent conventional data to be capped, after memorizer record is full, no longer
Record.
Flash wipes module：Before writing to NAND Flash chips, according to the wiping of command reception module output
Except instruction is wiped, during erasing, it is necessary first to judged that bad block is not according to the bad block RAM table that upper electro-detection module is set up
Carry out erasing operation；If good block erasing is unsuccessful, need to be marked as bad block and be written in bad block table.
Flash writing modules：Using double-side operation, the data correspondence in two independent FIFO is written to into two pieces of NAND
In Flash chip.
Come without erasing, download and stopping download instruction in 30s after the upper electricity of Flash, then Flash enters recording status.Write
Before, preferably whether block is checked for the position write to last time and presently written block, and good block just carries out two-sided write operation.It is right
The write operation of good block is specific as follows：
(1) from FIFO it is data cached in be successively read four groups of data, every group of data are 8KB；
(2) first group of data is written to first face of first CE of NAND Flash chips, second group of data is write
To second face of first CE, the 3rd group of data are written to into first face of second CE, the 4th group of data are written to into second
Second face of individual CE, and four groups of data write simultaneously, the address of write is last time and writes after block address at N number of block address,
And ensureing corresponding piece of the writing address preferably block, N is 2,3 or 4；
(3) after the completion of the write of every group of data, in the corresponding free area of this group of data write-in block write labelling is made；
(4) said process is repeated, the data cached in FIFO is written in NAND Flash chips.
Last corresponding write block address of write labelling is NAND Flash chip last time and writes in four CE faces
Block address.
Flash reads through model：Using double-side operation, one piece of NAND is selected according to the control instruction of command reception module output
Flash chip, from good block therein data are read, and are sent to data output control module.
Due to employing double-side operation when being programmed Flash operation, read also to be grasped using two-sided reading during Flash
Make.First according to the bad block table set up in upper electro-detection module, good block just carries out read operation to be judged to the current block read.
Wherein good piece two face corresponding blocks for referring to two CE preferably block.
The step of carrying out read operation to good block is as follows：
(1) successively from first face of first CE, second face of first CE, second CE the first face, second CE
The second face read one group of data, every group of data are 8KB；
(2) repeat step (1), completes the reading of data in NAND Flash chips；
(3) by the data of reading, according to reading, sequence integration is into data flow and exports.
In fact, two pieces of NAND Flash chips P1, P2 in C3 of the present invention can also journal, i.e., first deposit P1, P1
P2 is deposited after being filled with.Can be so original 2 times by the expanding storage depth of memory plane C3.
Further, the block address of record can be in real time sent to ground observing and controlling software by memorizer in the present invention, can be with
The block address of real-time monitoring memory read/write, after test terminates, ground observing and controlling software can automatically be calculated in memorizer and stored
Data volume, facilitate data to download.
The parameter of telemetry system measurement at present is more and more, generally with up to a hundred or even hundreds of road telemetry parameter.Tradition is distant
Examining system is in data processing and interpretation typically using the method for artificial interpretation, and this kind of interpretation method is inefficient, the interpretation time
It is long, and easily there is erroneous judgement.Only data frame loss condition is detected during artificial interpretation, or curve is done to measurement parameter
Row interpretation.First method cannot carry out comprehensive interpretation to all of telemetry parameter；Second method is sentenced carrying out big data quantity
During reading, it is slower to do curve, less efficient.
In the present invention, after the data of ground receiver to memorizer, the data for receiving can be added according to not homogeneous automatically
Electric situation is divided into multiple files, while the telemetry parameter to receiving every time carries out automatic interpretation.
The method of segmentation file is as follows：
4*NM " FF " is had between data according to the power-up of not homogeneous, (L≤4* when continuous L " FF " is detected
NM), then it is assumed that be the data of different power-up twice, the data that not homogeneous is powered up are saved as into respectively different data files, use
The data processing and interpretation of test are powered up in not homogeneous.
The method that data for adding electrical testing every time carry out automatic interpretation is as follows：
(1) maximum of each telemetry parameter, minima and average every time plus in the time history of electrical testing, are being calculated
Value；
(2) interpretation is carried out according to maximum, minima and meansigma methodss criterion that each telemetry parameter pre-sets, works as calculating
When maximum, minima and the meansigma methodss for obtaining are satisfied by the telemetry parameter maximum, minima and meansigma methodss criterion, the remote measurement
Parameter interpretation is reasonable.
Embodiment：
1st, memorizer composition
FPGA unit adopts the fpga chip XC3S500E-4CP132I of XILINX companies, NAND Flash cores in memorizer
Piece adopts Micron companies MT29F128G08AJAAAWP, is 16GB per chip block capacity.
Memorizer adopts identical three pieces of memory planes, and wherein memory plane C1 and memorizer C2 is connected with sampler and coder, all for depositing
Sampler and coder data and ground testing system control instruction are stored up, and C1 and C2 backup each other, the two panels Flash data in C1, C2
Backup each other.Memory plane C3 is used for storing external system Backup Data and ground testing system control instruction.
Every piece of memory plane include two pieces of NAND Flash chips, FPGA unit, RS422 interface chips, LVDS receiver,
LVDS transmitters, golden finger and power module.
2nd, FPGA unit design
FPGA unit includes clock generation module, reset signal generation module, top layer control module, data receiver caching mould
Block, command reception module, Flash control modules and data output control module.The IP that clock generation module is provided using ISE
Core produces clock, and using the input clock of 40MHz the operation clock of 80MHz, 40MHz and 20MHz is produced：clk80M、clk40M
And clk20M.Because input clock has two：Local crystal oscillator and external clock, therefore two DCM are designed, by clksel signals
Selected.
Reset signal generation module is set to global reset signal when the clock signal that clock generation module is produced is effective
Low level, is remained above 200ms rearmounted for high level using enumerator.
After global reset signal is high level, top layer control module produces configuration and enables signal to except clock produces mould
Other modules beyond block, reset signal generation module are configured, after the completion of configuration, top layer control module control FPGA unit
Into running status, the reception of instruction and data is proceeded by, and perform corresponding operation.
Data receiver cache module receives the data from LVDS receiver SN65lv1224B, LVDS receiver and data
The clock frequency that order caching module is interacted is 20MHz, LVDS receiver output ten bit data, therefore definition data bit
It is valid data when Gao Erwei is " 11 ".
Due to there is two mutually redundant Flash chips in each memory plane, thus need when designing two it is independent
FIFO, the data of reception are buffered in respectively in two independent FIFO.
Command reception module is used to receive the control instruction of RS422 interface chips, exports after parsing and controls mould to Flash
Block.Instruction transfer rate is 115200bps；Data form is 1 start bit, 8 data bit, and 1 bit parity check position and 1 stop
Stop bit, the transmission sequence of data be low level in a front high position rear.Every time ground testing system sends a frame control instruction, per frame control
System instructs the CMD of totally six bytes, the frame head 0XB8 of a byte and a byte to constitute a complete coding line, coding line
At intervals of 100us, three instructions for repeating constitute frame instruction, and command frame is at intervals of 2ms.
Two pieces of NAND Flash chips are resetted, is configured and upper electro-detection during electricity in Flash control modules.Then etc.
30s is treated, " download ", " erasing " instruction are only responded in 30s.Mode of operation is as follows：
1) if receiving download instruction within 30s, then NAND Flash chip data are downloaded, in downloading data process
In, if receiving stopping download instruction, stopping downloading, Flash control modules enter idle condition, can continue to download
Or erasing instruction.Data are downloaded after completing, and Flash control modules can receive download or erasing instruction also into idle condition.
2) if receiving erasing instruction in 30s, then NAND Flash chip data are wiped, while by current write address
It is reset to NAND Flash chip first address.
3) if being not received by any instruction within 30s, then automatically into write state after 30s, to NAND
Data are sequentially written in behind the currently stored writing address of Flash chip, can be stored and real-time update current write address, when
Front writing address does not disappear after memorizer power-off, can proceed to write from after presently written address after electricity on next time
Enter.Into after write state, any instruction is no longer received.After NAND Flash chips are write all over, then no longer write.
Two pieces of NAND Flash chips of memorizer are synchronously write, and are backuped each other.
Data output control module carries out ping-pong buffer operation to the data that Flash control modules send, then again by number
Sent by LVDS transmitters according to encoding through 8B10B.
3rd, Flash control modules design
Flash control modules include Flash reset submodules, Flash configuration submodule, the upper electro-detection submodules of Flash,
Flash erasing submodules, Flash write submodule and Flash reads submodule.
1) Flash reseting modules
The module mainly completes the reset to Flash chip and operates so as to being capable of normal work.
2) Flash configuration modules
The module major function is that the mode of operation of Flash chip is set after the completion of reset, is defaulted as
Timemode0, is set to Timemode4 during design.
3) electro-detection module on Flash
After the completion of configuration, the block address that the bad block and last time to NAND Flash chips is write is detected, by bad block ground
Location is written in bad block table, in the block address write depositor that last time is write.
Flash chip allows certain bad block amount when dispatching from the factory, so needing being wiped, before reading and writing operation
Flash bad block is detected.The bad block mark position of flash is labeled as 0x00 in the 8192nd position of each block page 1.
In order to improve the writing speed of flash, double-side operation, two chip selection signal (CE) ping-pong operations are adopted during design.In order to ensure
Block address is moved integrally, and by the two-sided address of two CE, totally 4 block address are judged together during design, if having one in 4 blocks
Individual bad block, then skip 4 block address simultaneously.The ram table of 1bit × 4096 is set up when checking bad block, bad block is labeled as ' 0 ',
Good block is labeled as ' 1 '.
During upper electro-detection, the block address that last time writes is found out, the method for lookup is to look for each piece of page 1
Content at 8193 positions, 0x55 is represented written into other representatives do not write, and are at find out last block page 1 8193
The block address that the block address of 0x55, as last time are write.The block address is written in depositor.
4) Flash erasings module
The module major function is to carry out erasing operation to it before write Flash.During erasing, it is necessary first to according to upper
The bad block RAM table that electro-detection module is set up is judged that bad block does not carry out erasing operation；If good block in erase process not into
Work(, then need to be marked as bad block, i.e., be labeled as 0x00 at the 8192nd address of the page 1 of the block.
5) Flash writing modules
Flash writing modules are used to be programmed Flash storage.Double-side operation, its sequential such as Fig. 4 institutes are adopted during design
Show.First to write instruction 80H in bus, write command is represented, be then written to write address, followed by the data for writing, then write
Enter 11H, represent two-sided write operation, then write 80H, write bus after plus 1 by address, followed by the data for writing, write afterwards
10H, represents that this two-sided write operation is completed.Come without erasing, download and stopping download instruction in 30s after the upper electricity of flash, then
Flash enters recording status.N=2 is chosen, before write, whether preferably block enters for the position write to last time and presently written block
Row checks that good block just carries out two-sided write operation.
6) Flash read operations
Also due to employing double-side operation when operation is programmed to Flash, therefore also must adopt when reading Flash double
Face read operation.First according to the bad block RAM table set up in electrification reset module, good block just enters to be judged to the current block read
Row read operation.Two-sided read operation sequential is as shown in Figure 5.00H is first write in bus, reading instruction is represented, then writing address A,
Then 32H is write, two-sided read operation is represented, then successively write 00H, address B and 30H, 30H represent that this two-sided read operation is complete
Into.Then according to the control of FPGA, data A in the A of address are read.Then 06H, address B and E0H are write successively in bus,
Expression is switched to address B, then according to the control of FPGA, reads data B in the B of address.
4th, in the face of the process of memorizer down-transmitting data
1) according to " FF " that 8M bytes are had between the data of not homogeneous power-up, detecting continuously less than or equal to 8M bytes
" FF ", then it is assumed that be the data of different power-up twice, the data that not homogeneous is powered up saved as into respectively different data files.
2) every time plus in the time history of electrical testing, maximum, minima and the meansigma methodss of each telemetry parameter are calculated.
3) interpretation is carried out according to maximum, minima and meansigma methodss criterion that each telemetry parameter pre-sets, works as calculating
When maximum, minima and the meansigma methodss for obtaining are satisfied by the telemetry parameter maximum, minima and meansigma methodss criterion, the remote measurement
Parameter interpretation is reasonable.
5th, practical situations
Memorizer in the present invention improves memory read/write speed；Function is renewed with power-off, improve memorizer can
By property and convenient test；Meanwhile, the present invention furthermore present process side of the ground testing system to memorizer down-transmitting data
The data of multiple power-up can be automatically divided into multiple files by method, be easy to the further interpretation of data and analysis；During data interpretation
Maximum, minima and the meansigma methodss of each telemetry parameter can be counted, according to the quick interpretation of criterion and sentence read result is provided,
Improve the efficiency and intelligence degree of data interpretation.
The present invention has been applied in certain aircraft, and through Multitest examination, has completely got the every survey of aircraft
Amount parameter, data storage rate and downloading rate improve about one times, during ground test and aircraft flight, support
Repeatedly add power operation, improve system reliability, meet system Special use requirement.Ground can be carried out entirely to telemetry parameter
Face interpretation, the data volume of telemetry parameter is bigger, and it is more that efficiency is improved, and the test flight data for 1 hour, efficiency improves
Nearly 1 times.
The above, optimal specific embodiment only of the invention, but protection scope of the present invention is not limited thereto,
Any those familiar with the art the invention discloses technical scope in, the change or replacement that can be readily occurred in,
All should be included within the scope of the present invention.
The content not being described in detail in description of the invention belongs to the known technology of professional and technical personnel in the field.
Claims (8)
1. a kind of high-speed memory that function is renewed with power-off, it is characterised in that：Including three pieces of memory planes, wherein two pieces of storages
Plate backups each other, for storing sampler and coder framing after data and interface controller forwarding ground testing system control instruction；
3rd piece of memory plane is used for the external system Backup Data and ground testing system control instruction of memory interface controller forwarding；
Three pieces of memory plane compositions are identical, connect including two pieces of NAND Flash chips, FPGA unit, RS422 interface chips, LVDS
Receive device, LVDS transmitters and power module；
LVDS receiver on mutually redundant two pieces of memory planes is used to receive the data after sampler and coder framing, and exports to FPGA
Unit；LVDS receiver on 3rd piece of memory plane is used for the external system Backup Data of receiving interface controller forwarding, and exports
To FPGA unit；
RS422 interface chips are used for the ground testing system control instruction of receiving interface controller forwarding, and export mono- to FPGA
Unit；
FPGA unit receives the data from LVDS receiver, if not receiving ground in the delay time section being pre-designed
Test system control instruction, then simultaneously write the data for receiving in two pieces of NAND Flash chips, otherwise according to ground test
System control instruction is wiped or down operation two pieces of NAND Flash chips, and the data downloaded are passed through into LVDS transmitters
Export to ground testing system, the ground testing system control instruction includes erasing, downloads, stops downloading；
Power module is that each device on memory plane is powered.
2. a kind of high-speed memory that function is renewed with power-off according to claim 1, it is characterised in that：It is described per block
Also include golden finger on memory plane, for the pin of two pieces of NAND Flash chips to be drawn, on memory plane power module,
When FPGA unit or LVDS transmitters fail, from outside NAND Flash chips can be write, be wiped by golden finger
Or down operation.
3. a kind of high-speed memory that function is renewed with power-off according to claim 2, it is characterised in that：The FPGA
Unit includes clock generation module, reset signal generation module, top layer control module, data receiver cache module, command reception
Module, Flash control modules and data output control module；
Clock generation module：Clock signal needed for for producing the operation of global and modules, can according to outside input when
Clock selection signal selects local crystal oscillator or external clock；
Reset signal generation module：Global reset signal is produced, when the clock signal that clock generation module is produced is effective, will be complete
Office's reset signal is set to low level, for by other module resets in addition to itself and clock generation module, when being kept for one section
Between after global reset signal is set to into high level；
Top layer control module：After global reset signal is high level, produces configuration and enable signal to except itself and clock are produced
Other modules beyond raw module, reset signal generation module are configured, after the completion of configuration, top layer control module control FPGA
Unit enters running status；
Data receiver cache module：After the completion of configuration, the data from LVDS receiver are received, and the data of reception are delayed respectively
In there are two independent FIFO；
Command reception module：For receiving and parsing through the control instruction from RS422 interface chips, export and control mould to Flash
Block；
Flash control modules：NAND Flash chips are resetted when upper electric, configured and upper electro-detection；If set in advance
The control instruction for receiving control module output is not received in the delay time section of meter, is then write the data in two independent FIFO
Enter in corresponding NAND Flash chips, if received, correspondence NAND Flash are completed according to the control instruction for receiving
The erasing of chip or down operation；Data output control module is given by the data is activation downloaded；
Data output control module：Ping-pong buffer operation carried out to the data that Flash control modules send, it is encoded after pass through
LVDS transmitters are exported to ground.
4. a kind of high-speed memory that function is renewed with power-off according to claim 3, it is characterised in that：It is described
Flash control modules include that Flash reset submodules, Flash configuration submodules, the upper electro-detection submodules of Flash, Flash are wiped
Except submodule, Flash write submodule and Flash reading submodules；
Flash reset submodules：After electrification reset, the reset operation of two pieces of NAND Flash chips is completed so as to can be normal
Work；
Flash configures submodule：After the completion of reset, the mode of operation of NAND Flash chips is configured；
The upper electro-detection submodules of Flash：After the completion of configuration, the block address that the bad block and last time to NAND Flash chips is write is entered
Row detection, defect block addresses are written in bad block table, in the block address write depositor that last time is write；
Flash wipes submodule：Before writing to NAND Flash chips, if receiving command reception module output
Erasing instruction, then simultaneously erasing operation is carried out to the position beyond two pieces of NAND Flash chip bad blocks, if good block is wiped not
Success, then need to be marked as bad block and be written in bad block table；
Flash writes submodule：The block address that reading last time writes from depositor, using double-side operation, by two independent FIFO
The data correspondence of middle caching is written in the good block that two pieces of NAND Flash chip last time are write after block address；
Flash reads submodule：Using double-side operation, one piece of NAND is selected according to the control instruction of command reception module output
Flash chip, from good block therein data are read, and are sent to data output control module.
5. a kind of high-speed memory that function is renewed with power-off according to claim 4, it is characterised in that：The employing
Double-side operation to the implementation method that one piece of NAND Flash chip carries out write operation is：
(5.1) from FIFO it is data cached in be successively read four groups of data, every group of data are 8KB；
(5.2) first group of data is written to first face of first CE of NAND Flash chips, second group of data is written to
3rd group of data are written to first face of second CE by second face of first CE, and the 4th group of data are written to into second
Second face of CE, and four groups of data write simultaneously, the address of write is last time and writes after block address at N number of block address, N=
2,3 or 4；
(5.3) after the completion of the write of every group of data, in the corresponding free area of this group of data write-in block write labelling is made；
(5.4) said process is repeated, the data cached in FIFO is written in NAND Flash chips.
6. a kind of high-speed memory that function is renewed with power-off according to claim 5, it is characterised in that：The employing
Double-side operation is to the implementation method that one piece of NAND Flash chip carries out read operation：
(6.1) successively from first face of first CE, second face of first CE, first face of second CE, second CE
One group of data is read in second face, and every group of data are 8KB；
(6.2) repeat step (6.1), complete the reading of data in NAND Flash chips；
(6.3) by the data of reading, according to reading, sequence integration is into data flow and exports.
7. a kind of high-speed memory that function is renewed with power-off according to claim 5, it is characterised in that：It is described
The upper electro-detection modules of Flash are to the implementation method that the block address that NAND Flash chip last time writes is detected：
The upper electro-detection modules of Flash read the labelling of NAND Flash chips free area, last write mark in four CE faces
The corresponding write block address of note is the block address write NAND Flash chip last time.
8. a kind of high-speed memory that function is renewed with power-off according to claim 1, it is characterised in that：Ground receiver
To after the data of memorizer, proceed as follows：
(8.1) ground detects to receiving data, when L " FF " is detected, then it is assumed that be the data of different power-up twice,
The data that not homogeneous is powered up are saved as into respectively different data files, the data processing of test is powered up for not homogeneous and is sentenced
Read；Wherein L<=4*NM；
(8.2) every time plus in the time history of electrical testing, maximum, minima and the meansigma methodss of each telemetry parameter are calculated；
(8.3) interpretation is carried out according to maximum, minima and meansigma methodss criterion that each telemetry parameter pre-sets, when calculating
To maximum, minima and meansigma methodss be satisfied by the telemetry parameter maximum, minima and meansigma methodss criterion when, remote measurement ginseng
Number interpretation is reasonable.
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