CN204944518U - The missile-borne telegauge of tape recording function - Google Patents
The missile-borne telegauge of tape recording function Download PDFInfo
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- CN204944518U CN204944518U CN201520714290.6U CN201520714290U CN204944518U CN 204944518 U CN204944518 U CN 204944518U CN 201520714290 U CN201520714290 U CN 201520714290U CN 204944518 U CN204944518 U CN 204944518U
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Abstract
The utility model discloses a kind of missile-borne telegauge of tape recording function, comprise remote measurement power supply and power management module, described remote measurement power supply is connected with described power management module, for providing working power for missile-borne telegauge; Also comprise Signal-regulated kinase, signals collecting conversion module, module of gathering and editing and transmitter; Described Signal-regulated kinase is electrically connected with described signals collecting conversion module; Described signals collecting conversion module is electrically connected with described module of gathering and editing; Described module of gathering and editing is electrically connected with described transmitter; Also comprise record memory module, described record memory module is electrically connected with described module of gathering and editing.The utility model carries out storage backup to image data, Backup Data can read landing recovery, can not be subject to electromagnetic interference influence, the acquisition of telemetry is by wireless transmission and reclaim two the approach acquisitions of back-up storage data, improves the acquisition reliability of data.
Description
Technical field
The utility model relates to missile-borne telegauge, is specifically related to a kind of missile-borne telegauge of tape recording function.
Background technology
Missile-borne telegauge is the nucleus equipment of telemetry system on bullet, for gathering the work in every parameter of body before penetrating and in flight course, telegauge carries out volume frame to image data, and serialization process formation binary code stream is carried out to volume frame data, ground telemetering receiving equipment is real-time transmitted to by wireless channel, to carry out analysis and judgment to the running status of system on bullet by transmitter.
Transmitter is compiled frame data to the serialization of missile-borne telegauge and is carried out rf modulations, modulation signal passes through antenna transmission, received by ground receiver antenna, receiver carries out demodulation to the radiofrequency signal received, be reduced into the serialized data of binary code stream, serialized data passes through the synchronous and frame synchronization process of code again, obtains the Frame reduced.In signals transmission, when radiofrequency signal is by electromagnetic interference (EMI), the binary code flow data of receiving equipment reduction can make a mistake, because telemetry carries out organizing transmission frame by frame, when the transmission of individual data makes a mistake, the destruction of full frames of data can be caused to lose.
Mainly there are the following problems for existing method:
The measurement data of tradition missile-borne telegauge only relies on wireless channel and carries out real-time Transmission to image data, and transmission of wireless signals is subject to environment electromagnetics disturbing effect, when transmitting procedure is subject to electromagnetic interference (EMI), telemetry cannot carry out transmitting, part telemetry mistake or loss can be caused, the integrality of telemetry cannot ensure, affects the multianalysis to working state of system on bullet.
Utility model content
The utility model overcomes the deficiencies in the prior art, for remote measurement wireless transmission owing to disturbing the data loss problem caused, provides a kind of missile-borne telegauge of tape recording function.By increasing record memory module in missile-borne telegauge, important test parameter being delivered to memory device in the course of work of remote measurement and carrying out record storage, can read storage data record afterwards.To adopt on the missile-borne telegauge of this technical scheme for remote measurement wireless transmission owing to disturbing the data loss problem that causes, improve the acquisition reliability of important test data.
For solving above-mentioned technical matters, the utility model by the following technical solutions:
A missile-borne telegauge for tape recording function, comprises remote measurement power supply and power management module, and described remote measurement power supply is connected with described power management module, for providing working power for missile-borne telegauge;
Also comprise Signal-regulated kinase, signals collecting conversion module, module of gathering and editing and transmitter; Described Signal-regulated kinase is electrically connected with described signals collecting conversion module; Described signals collecting conversion module is electrically connected with described module of gathering and editing; Described module of gathering and editing is electrically connected with described transmitter;
Also comprise record memory module, described record memory module is electrically connected with described module of gathering and editing.
Further technical scheme is that record memory module arranges serial line interface, for obtaining external command; Described instruction comprises erasing instruction, read instruction and/or stores instruction.
Further technical scheme is that record memory module comprises microcontroller and NandFlash device, and described microcontroller is electrically connected with described NandFlash device.
Further technical scheme is that module installation of gathering and editing has the interface docked with described record memory module; Described interface comprises address wire interface and data line interface.
Further technical scheme has two Signal-regulated kinase and two signals collecting conversion modules at least, and each Signal-regulated kinase is corresponding with a signals collecting conversion module.
Further technical scheme be gather and edit module comprise gather conversion control module, data register, volume frame device and pcm stream generator; Described collection conversion control module is electrically connected with described data register; Described data register is electrically connected with described volume frame device; Described volume frame device is electrically connected with described pcm stream generator; Described pcm stream generator connects transmitter.
Further technical scheme is that module of gathering and editing also comprises address decoder, and described address decoder is connected with described microcontroller by address wire interface, and described address decoder is electrically connected with described data register; Described data register is connected with described microcontroller by data line interface.
Further technical scheme is the relation satisfied 2 between address decoder Input Address line width m and signals collecting way n
m>=n.
Further technical scheme is module of gathering and editing is FPGA device.
Further technical scheme is that module of gathering and editing comprises at least two data registers.
Compared with prior art, the beneficial effects of the utility model are: the missile-borne telegauge of the utility model tape recording function carries out storage backup to image data, Backup Data can read landing recovery, electromagnetic interference influence can not be subject to, can only rely on wireless transmission with existing telegauge obtains compared with the implementation of data, the acquisition of telemetry is by wireless transmission and reclaim two the approach acquisitions of back-up storage data, improves the acquisition reliability of data.
Accompanying drawing explanation
Fig. 1 is the theory diagram of the missile-borne telegauge of the utility model example belt writing function.
Fig. 2 records memory module control flow chart in the utility model embodiment.
Fig. 3 wipes FLASH process flow diagram in the utility model embodiment.
Fig. 4 reads Flash data from serial ports transmission flow figure in the utility model embodiment.
Fig. 5 reads Flash data stored in FLASH process flow diagram in the utility model embodiment.
Embodiment
All features disclosed in this instructions, or the step in disclosed all methods or process, except mutually exclusive feature and/or step, all can combine by any way.
Arbitrary feature disclosed in this instructions (comprising any accessory claim, summary and accompanying drawing), unless specifically stated otherwise, all can be replaced by other equivalences or the alternative features with similar object.That is, unless specifically stated otherwise, each feature is an example in a series of equivalence or similar characteristics.
Below in conjunction with drawings and Examples, embodiment of the present utility model is described in detail.
As shown in Figure 1, the missile-borne telegauge of an example belt writing function of the present utility model, it comprises remote measurement power supply, power management module, Signal-regulated kinase, signals collecting conversion module, module of gathering and editing, transmitter, concrete, and remote measurement power supply is remote measurement battery.
Concrete, remote measurement battery by power management module for missile-borne telegauge provides working power.
Signal-regulated kinase is responsible for processing input signal, converts the signal into the form that applicable signals collecting conversion module receives.
Signals collecting conversion module, under the control of module of gathering and editing, carries out analog to digital conversion to input signal, and exports the digital signal after conversion to module of gathering and editing.
Module of gathering and editing provides data changeover control signal to signals collecting conversion module, after receiving translation data, carries out buffer memory to data, and by the data cached format sequential composition digital frame by presetting, carrying out serialization process form data code flow to digital frame; The data cached of module of gathering and editing provides digital independent interface.
Concrete, module of gathering and editing realizes primarily of FPGA device, is provided with and gathers conversion control module, data register, volume frame device and pcm stream generator in FPGA.
Multiplexed signal sampling conversion module can be controlled by collection conversion control module FPGA to change input signal simultaneously, setting data register corresponding with signals collecting conversion module in FPGA, the output data of FPGA receiving conversion module periodically update the storing value of data register.Compile frame device by the form preset such as:
| Frame head | Register 1 data | Register 2 data | …… | Register n data | Frame count | Frame synchronization code |
Order is peek composition digital frame from data register, then carries out serialization process by pcm stream generator to digital frame and form data code flow.
Transmitter receives serial data bit stream, carries out signal madulation, becomes radiofrequency signal and sends transmission by antenna again.
Preferably, the missile-borne telegauge of the present embodiment tape recording function, also comprise record memory module, module of gathering and editing provides and records the interface between memory module, and interface comprises address wire interface and data line interface, when module of gathering and editing receives address date, module of gathering and editing utilizes address decoder decoding, produce gating signal, be strobed the data register that signal specifies and data are delivered to data line, module data line of gathering and editing when not having data register to be strobed is high-impedance state.Record memory module is formed primarily of microcontroller and Large Copacity NandFlash device, and microcontroller selects device model to be stm32f103Zx chip, and Large Copacity NandFlash device selects device model to be K9K8G08U0M storage chip.The address wire that microcontroller utilizes its parallel data FSMC interface to provide, 8 position datawires, control signal wire are connected with gather and edit module and NandFlash device respectively, external control instruction is received by serial ports, instruction is divided into erasing instruction, stores instruction, reads recording instruction, concrete director data can be made by oneself, should ensure that microcontroller can distinguish different instruction state.
During physical circuit design, the relation between the address decoder Input Address line width m of module of gathering and editing and signals collecting way n meets 2
mthe FSMC parallel data grabbing card address wire of>=n, stm32f103Zx chip is 26 BITBUS network A [25:0], gets A [m-1:0] wherein and is connected with the m bit address line of FPGA address decoder.
The data line that the data port of Nandflash device and module of gathering and editing provide is 8 three-state data interfaces, with FSMC parallel data grabbing card data line D [7:0] parallel join of stm32f103Zx chip.Control signal between stm32f103Zx chip and NandFlash device comprises chip selection signal NCE, read signal NOE, write signal NWE, instruction latch signal CLE, address latch signal ALE, waiting signal NWAIT, the corresponding function pin of stm32f103Zx chip and NandFlash should be interconnected.
During work, address wire to be given the address decoder of FPGA by the NOR/PSRAM read-write sequence of FSMC interface and receives the data register data of gating from the data line of FPGA by stm32f103Zx chip.Stm32f103Zx chip carries out reading and writing data by the Nand16bit read-write sequence of FSMC interface and NandFlash.
As shown in Figure 2, openly telegauge record memory module control flow is as follows further for the present embodiment:
1, device Initialize installation:
Initialize installation comprises the configuration of devices function clock, FSMC configuration, and serial port function configures.
Configuration effort clock makes stm32f103Zx device system clock be 72MHz, and bus clock is 36MHz, arranges timer conter and is every millisecond and adds 1.Configuration FSMC functional pin, determines NOR/PSRAM sequential and Nand16bit read-write sequence parameter, and enable FSMC interface.Configuration serial port function pin, arranges serial port baud rate and enable serial ports.
2, reception judges serial ports instruction:
Detect serial ports by inquiry or interrupt mode and whether receive data, then receive FIFO stored in serial ports if any data.The director data sequence that pre-defined erasing instruction, read instruction are different with storage instruction three kinds, the data reading and instruction received by serial ports in FIFO contrasts, and as consistent, be judged to and receive corresponding instruction.
After receiving erasing instruction, carry out erasing NandFlash operate, return continuation reception after completing erasing and judge serial ports instruction.
After receiving read instruction, read NandFlash data, reading data are sent by serial ports, return continuation reception after being sent completely and judge serial ports instruction.
Store timing after instruction and read FPGA data when receiving and also write NandFlash, until write full after return to continue to receive and judge serial ports instruction.
As shown in Figure 3, FLASH flow process is wiped in the present embodiment as follows:
There are 8192 storage blocks in NandFlash device K9K8G08U0M, need wipe one by one each storage block during erasing device.First should write first piece of erasing instruction to Flash when wiping single piece, write-in block erasing address, writes second piece of erasing instruction, in erase process, NWAIT signal remains low level, when NWAIT signal becomes high level, block erasure completion, repeatable block erase process is until device completes erasing.
As shown in Figure 4, FLASH data are read in the present embodiment as follows from serial ports transmission flow:
In NandFlash device K9K8G08U0M, each storage block has 64 pages, and each page can store 2048 bytes.When reading Flash data, need read one by one each storage block, read page by page in block.First instruction should be read to Flash write first when reading single page, write reading page address, instruction is read in write second, and at this moment NWAIT signal becomes low level, when waiting for that NWAIT signal becomes high level, continuous 2048 read signals can read all storage data in page, when reading, often complete reading and the transmission of a page data in block, page address adds 1, after completing the reading of all pages in block, block address adds 1, and page address in block is reset to 0.
Sense data leaves serial ports in and sends in FIFO, makes regular check in FIFO whether have number, has several, takes out and transfers to serial ports to send, until FIFO reads sky.
As shown in Figure 5, FPGA data are read in the present embodiment as follows stored in FLASH flow process:
Read FPGA data stored in FLASH for completing, first should carry out initial work, comprising the initial value arranging write-in block address is 0, and the initial value arranging write page address is 0,
The array buffer memory of definition two 2048 bytes is used as " writing BUF ", and defining variable " is write BUF and got out mark ".Ping-pong operation is carried out to two data, when writing data, data are written into an array, and during read data, data then go out from another array corner, count write data, two array read-write role exchanges when an array is write full, and set " writes BUF to be ready to " mark.
Judge whether that arriving sampling instant is by timer conter divided by predetermined period value, the integral multiple being predetermined period value as time counter value is then judged to arrival sampling instant, otherwise waits for that timing reader judges after upgrading again.
Record memory module periodically reads the data of data register in FPGA when sampling instant arrives, by the value of timing reader together with data stored in " writing BUF ", detect " writing BUF to be ready to " mark simultaneously, have enough data can carry out once page write operation to NandFlash device as flag set then represents in " writing BUF ".When carrying out Flash page write operation, need write page by page each storage block.Should write the first write command to Flash successively, write page address, from " writing BUF ", read 2048 byte write Flash, write the second write command, at this moment NWAIT signal becomes low level, and when waiting for that NWAIT signal becomes high level, page write operation completes.
The present embodiment carries out record to important telemetry parameter and stores and reclaim reading, by increasing the acquiring way of test parameter, improves the acquisition reliability of data.
Spoken of in this manual " embodiment ", " another embodiment ", " embodiment ", etc., refer to the specific features, structure or the feature that describe in conjunction with this embodiment and be included at least one embodiment of the application's generality description.Multiple place occurs that statement of the same race is not necessarily refer to same embodiment in the description.Furthermore, when describing specific features, structure or a feature in conjunction with any one embodiment, what advocate is also drop in scope of the present utility model to realize this feature, structure or feature in conjunction with other embodiments.
Although the multiple explanatory embodiment here with reference to utility model is described the utility model, but, should be appreciated that, those skilled in the art can design a lot of other amendment and embodiment, these amendments and embodiment will drop within spirit disclosed in the present application and spirit.More particularly, in the scope of the open claim of the application, multiple modification and improvement can be carried out to the building block of subject combination layout and/or layout.Except the modification of carrying out building block and/or layout is with except improvement, to those skilled in the art, other purposes also will be obvious.
Claims (10)
1. a missile-borne telegauge for tape recording function, comprises remote measurement power supply and power management module, and described remote measurement power supply is connected with described power management module, for providing working power for missile-borne telegauge;
Also comprise Signal-regulated kinase, signals collecting conversion module, module of gathering and editing and transmitter; Described Signal-regulated kinase is electrically connected with described signals collecting conversion module; Described signals collecting conversion module is electrically connected with described module of gathering and editing; Described module of gathering and editing is electrically connected with described transmitter; It is characterized in that:
Also comprise record memory module, described record memory module is electrically connected with described module of gathering and editing.
2. the missile-borne telegauge of tape recording function according to claim 1, is characterized in that described record memory module arranges serial line interface, for obtaining external command; Described instruction comprises erasing instruction, read instruction and/or stores instruction.
3. the missile-borne telegauge of tape recording function according to claim 1, it is characterized in that described record memory module comprises microcontroller and NandFlash device, described microcontroller is electrically connected with described NandFlash device.
4. the missile-borne telegauge of tape recording function according to claim 3, is characterized in that described module installation of gathering and editing has the interface docked with described record memory module; Described interface comprises address wire interface and data line interface.
5. the missile-borne telegauge of tape recording function according to claim 1, it is characterized in that having two Signal-regulated kinase and two signals collecting conversion modules at least, and each Signal-regulated kinase is corresponding with a signals collecting conversion module.
6. the missile-borne telegauge of tape recording function according to claim 4, is characterized in that described module of gathering and editing comprises and gathers conversion control module, data register, volume frame device and pcm stream generator; Described collection conversion control module is electrically connected with described data register; Described data register is electrically connected with described volume frame device; Described volume frame device is electrically connected with described pcm stream generator; Described pcm stream generator connects transmitter.
7. the missile-borne telegauge of tape recording function according to claim 6, it is characterized in that described module of gathering and editing also comprises address decoder, described address decoder is connected with described microcontroller by address wire interface, and described address decoder is electrically connected with described data register; Described data register is connected with described microcontroller by data line interface.
8. the missile-borne telegauge of tape recording function according to claim 7, is characterized in that the relation between described address decoder Input Address line width m and signals collecting way n meets 2
m>=n.
9. the missile-borne telegauge of the tape recording function according to claim 1 or 4 or 6, is characterized in that described module of gathering and editing is FPGA device.
10. the missile-borne telegauge of tape recording function according to claim 6, is characterized in that described module of gathering and editing comprises at least two data registers.
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| CN201520714290.6U CN204944518U (en) | 2015-09-15 | 2015-09-15 | The missile-borne telegauge of tape recording function |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106649142A (en) * | 2016-12-02 | 2017-05-10 | 北京航天长征飞行器研究所 | High-speed memorizer with outage renew function |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106649142A (en) * | 2016-12-02 | 2017-05-10 | 北京航天长征飞行器研究所 | High-speed memorizer with outage renew function |
| CN106649142B (en) * | 2016-12-02 | 2019-09-06 | 北京航天长征飞行器研究所 | A kind of high-speed memory renewing function with power-off |
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