CN111324917A - System and method for realizing power-off resume function by FPGA (field programmable Gate array) - Google Patents

Abstract

The invention discloses a system and a method for realizing a power-off resume function by an FPGA (field programmable gate array), which mainly comprise a power-on reset detection module, a binary search module, an SPI (serial peripheral interface) read-write control module and a data FIFO (first in first out) module. Aiming at the problems that a circuit is possible to generate transient faults, so that a fault recorder loses power, and data cannot be written into a Flash chip after being electrified again or a large amount of time is needed to search a storage position before last power failure.

Description

System and method for realizing power-off resume function by FPGA (field programmable Gate array)

Technical Field

The invention relates to a data storage method for powering on a system again after power failure, in particular to a system and a method for realizing a power failure storage function by an FPGA (field programmable gate array).

Background

With the rapid development of information technology in the field of telemetry, the demand of information is rapidly increasing, and higher requirements are also put forward on data storage systems. In some special applications, it is sometimes necessary to continue to store critical data received by the system in real time in the event that the system is powered off and powered back on, and finally to enable playback of the data for subsequent data analysis and processing.

The motion parameters of the projectile in the flying process are very important to control and calibrate the projectile body, and the flying parameters need to be recorded by using a data acquisition memory. However, during the flying process of the rocket, a fault of instantaneous power failure may occur, which results in the loss of the address to be written in the main controller, thereby causing the problem that the data cannot be written into the Flash chip after being powered on again, and such a situation is not favorable for data recording and subsequent analysis work.

In the prior art, Flash sectors are sequentially detected, that is, sectors are searched step by step from the first step of starting sectors in a storage area until a sector which is not stored yet is found, and then current data is stored. This approach requires detection of all currently stored sectors, which consumes a lot of time when data is stored, which reduces efficiency, and requires a limited time when the rocket is in flight, and the method of power-off resume in the prior art causes data loss when power-off is resumed.

Therefore, in the modern data storage system research, how to detect the remaining capacity of the storage system to achieve high-speed storage and power-off restoration of data has become a hot issue of research.

Disclosure of Invention

In order to solve the technical problem of instantaneous power failure, the invention provides a method for realizing a power failure resume function by an FPGA. When the power is turned on again after the instantaneous power failure, the data is ensured to be stored continuously from the stored data, the problem that the data cannot be written into Flash is avoided, the reliability of data storage is improved, and the searching efficiency of the method is higher.

The invention provides the following technical scheme:

a system for realizing a power-off continuous storage function by an FPGA (field programmable gate array) comprises a power-on reset detection module, a binary search module, an SPI (serial peripheral interface) read-write control module and a data FIFO (first in first out) module; wherein:

after power-on reset, a power-on reset detection module firstly detects a special storage address to read valid data so as to determine an approximate storage position;

the power-on reset detection module is connected with the folded half search module, and after detecting power-on, the power-on reset detection module sends the power-on reset detection module to the folded half search module to start searching the written page number before power failure;

the binary search module is respectively connected with the SPI read-write control module and the data FIFO module, reads the Flash storage content by controlling the SPI read-write control module, and finds the written page number by using a binary search algorithm;

the data FIFO module and the two ends are respectively connected with the serial port receiving end and the SPI read-write control module, when the written page number is found by the second half searching module, the written page number information and a signal which permits to be written into the Flash chip are transmitted to the data FIFO module, and the serial port data can be ensured to be continuously written into the Flash chip after the written page number before power failure, so that the function of power failure continuous storage is completed.

Furthermore, the input end of the semi-searching module is connected with the power-on reset detection module and used for receiving a starting searching signal, and the output end of the semi-searching module is connected with the data FIFO module and the SPI control read-write module.

Further, the half-folding searching module finds the written page number through a half-folding searching algorithm and is realized by a state machine, variables of a first page and a last page are defined, and the written page number before power failure is finally found through half-folding approximation; after finding, the written page number information and the permission receiving data signal are output to the data FIFO module, so that the system continues to save the data.

A method for realizing a power-off resume function by an FPGA (field programmable gate array) comprises the following steps of:

s1, transmitting the data to a cache region of the FPGA through a serial port, and writing the data into a Flash chip through an SPI read-write control module in the FPGA when the data amount meets the storage byte amount of one page of Flash;

s2, when the storage system is powered on again after being powered off instantly, the power-on reset module in the FPGA is triggered, and the power-on reset module starts to turn on the half-folded searching module to search the written number of pages of the Flash chip before the power off;

s3, when the number of written pages before power failure is found out by the halving search module, the parameter of the number of written pages is transmitted to the SPI read-write control module, so that the system writes the data in the cache area into the Flash chip after the written pages before the power failure, and the power failure resume function is completed.

Further, the specific steps of searching the written number of pages of the Flash chip before power failure by the halving searching module are as follows:

(1) defining three variable parameters Min, Max and k, wherein the Min variable is the first page of the Flash chip, and the Max variable is the last page of the Flash chip;

(2) k is k = (Min + Max)/2;

(3) the halving searching module inquires the k page of the Flash through the SPI read-write control module, detects whether the page is written, if the data is written, the step (4) is carried out, and if the data is not written, the step (5) is carried out;

(4) the kth page has not yet been written with data; assigning a Max variable to a k value, keeping a Min variable unchanged, and returning to the step (2);

(5) if the data is written into the k page, the Min variable is endowed with the k value, the Max variable is unchanged, and the step (2) is returned;

(6) and (5) when the condition of Max-Min =1 is met, the number of the continuous pages to be searched is Max, namely the search is completed.

Compared with the prior art, the invention has the beneficial effects that: the method takes the FPGA as a main controller, utilizes the algorithm of the fold-and-half search and the special storage space indication storage position to quickly find out the written range in the storage chip after power-on reset, can quickly find out the written page number of the Flash of the circuit breaker after power-on by utilizing the fold-and-half search algorithm, ensures that data transmitted after power-on can be written in after the written page before the power interruption, and has higher search speed compared with the existing power interruption continuous storage method. And if the stored data amount is more, the time consumed by the existing sequential searching method is more, the flight time of the rocket is limited, and the data loss can be caused.

Drawings

FIG. 1 is a block diagram of the system of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

As shown in fig. 1, a method for implementing a power-off resume function by an FPGA of the present invention includes the following steps:

a system for realizing a power-off continuous storage function by an FPGA (field programmable gate array) comprises a power-on reset detection module, a binary search module, an SPI (serial peripheral interface) read-write control module and a data FIFO (first in first out) module; wherein:

after power-on reset, a power-on reset detection module firstly detects a special storage address to read valid data so as to determine an approximate storage position;

the power-on reset detection module is connected with the folded half search module, and after detecting power-on, the power-on reset detection module sends the power-on reset detection module to the folded half search module to start searching the written page number before power failure;

the binary search module is respectively connected with the SPI read-write control module and the data FIFO module, reads the Flash storage content by controlling the SPI read-write control module, and finds the written page number by using a binary search algorithm;

the data FIFO module and the two ends are respectively connected with the serial port receiving end and the SPI read-write control module, when the written page number is found by the second half searching module, the written page number information and a signal which permits to be written into the Flash chip are transmitted to the data FIFO module, and the serial port data can be ensured to be continuously written into the Flash chip after the written page number before power failure, so that the function of power failure continuous storage is completed.

And the input end of the semi-searching module is connected with the power-on reset detection module and is used for receiving a starting searching signal, and the output end of the semi-searching module is connected with the data FIFO module and the SPI control read-write module.

The half-folding searching module finds the written page number through a half-folding searching algorithm and is realized by a state machine, the variables of a first page and a last page are defined, and the written page number before power failure is finally found through half-folding approximation; after finding, the written page number information and the permission receiving data signal are output to the data FIFO module, so that the system continues to save the data.

A method for realizing a power-off resume function by an FPGA (field programmable gate array) comprises the following steps of:

s1, transmitting the data to a cache region of the FPGA through a serial port, and writing the data into a Flash chip through an SPI read-write control module in the FPGA when the data amount meets the storage byte amount of one page of Flash;

s2, when the storage system is powered on again after being powered off instantly, the power-on reset module in the FPGA is triggered, and the power-on reset module starts to turn on the half-folded searching module to search the written number of pages of the Flash chip before the power off;

s3, when the number of written pages before power failure is found out by the halving search module, the parameter of the number of written pages is transmitted to the SPI read-write control module, so that the system writes the data in the cache area into the Flash chip after the written pages before the power failure, and the power failure resume function is completed.

The binary search algorithm is an important algorithm of an ordered sequence in a data structure, and the basic idea is that in a search interval, data elements to be searched are compared with data elements on a central subscript, and if the data elements are equal to the data elements on the central subscript, the search is successful. Otherwise, when the former is smaller than the latter, the search interval is set as the first half section of the original search interval, and the process is continued; if the former is larger than the latter, the interval is determined as the second half of the original search interval, and the process is continued. Such a search process proceeds until the starting index of the search interval is greater than the ending index of the search interval.

If an upper bound of the maximum value of the difference between every two adjacent elements in the ordered sequence is known, MAX = MAX_2≤i≤n{A[i]An A [ i-1 ]]And if M is known and is more than or equal to MAX, screening can be performed once before halving of each cycle, and unnecessary elements are filtered out as much as possible, so that the searching speed can be greatly increased.

The searching process is the down comparison of one layer by one layer, and the next layer is entered if the searching is unsuccessful each time. The maximum comparison times are the height of the judgment tree plus 1.

To realize the function of continuous transmission of the data storage system in case of power failure, the system must automatically and accurately identify the recorded position of the data storage system immediately before power failure when power failure occurs accidentally and power is turned on again, and feed back the effective programming address to the main controller as the first address in continuous recording.

The specific steps of searching the written number of pages of the Flash chip before power failure by the halving searching module are as follows:

(1) defining three variable parameters Min, Max and k, wherein the Min variable is the first page of the Flash chip, and the Max variable is the last page of the Flash chip;

(2) k is k = (Min + Max)/2;

(3) the halving searching module inquires the k page of the Flash through the SPI read-write control module, detects whether the page is written, if the data is written, the step (4) is carried out, and if the data is not written, the step (5) is carried out;

(4) the kth page has not yet been written with data; assigning a Max variable to a k value, keeping a Min variable unchanged, and returning to the step (2);

(5) if the data is written into the k page, the Min variable is endowed with the k value, the Max variable is unchanged, and the step (2) is returned;

(6) and (5) when the condition of Max-Min =1 is met, the number of the continuous pages to be searched is Max, namely the search is completed.

The invention discloses a system and a method for realizing a power-off continuous storage function by an FPGA (field programmable gate array). aiming at the problem that a fault recorder loses power due to the possibility of transient fault of a line, so that data cannot be written into a Flash chip after being electrified again or a large amount of time is needed to search a storage position before the last power-off.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims (5)

1. The utility model provides a system of outage persistence function that FPGA realized which characterized in that: the device comprises a power-on reset detection module, a binary search module, an SPI read-write control module and a data FIFO module; wherein:

after power-on reset, a power-on reset detection module firstly detects a special storage address to read valid data so as to determine an approximate storage position;

the power-on reset detection module is connected with the folded half search module, and after detecting power-on, the power-on reset detection module sends the power-on reset detection module to the folded half search module to start searching the written page number before power failure;

the binary search module is respectively connected with the SPI read-write control module and the data FIFO module, reads the Flash storage content by controlling the SPI read-write control module, and finds the written page number by using a binary search algorithm;

the data FIFO module and the two ends are respectively connected with the serial port receiving end and the SPI read-write control module, when the written page number is found by the second half searching module, the written page number information and a signal which permits to be written into the Flash chip are transmitted to the data FIFO module, and the serial port data can be ensured to be continuously written into the Flash chip after the written page number before power failure, so that the function of power failure continuous storage is completed.

2. The FPGA-implemented power-off resume function system of claim 1, wherein: and the input end of the semi-searching module is connected with the power-on reset detection module and is used for receiving a starting searching signal, and the output end of the semi-searching module is connected with the data FIFO module and the SPI control read-write module.

3. The FPGA-implemented power-off resume function system of claim 2, wherein: the half-folding searching module finds the written page number through a half-folding searching algorithm and is realized by a state machine, the variables of a first page and a last page are defined, and the written page number before power failure is finally found through half-folding approximation; after finding, the written page number information and the permission receiving data signal are output to the data FIFO module, so that the system continues to save the data.

4. The method for realizing the power-off and memory-resuming function of the FPGA according to claim 1, comprising the following steps:

s1, transmitting the data to a cache region of the FPGA through a serial port, and writing the data into a Flash chip through an SPI read-write control module in the FPGA when the data amount meets the storage byte amount of one page of Flash;

s2, when the storage system is powered on again after being powered off instantly, the power-on reset module in the FPGA is triggered, and the power-on reset module starts to turn on the half-folded searching module to search the written number of pages of the Flash chip before the power off;

s3, when the number of written pages before power failure is found out by the halving search module, the parameter of the number of written pages is transmitted to the SPI read-write control module, so that the system writes the data in the cache area into the Flash chip after the written pages before the power failure, and the power failure resume function is completed.

5. The method for realizing the power-off and memory-resuming function of the FPGA according to claim 4, wherein: the specific steps of searching the written number of pages of the Flash chip before power failure by the halving searching module are as follows:

(1) defining three variable parameters Min, Max and k, wherein the Min variable is the first page of the Flash chip, and the Max variable is the last page of the Flash chip;

(2) k is k = (Min + Max)/2;

(3) the halving searching module inquires the k page of the Flash through the SPI read-write control module, detects whether the page is written, if the data is written, the step (4) is carried out, and if the data is not written, the step (5) is carried out;

(4) the kth page has not yet been written with data; assigning a Max variable to a k value, keeping a Min variable unchanged, and returning to the step (2);

(5) if the data is written into the k page, the Min variable is endowed with the k value, the Max variable is unchanged, and the step (2) is returned;

(6) and (5) when the condition of Max-Min =1 is met, the number of the continuous pages to be searched is Max, namely the search is completed.

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