CN106603085B - Generating method and generating device for generating polynomial, encoder, controller and electronic equipment - Google Patents
Generating method and generating device for generating polynomial, encoder, controller and electronic equipment Download PDFInfo
- Publication number
- CN106603085B CN106603085B CN201611041572.XA CN201611041572A CN106603085B CN 106603085 B CN106603085 B CN 106603085B CN 201611041572 A CN201611041572 A CN 201611041572A CN 106603085 B CN106603085 B CN 106603085B
- Authority
- CN
- China
- Prior art keywords
- polynomial
- fixed
- polynomials
- minimum
- error correction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
- H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
- H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes
Landscapes
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Algebra (AREA)
- General Physics & Mathematics (AREA)
- Pure & Applied Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Error Detection And Correction (AREA)
- Detection And Correction Of Errors (AREA)
Abstract
The embodiment of the invention discloses a generation method, a generation device, an encoder, a controller and electronic equipment of a BCH code generator polynomial. The encoder includes: an input circuit that receives input information; an output circuit that outputs the encoded information; the coding circuit executes BCH code coding operation; the encoding circuit includes: a first encoding unit for performing a fixed polynomial based encoding operation and a second encoding unit for performing a variable polynomial based encoding operation. The fixed polynomial and the variable polynomial used by the encoder are used for constructing the generator polynomial, so that the area occupied by the pre-stored polynomial and the time delay of a selection circuit are effectively reduced while the cyclic code with variable error correction capability is output.
Description
Technical Field
The present invention relates to the field of cyclic code encoding technologies, and in particular, to a method and an apparatus for generating a BCH code generator polynomial, an encoder, a memory controller, and an electronic device.
Background
The BCH error correcting code is a cyclic check code that is commonly used to correct random errors. Collectively proposed by r.c. bose, d.k.chaudhuri and a.hocquenghem. The linear block code has the characteristics of strict algebraic structure, strong error correction capability, simple structure, easy coding realization and the like.
BCH error correction code (hereinafter referred to as BCH code) is one of cyclic codes in linear block codes, and can be very easily implemented on a circuit and widely used. As a cyclic code, the BCH code may be represented by a specific polynomial. This polynomial is in turn referred to as the generator polynomial g (x) of the BCH code. The generator polynomials g (x) are different for BCH codes with different designed error correction capabilities.
In actual use, a plurality of BCH codes with different error correction capabilities may need to be used. An encoder capable of supporting or implementing variable error correction capability is desirable. As shown in fig. 1, a chinese patent "BCH code encoder and decoder with variable parameters" (patent document No. CN101567696A) provides an encoder storing various generating polynomials g (x) with different error correction capabilities in advance. When in use, the encoder can switch the used g (x) according to the requirement, thereby realizing that the error correction capability of the encoder is variable.
In the process of implementing the invention, the inventor finds that the following problems exist in the related art: in the encoder with variable error correction capability, it is necessary to provide a large circuit area for storing and switching different generator polynomials g (x).
For example, in a flash controller, the error correction capability requirements of different models of flash are different, and at least 56 different generating polynomials g (x) are usually stored in advance. Finite field GF (2)m) The term number r of the generator polynomial g (x) of the BCH code is equal to the error correction capability t multiplied by the information bits m (in flash applications, m is usually 14, t is 17-72). Therefore, in a general flash controller, the number r of terms in g (x) is 238 to 1008.
Based on the above operations, it can be seen that the total storage space of 34888 bits is required for storing the above 56 different g (x), and the area occupied by such a selection circuit is large. In addition, considering that the larger the number of generating polynomials g (x), the longer the delay of the selection circuit will be, which will result in a reduction of the operating frequency of the encoder.
Disclosure of Invention
The embodiments of the present invention mainly solve the technical problem of providing a method, a device, an encoder, a memory controller, and an electronic device for generating a BCH code generator polynomial, which can solve the problems of large storage space occupied by pre-storing a generator polynomial and reduced operating frequency of an encoder in the prior art.
To solve the above technical problem, an embodiment of the present invention provides a method for generating a generator polynomial of a BCH code. The method comprises the following steps: determining a first generator polynomial with a predetermined maximum error correction capability, the first generator polynomial being a product of a plurality of minimum polynomials; (ii) a A minimum polynomial set for representing the product of one or more of said minimum polynomials, each said minimum polynomial set being a fixed polynomial dividing at least one of said fixed polynomials in said first generator polynomial to form a set of fixed polynomials; the set of fixed polynomials comprises one or more of the fixed polynomials; setting a target error correction capability, and selecting at least one fixed polynomial in the fixed polynomial set according to the target error correction capability; the target error correction capability is less than or equal to the maximum error correction capability; calculating a product of remaining minimum polynomials except for the selected fixed polynomial as a variable polynomial; and dividing a second generator polynomial with target error correction capability by the selected fixed polynomial to obtain a remainder as a variable polynomial, wherein the second generator polynomial with the target error correction capability is obtained by multiplying the variable polynomial by the fixed polynomial.
Optionally, the set of fixed polynomials comprises: n +1 fixed polynomials of P (0) to P (n); wherein P (n) is the product of the first m × (n +1) least polynomials of the first generator polynomial; m is the minimum polynomial number P (0) has; n is a positive integer.
Optionally, the dividing at least one fixed polynomial in the first generator polynomial specifically includes: averagely dividing the minimum polynomial sequence of the first generated polynomial into k minimum polynomial groups, wherein k is a positive integer; each set of minimum polynomials comprises either x or x-1 minimum polynomials; taking the first x minimum polynomials as a first fixed polynomial, wherein x and m are equal and are used for indicating the number of minimum polynomials in the first fixed polynomial; performing a recursive operation until a minimum polynomial quantity of the fixed polynomial is closest to a minimum polynomial quantity of the first generator polynomial, with the first fixed polynomial as an initial value; the recursive operation is: the product of the fixed polynomial and the last x least polynomials is calculated as the next fixed polynomial.
Optionally, the selecting at least one fixed polynomial from the set of fixed polynomials according to the target error correction capability specifically includes: selecting a fixed polynomial of which the number is less than and closest to the target minimum polynomial number; the target minimum polynomial number is the minimum polynomial number of the second generator polynomial with the target error correction capability.
To solve the above technical problem, an embodiment of the present invention provides a generating polynomial generating apparatus for BCH codes. The generation apparatus includes: a maximum generator polynomial generating module for determining a first generator polynomial with a predetermined maximum error correction capability, the first generator polynomial being a product of a plurality of minimum polynomials; the minimum polynomial set is used for expressing the product of one or more minimum polynomials, and each minimum polynomial set is a fixed polynomial; a fixed polynomial generation module for dividing at least one of the fixed polynomials in the first generator polynomial to form a set of fixed polynomials; the set of fixed polynomials comprises one or more of the fixed polynomials; the fixed polynomial selection module is used for setting target error correction capability and selecting at least one fixed polynomial in the fixed polynomial set according to the target error correction capability; the target error correction capability is less than or equal to the maximum error correction capability; calculating a product of remaining minimum polynomials except for the selected fixed polynomial as a variable polynomial; and a variable polynomial generating module, configured to divide a second generator polynomial with a target error correction capability by the selected fixed polynomial to obtain a remainder as a variable polynomial, where the second generator polynomial with the target error correction capability is obtained by multiplying the variable polynomial and the fixed polynomial.
Optionally, the set of fixed polynomials comprises: n +1 fixed polynomials of P (0) to P (n); wherein p (n) is the product of the first m × (n +1) smallest polynomials that generate the polynomials; m is the minimum polynomial number P (0) has; n is a positive integer.
Optionally, the fixed polynomial generating module is specifically configured to: averagely dividing the minimum polynomial sequence of the first generated polynomial into k minimum polynomial groups, wherein k is a positive integer; each set of minimum polynomials comprises either x or x-1 minimum polynomials; taking the first x minimum polynomials as a first fixed polynomial, wherein x and m are equal and are used for indicating the number of minimum polynomials in the first fixed polynomial; performing a recursive operation until a minimum polynomial quantity of the fixed polynomial is closest to a minimum polynomial quantity of the first generator polynomial, with the first fixed polynomial as an initial value; the recursive operation is: the product of the fixed polynomial and the last x least polynomials is calculated as the next fixed polynomial.
Optionally, the fixed polynomial selecting module is specifically configured to: selecting a fixed polynomial of which the number is less than and closest to the target minimum polynomial number; the target minimum polynomial number is the minimum polynomial number of the second generator polynomial with the target error correction capability.
To solve the above technical problem, an embodiment of the present invention provides an encoder applying the generator polynomial as described above. The encoder includes: an input circuit that receives input information; an output circuit for outputting the coded information and a coding circuit for executing BCH code coding operation;
the encoding circuit includes: a first encoding unit for performing a fixed polynomial based encoding operation and a second encoding unit for performing a variable polynomial based encoding operation.
Optionally, the encoder further comprises: a storage circuit to store the set of fixed polynomials; one or more fixed polynomials in the set of fixed polynomials are selected and provided to a first selector of the first encoding unit.
Optionally, the storage circuit stores n +1 fixed polynomials of P (0) to P (n); p (n) is the product of the first m (n +1) smallest polynomials of the first generator polynomial; m is the minimum polynomial number P (0) has; n is a positive integer.
Optionally, the fixed polynomial selected by the first selector is a fixed polynomial of which the minimum polynomial number is smaller than and closest to a target minimum polynomial number; the target minimum polynomial number is the minimum polynomial number of the second generator polynomial with the target error correction capability.
Optionally, the encoder further comprises a polynomial calculation unit; the polynomial calculation unit is configured to calculate the variable polynomial from the fixed polynomial provided to the first encoding unit and provide the variable polynomial to the second encoding unit.
Optionally, the first encoding unit includes: the first multiplier circuit, r first adders and r stages of linear feedback shift registers execute multiplication of a fixed polynomial; the first multiplication circuit is used for determining the feedback of the r-stage linear feedback shift register;
the second encoding unit includes: a second multiplication circuit for executing multiplication operation of variable polynomial, d +1 second adders and a d-stage linear feedback shift register; the second multiplication circuit is used for determining the feedback of the d-stage linear feedback shift register;
the output end of the nth first adder is connected with the nth stage register of the r stages of linear feedback shift registers; the output end of the nth second adder is connected with the nth stage register of the d-stage linear feedback shift register;
the (d +1) th second adder is connected with the (d) th second adder, and the (d) th second adder is connected with the r-stage linear feedback shift register and the last stage register of the d-stage linear feedback shift register respectively; wherein r and d are both positive integers, and n is less than or equal to r or d + 1.
Optionally, the input circuit is connected to an r-th first adder of the first encoding unit and a d + 1-th second adder of the second encoding unit;
the output circuit is connected with the input circuit through a second selector to form a first output path; the output circuit is also connected with a d second adder through the second selector to form a second output path;
the second selector determines whether the output circuit is the first output path or the second output path according to the clock timing.
To solve the above technical problem, an embodiment of the present invention provides a controller for the nonvolatile memory. The storage controller includes an encoder as described above, performing BCH encoding on the input information.
To solve the above technical problem, an embodiment of the present invention provides an electronic device. The electronic device comprises a non-volatile memory applying a controller as described above for storing data information.
According to the generating polynomial generating method provided by the embodiment of the invention, the generating polynomial is divided into a plurality of forms of fixed polynomials and variable polynomials according to a multiplication combination law. When different error correction capabilities are required to be realized, corresponding generator polynomials can be constructed in a mode of selecting different fixed polynomials and variable polynomials and combining the fixed polynomials and the variable polynomials, the generator polynomials do not need to be stored independently, the number of prestored polynomials is reduced, and therefore the area occupied by the storage circuit is well reduced, and the time delay of the selection circuit is shortened.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.
FIG. 1 is a circuit diagram of a prior art encoding circuit outputting a variable error correction capability BCH;
FIG. 2 is a flowchart of a method for constructing a fixed polynomial set stage according to an embodiment of the present invention;
FIG. 3 is a flowchart of a method for calculating a variable polynomial stage according to an embodiment of the present invention;
FIG. 4 is a circuit diagram of an embodiment of the present invention for implementing BCH coding according to generator polynomial;
FIG. 5 is a functional block diagram of a BCH encoder with variable error correction capability according to an embodiment of the present invention;
FIG. 6 is a circuit diagram of a BCH encoder with variable error correction capability according to an embodiment of the present invention;
FIG. 7 is a diagram illustrating a combination of polynomials with error correction capability of 17 according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of a combination of generator polynomials with error correction capability 11 according to an embodiment of the present invention;
FIG. 9 is a diagram illustrating a combination of polynomials with error correction capability of 4 according to an embodiment of the present invention;
FIG. 10 is a diagram illustrating a combination of polynomials with error correction capability 27 according to another embodiment of the present invention;
FIG. 11 is a diagram illustrating a combination of generating polynomials with error correction capability of 6 according to another embodiment of the present invention;
fig. 12 is a schematic device diagram of a generator for generating a generator polynomial according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The error correction capability of an error correction code is one of the more important parameters of an error correction code. Conventionally, an error correction code is constructed and then the minimum distance is calculated during use. In the BCH code constructing process provided in the embodiment of the present invention, firstly, the number of errors that the BCH code desires to correct (i.e., error correction capability) is considered, and then, the corresponding BCH code is constructed according to the target error correction capability (i.e., correctable random error number).
According to the characteristics of the cyclic code, for (n, k) cyclic code (n is total code length, k is information bit length), all code word polynomials are multiples of certain n-k degree polynomial g (x), and g (x) is xnA factor of + 1. From this, it is understood that the coefficient of the highest order term of g (x) is 1.
For any information sequence m ═ m1，m2，…,mk) Can be defined as:
m(x)＝m1xk-1+m2xk-2+...+mk-1x+mk
from the above discussion, the codeword polynomial c (x) of the corresponding information sequence m in the information sequence may be given by c (x) ═ m (x) g (x). Wherein g (x) is called a generator polynomial of the cyclic code. Obviously, when the information polynomial m (x) is determined, the codeword polynomial can be obtained by generating a polynomial, and the information is encoded.
For example, for a (7,4) cyclic code, its generator polynomial may be x3+x2+1 or x3+ x + 1. From the above description, it can be seen that, in order to implement cyclic code encoding, determining the generator polynomial of the cyclic code is its most important objective.
After the generator polynomial g (x) is determined, a corresponding systematic cyclic code can be generated accordingly. For example, inFinite field GF (2)m) In the above, the coding polynomial for the systematic form coding of BCH codes can be defined by equation (1):
c(x)＝m(x)xn-k+Rem(m(x)xn-k,g(x)) (1)
wherein m (x) is input information, g (x) is a generator polynomial, Rem (a, b) represents a remainder of a/b, n is total code length of BCH, k is information bit length, m (x) xn-kDenotes that m (x) is left-shifted by (n-k) bits.
Assuming that the input message is (1001), the generator polynomial g (x) is used3The specific method of + x +1 coding the (7,4) cyclic codeword is as follows:
1) the message polynomial of (1001) is: m (x) ═ m3x3+m2x2+m1x+m0＝x3+1，
2)m(x)xn-kIs x6+x3
3) Cyclic code polynomial c (x) is c (x) ═ x6+x3+x2+ x. The resulting cyclic codeword is thus (1001110) comprising information bits and redundancy bits.
It can be seen that in cyclic code coding, the generator polynomial is related to the error correction capability of the codeword. Therefore, after determining the number of errors to be corrected (i.e. the correctable random independent errors), the generator polynomial for correcting t random independent errors (hereinafter referred to as error correction capability t) can be determined as:
g(x)＝LCM{m1(x)m2(x)m3(x)...m2t-1(x)m2t(x)} (2)
wherein LCM represents the minimum formula, miIs a minimum polynomial. The minimum polynomial is irreducible in the finite field GF (2)m) Therein with ai(the power of a is expressed in GF (2)m) Any non-zero element in) is the lowest order polynomial of the root. Based on the well-known characteristics of binary BCH codes, the minimum polynomial of an even term must be the same as the minimum polynomial of some odd term. Therefore, the generator polynomial expressed by equation (2) can be simplified as:
g(x)＝LCM{m1(x)m3(x)...m2t-3(x)m2t-1(x)}
as can be seen from equation (2), the error correction capability t is closely related to the minimum polynomial number of the generator polynomial g (x), and the more the minimum polynomial calculated by the generator polynomial g (x), the greater the error correction capability t.
In the generator polynomial g (x), there may be the same minimum polynomial mi(x) E.g. m1(x)m3(x) Likewise, duplicate least polynomials may be removed (i.e., only one may be retained). As shown in equation (1), after removing the same minimum polynomial in g (x), the minimum polynomial of the remaining minimum polynomial is the product of the minimum polynomial. Thus, g (x) can be represented by a product of a plurality of mutually different minimum polynomials (for simplicity of presentation, the generator polynomials in the following embodiments are all represented by mutually different minimum polynomials).
According to the multiplicative binding law, g (x) can be divided into arbitrary sets of products of least polynomials, for example, let g (x) be { m }1(x)m3(x)}{m5(x)m2t-3(x)m2t-1(x) And (4) dividing. It will be understood by those skilled in the art that such partitioning or splitting need not satisfy any constraints and may be performed at will, either as groups of products having the same number of minimum polynomials or as products having different numbers of minimum polynomials. For simplicity of presentation, the "smallest polynomial set" is used to denote the product containing one or more smallest polynomials. The product of each minimum polynomial set is g (x).
According to the property of the generator polynomial of the BCH code described above (i.e. it can be represented by the product of splitting into any minimum polynomial group), in the process of implementing coding, the corresponding minimum polynomial group can be set and stored according to the actual requirement (for example, part of the minimum polynomial group is used as a fixed polynomial set).
When the error correction capability t needs to be adjusted, the minimum polynomial sets which meet the requirements and are stored in advance are selected and combined to obtain a generating polynomial with a certain number of minimum polynomials (namely the error correction capability t), and a BCH code with a preset design code distance is output according to the generating polynomial. The term "fixed set of polynomials" is used herein to mean a pre-stored series of invariant minimum polynomial sets. Wherein each minimum polynomial set is a fixed polynomial.
The above-described manner of combining the plurality of minimum polynomial sets to generate the polynomial can effectively reduce the amount of data that needs to be stored in advance. For example, in order to output a BCH code with error correction capability t between 17 and 72, the original method of independently storing generator polynomials needs to store all possible generator polynomials (60 kinds). With the above-described minimum polynomial set combination, only 5, 3 or less fixed polynomials may need to be stored.
In some embodiments, in order to further reduce the number of the minimum polynomial sets stored in advance, provide a more flexible combination manner or simplify the design of the implementation circuit, the minimum polynomial sets may be set as variable polynomials in addition to the fixed polynomial storage. The variable polynomial is a polynomial obtained by logical calculation, which has better flexibility than a fixed polynomial. For example, the generator polynomial with the target error correction capability t and the remainder of the fixed polynomial may be used as variable polynomials, which may provide more generator polynomials with different error correction capabilities t in the case of storing the same number of fixed polynomials.
In this way, the variable polynomial is determined according to the fixed polynomial used. That is, the correction coefficient is calculated based on the limit of the generator polynomial having the target error correction capability, which is the product of the variable polynomial and the fixed polynomial.
It should be noted that the addition of the set variable polynomial results in additional computational consumption, and a proper balance should be achieved between the computational consumption and the storage capacity for storing the fixed polynomial.
The following is a detailed description of an example in which a fixed polynomial and a variable polynomial form a generator polynomial with a specific error correction capability t:
assuming that the maximum error correction capability that the encoder can achieve is Tmax. In the finite field GF (2)m) In (1) corresponding to maximum error correction capability TmaxIs composed of TmaxA product expression of minimum polynomials different from each other. The whole method comprises two stages of constructing a fixed polynomial set and calculating a variable polynomial.
1) For the stage of constructing a set of fixed polynomials, as shown in FIG. 2, this step may include:
201: the minimum polynomial is divided into k minimum polynomial groups on average in the order, and the number of the minimum polynomial included in each minimum polynomial group is x or x-1 (for the sake of convenience of presentation, it can be assumed that the minimum polynomial number of the k-th minimum polynomial group is x-1, and the minimum polynomial numbers of the remaining minimum polynomial groups are x).
202: the first set of minimum polynomials is stored as the first fixed polynomial P (0) (i.e., the product of the first x minimum polynomials).
203: the product of the second minimum polynomial set and the first fixed polynomial P (0) is regarded as the second fixed polynomial P (1) and stored.
Step 203 (i.e., the strategy of recursive operation) is repeated for the next fixed polynomial. It can be concluded that for the nth least polynomial set, the product of this with the previous fixed polynomial P (n-1) is stored as a fixed polynomial P (n).
204: the execution is repeated until the k-2 th minimum polynomial set. Which can be multiplied by the (k-3) th fixed polynomial P (k-3) to obtain the fixed polynomial P (k-2). Wherein the minimum polynomial number of the fixed polynomial P (k-2) is x (k-2+ 1).
Step 203 above shows a recursive operation in constructing the fixed polynomial, generating the next fixed polynomial based on each previous fixed polynomial. The stopping condition of the recursion is until the second last least polynomial set generates the fixed polynomial P (k-2).
In this way, a plurality of fixed polynomials with successively increasing minimum polynomial numbers can be generated, which can be stored as one set.
2) For the computational variable polynomial stage, as shown in fig. 3, this stage may include the steps of:
301: assume that the target error correction capability of the BCH code to be generated is T (T is less than or equal to T)max). From the above description, it can be determined that the target minimum polynomial number of the generator polynomial with the target error correction capability should be t.
302: among the above-described stored fixed polynomials, the fixed polynomial p (n) whose smallest polynomial number is closest and smaller than t is selected as the fixed polynomial part of the generator polynomial. In such a case, the difference between the fixed polynomial and the target minimum polynomial number is t-x (n + 1).
303: the product of the remaining t-x (n +1) minimum polynomials is calculated as a variable polynomial by an online logical operation. It should be noted that from the description of step 204, it can be determined that the maximum minimum number of polynomials that need to be computed is x-1.
After the calculation in step 303 is completed, both the variable polynomial and the fixed polynomial are determined. Therefore, the generator polynomial with corresponding error correction capability t can be uniquely determined and applied to the encoder to output the BCH code with target error correction capability t.
In the generating process of the generating polynomial of the embodiment, only k-1 fixed polynomials need to be stored to obtain the error correction capability of 0-T in combinationmaxThe generator polynomial changes between the two, and the data size needing to be stored is greatly reduced.
On the other hand, in the above embodiment, the resources (embodied as the area occupied by the implementation circuit) required by the encoder to implement the variable error correction capability generator polynomial are: the amount of storage for storing the fixed polynomial and the amount of calculation for calculating the variable polynomial.
For a fixed TmaxIncreasing the value of k increases the amount of memory but decreases the amount of computation, whereas decreasing the value of k is a function with inflection points. Therefore, those skilled in the art can obtain the optimal k value (at the inflection point) through repeated experiments or suitable optimization algorithms, so as to minimize the area occupied by the circuit.
As described above, the above is only an embodiment of dividing the generator polynomial into one fixed polynomial and one variable polynomial. In practical application, it can also be divided into two or more fixed polynomials. The specific partitioning strategy can be adjusted according to actual conditions, and for each minimum polynomial in the generator polynomial, any combination or adjustment can be performed without any limitation. Any partitioning strategy based on a minimum polynomial or a minimum polynomial set as a basis unit falls within the scope of the present invention.
The embodiment of the invention also provides a generating polynomial generating device for executing the steps of the method. As shown in fig. 12, the apparatus includes: a maximum generator polynomial generation module 10, a fixed polynomial generation module 20, a fixed polynomial selection module 30 and a variable polynomial generation module 40.
The maximum generator polynomial generating module 10 is configured to determine a first generator polynomial with a predetermined maximum error correction capability, where the first generator polynomial is a product of several minimum polynomials. The fixed polynomial generator module 20 is configured to divide at least one fixed polynomial in the first generator polynomial to form a set of fixed polynomials; the set of fixed polynomials comprises one or more fixed polynomials. The fixed polynomial selecting module 30 is configured to select at least one fixed polynomial from the set of fixed polynomials according to a target error correction capability; the target error correction capability is less than or equal to the maximum error correction capability. The variable polynomial generating module 40 is configured to divide the second generator polynomial with the target error correction capability by the selected fixed polynomial, and obtain a remainder as a variable polynomial.
Optionally, the maximum generator polynomial generating module 10, the fixed polynomial generating module 20, the fixed polynomial selecting module 30, and the variable polynomial generating module 40 of the embodiment of the present invention may be further configured to perform any specific step or combination of steps described in the above method embodiments, for example, the fixed polynomial generating module 20 may divide the fixed polynomial into n +1 fixed polynomials of P (0) to P (n). Wherein p (n) is the product of the first m × (n +1) smallest polynomials that generate the polynomials; m is the minimum polynomial number P (0) has; n is a positive integer; alternatively, the fixed polynomial selection module 30 selects the fixed polynomial with the smallest polynomial number that is less than and closest to the smallest polynomial number of the generator polynomial with the target error correction capability. Since the generation apparatus and the generation method in the embodiment of the present invention are based on the same application concept, the corresponding contents or technical solutions in the method embodiment are also applicable to the apparatus embodiment, and are not described in detail herein.
The above-described generation method and generation apparatus can generate a plurality of different fixed polynomials and variable polynomials, and form a generator polynomial having a specific error correction capability (i.e., the minimum number of polynomials) based thereon. The data (e.g., the fixed polynomial) in the step may be stored in any suitable type of data storage device, such as a local storage medium or an online storage medium.
Those of skill would further appreciate that the various illustrative components and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application. The computer software may be stored in a computer readable storage medium, and when executed, may include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a read-only memory or a random access memory.
Conventionally, after determining the generator polynomial, an encoder of cyclic codes can be implemented using a digital circuit based on a linear feedback shift register. For example, a generator polynomial g (x) of the BCH code is calculated according to the designed error correction capability t, and a Linear Feedback Shift Register (LFSR) of length r is used, which determines the feedback according to the generator polynomial g (x), all registers of the LFSR having an initial value of 0.
And carrying out exclusive-or operation on the input data and the most significant bit of the LFSR along with the input of the data until all the input data with k bits are subjected to exclusive-or operation. At this time, the value in the LFSR is the redundancy code of the BCH code, and the redundancy code and the input data of k bits form a systematic codeword with length of k + r bits.
Of course, in practical use, other suitable digital circuits or encoders may be used to implement the encoding of the BCH code.
The basic principle of BCH encoding implemented by a multi-stage register-based multiplication circuit is described in detail below in conjunction with the circuit schematic shown in fig. 4. In the circuit schematic shown in fig. 4, a linear shift register implementation with feedback may be used. The basic encoder circuit may include a multi-stage linear shift register, a multiplier (generator polynomial g (x) multiplication circuit), and an adder.
Let the generator polynomial g (x) corresponding to the multiplication circuit be:
g(x)＝1+g1x+g2x2+...+gn-k-1xn-k-1+xn-k
at 1 st to k clock edges, gate S2 is in position 2, and while the output outputs an information bit, the remainder (item Rem in equation 1) -redundant bits are calculated (each "1" is shifted out of the register into the feedback line, and the divide is subtracted from the divide).
At the k +1 to n clock edges, the gate S2 is at position 1, while the feedback line is disconnected (gate S1 is at position 1), outputting the redundant bit.
Based on the implementation principle similar to that of fig. 4, the embodiment of the present invention further provides a BCH encoder that applies the generating polynomial provided by the above generating method embodiment to realize the variable error correction capability.
FIG. 5 is a functional block diagram of a BCH encoder provided in an embodiment of the present invention. As shown in fig. 5, the main body thereof includes: a first encoding unit 100, a second encoding unit 200, and a polynomial calculation unit 300.
In the present embodiment, based on the generator polynomial constructing method provided in the above-described embodiment, the polynomial calculating unit 300 calculates a specific variable polynomial and supplies it to the second encoding unit 200 and the second encoding unit 200 performs the operation of the above-described variable polynomial. The first encoding unit 100 selects a pre-stored constant polynomial for performing multiplication according to actual conditions.
The various fixed polynomials formed by the division in the above-described embodiments can be stored in various suitable memory circuits having a data storage function. The memory circuit may be included as a part of the first encoding unit 100 or may be provided outside the first encoding unit as an independent part.
The polynomial calculating unit 300 may be implemented by the variable polynomial generating module 400 of the generating apparatus. The encoder can be realized by a software method, or can be realized by an independent hardware circuit, and is used as one of the functional modules of the encoder or independently arranged outside the encoder.
That is, the encoder may only have the first encoding unit and the second encoding unit, and perform the corresponding logical operation according to the input polynomial to output the operation result. The encoder may add or omit some other distinct modules (such as memory circuits, polynomial computation units, etc., as described above).
The first encoding unit 100 and the second encoding unit 200 may be implemented by using any suitable digital circuit that generates corresponding encoded information according to a polynomial, such as the LFSR-based implementation described above.
In the first encoding unit 100, the fixed polynomial may be regarded as a generator polynomial, and corresponding encoded information may be generated. And in the second encoding unit 200, the variable polynomial is regarded as a generator polynomial. Therefore, by synthesizing the operation output results of the first and second encoding units, systematic encoding of a BCH code generating a polynomial composed of a product of a fixed polynomial and a variable polynomial can be obtained.
It should be noted that in the case where some minimum polynomial groups that divide the generator polynomials into two or more groups are used as the fixed polynomials, this can be achieved by adding a corresponding number of first coding units in the encoder as shown in fig. 5. In some embodiments, the generator polynomial may be further divided into more minimum polynomial sets and treated as a fixed polynomial to replace the variable polynomial.
In these embodiments of the encoder with a larger number of first coding units, the logic structure is complicated and the operation frequency is reduced due to the addition of the additional fixed polynomial coding unit (i.e. the first coding unit). Moreover, in practical operation, to speed up encoding, a plurality of encoding units are usually connected in series to perform parallel computation, which further reduces the operation frequency of the encoder. Therefore, setting more first coding units is an unremitting strategy, and the negative effect on the coding efficiency is much larger than the positive effect.
Alternatively, as shown in fig. 6, the first encoding unit 100 may include: a storage circuit (not shown) for storing a fixed polynomial, a first selector 120, a first multiplier 130, a multi-stage register 140, and a first adder 150.
Similarly, the second encoding unit 200 may include: a second multiplier 230, a second multi-stage register 240, and a second adder 250.
The selector 120 and the first multiplier 130 form a fixed polynomial multiplication circuit, and the first adder 150 is provided between the plurality of stages of registers. The operation principle is similar to that of the generator polynomial multiplication circuit shown in fig. 4. In distinction, the storage circuit stores the fixed polynomial generated in the above method embodiment for selection by the selector. The selector 120 may select an appropriate fixed polynomial from the storage circuit according to the error correction capability t actually required by the encoder to perform the multiplication with the input data.
For the second encoding unit, the variable polynomial thereof is provided by the polynomial calculating unit 300, and the specific logical operation processes of the second multiplier 240, the second multi-stage register 240 and the second adder 250 are similar to the implementation principle shown in fig. 4. In the second encoding unit, on the one hand, the polynomial which it uses to perform the multiplication calculation is provided by the polynomial calculation unit 300 (i.e., a variable polynomial). On the other hand, it has a second adder 250, one more than the number of levels of the multi-level register, for integrating the output information of the first coding unit and the second coding unit (i.e. the last adder output of the first coding unit is connected to the second adder).
In the actual encoding operation, after determining the fixed polynomial and the variable polynomial according to the error correction capability t, the following steps are performed by the encoder shown in fig. 6 as feedback of the first encoding unit and the second encoding unit, respectively, so as to realize the BCH code encoding operation with the target error correction capability t.
As shown in fig. 6, the registers are multi-stage registers, each register is connected to an adder at the back, and the last adder is also connected to a register of the first stage through a feedback line to input information. An input circuit for inputting information is connected to the r-th first adder of the first encoding unit and the d + 1-th second adder of the second encoding unit. The output circuit for outputting information is connected to the input circuit through the second selector. Similar to the principle shown in fig. 4, the selector switches to select either the output of information bits via the first output path or the output of redundant bits via the second output path.
The specific switching mode of the selector is as follows: first, the output source is switched to input, and the input is respectively connected to the r-th first adder and the d + 1-th second adder of the first encoding unit 100 and the second encoding unit 200, and each clock edge is updated once, and an information bit is output at the output end (the number of register stages is related to the number of terms of the polynomial).
Then, when all the information is input, the output source is switched to the d-th second adder 250 of the second encoding unit 200 (i.e., the second adder 250 from the right). The d-th second adder 250 is respectively connected to the r-th first adder of the first coding unit and the d + 1-th second adder (i.e., the rightmost second adder) of the second coding unit, and is updated once every clock edge, so that the redundant bit is output at the output terminal.
And finally, finishing BCH coding until all redundant bits are output.
To further state the encoding method with variable error correction capability and the encoding apparatus thereof provided by the embodiments of the present invention, several examples are provided as follows.
For example, assume that the maximum error correction capability of the output supported by the encoding apparatus is TmaxThe corresponding generator polynomial is represented by the product of 17 distinct minimum polynomials:
g(x)＝m1(x)m3(x)...m31(x)m33(x)
if k is 3 (i.e. equal division into 3), it can be divided into two fixed polynomials
p(0)＝m1(x)m3(x)...m9(x)m11(x)
p(1)＝m1(x)m3(x)...m21(x)m23(x)
As shown in fig. 7, if a BCH code with error correction capability t of 17 needs to be output, the selector may select a fixed polynomial P (1) for feedback connection of the first encoding unit 100, and calculate the product of the remaining 5 minimum polynomials as a variable polynomial s (x) for feedback connection of the second encoding unit 200 by the polynomial calculating unit.
As shown in fig. 8, if a BCH code with error correction capability t of 11 needs to be output, the selector selects a fixed polynomial P (0) closest to and smaller than the number of target polynomials (equal to error correction capability t) for feedback connection of first encoding section 100, and calculates the product of the remaining 5 smallest polynomials as variable polynomials for feedback connection of second encoding section 200 by the polynomial calculating section.
As shown in fig. 9, if a BCH code with an error correction capability t of 4 is required to be output (at this time, there is no fixed polynomial that can satisfy the requirement in the storage circuit), the fixed polynomial may be set to all zero for feedback connection of the first encoding unit 100, and the product of the required 4 minimum polynomials may be calculated by the polynomial calculating unit as a variable polynomial for feedback connection of the second encoding unit 200.
In other embodiments, let the maximum error correction capability of the output supported by the encoding device be TmaxThe corresponding generator polynomial is represented by the product of 30 distinct minimum polynomials:
g(x)＝m1(x)m3(x)...m57(x)m59(x)
if the generator polynomial is divided into 5 fixed polynomials and one variable polynomial. Wherein, include following 5 fixed polynomial:
p(0)＝m1(x)m3(x)...m9(x)m11(x)
p(1)＝m1(x)m3(x)...m21(x)m23(x)
p(2)＝m1(x)m3(x)...m33(x)m35(x)
p(3)＝m1(x)m3(x)...m45(x)m47(x)
p(4)＝m1(x)m3(x)...m57(x)m59(x)
as shown in fig. 10, if a BCH code with error correction capability t of 27 is to be output, the selector may select the 4 th fixed polynomial p (3) for the feedback connection of the first encoding unit 100, and calculate the remaining 3 minimum polynomials m through the polynomial calculation unit49(x)m51(x)m53(x) For the feedback connection of the second coding unit 200.
As shown in fig. 11, if a BCH code with error correction capability t of 6 is to be output, the selector may select the 1 st fixed polynomial p (0) for the feedback connection of the first coding unit 100 and set the variable polynomial to all zeros for the feedback connection of the second coding unit 200.
In such an arrangement, only 5 fixed polynomials need to be stored and the maximum number of the polynomial calculation unit calculating the polynomial is less than or equal to 5, so that the generator polynomial with the maximum error correction capability of 30 can be obtained by combination.
The encoder has the capability of variable error correction capability, the number of fixed polynomials to be stored is small, and the encoder can be conveniently applied to occasions with different error correction capability requirements, for example, in the existing controllers of nonvolatile storage media (such as flash memories), the error correction capability requirements of the flash memories of different models are different, the BCH code encoding executed by the encoder can meet the requirements of the flash memory controllers, the circuit consumption is effectively reduced, and the working frequency of the encoder is improved.
The encoder of the embodiment of the present invention may be applied to any suitable BCH code encoding device, and may also be used as a BCH code encoding functional module in a system, and be applied to any suitable system in a combined or independent manner, for example, in a flash memory device that needs to use BCH code to read and write data to achieve higher reliability, or in other electronic devices that apply such a flash memory device, such as a smart phone, a personal computer, a wearable device, a handheld computer, and the like. The electronic device employs such non-volatile memory for storing various suitable types of data information, such as computer-executable programs.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes performed by the present specification and drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (17)
1. A method for generating a generator polynomial of a BCH code is characterized by comprising the following steps:
determining a first generator polynomial with a predetermined maximum error correction capability, the first generator polynomial being a product of a plurality of minimum polynomials; the minimum polynomial set is used for expressing the product of one or more minimum polynomials, and each minimum polynomial set is a fixed polynomial;
dividing at least one of the fixed polynomials in the first generator polynomial to form a set of fixed polynomials; the set of fixed polynomials comprises one or more of the fixed polynomials;
setting a target error correction capability, and selecting at least one fixed polynomial in the fixed polynomial set according to the target error correction capability; the target error correction capability is less than or equal to the maximum error correction capability;
calculating the difference value between the number of the selected fixed polynomials and the target error correction capability, and multiplying the minimum polynomial of the number corresponding to the difference value to obtain a variable polynomial;
and dividing a second generator polynomial with target error correction capability by the selected fixed polynomial to obtain a remainder as a variable polynomial, wherein the second generator polynomial with target error correction capability is obtained by multiplying the variable polynomial by the fixed polynomial.
2. The method of claim 1, wherein the set of fixed polynomials comprises: n +1 fixed polynomials of P (0) to P (n); wherein P (n) is the product of the first m × (n +1) least polynomials of the first generator polynomial; m is the minimum polynomial number P (0) has; n is a positive integer.
3. The method according to claim 2, wherein said dividing at least one of said fixed polynomials in said first generator polynomial comprises:
averagely dividing the minimum polynomial sequence of the first generated polynomial into k minimum polynomial groups, wherein k is a positive integer; each set of minimum polynomials comprises either x or x-1 minimum polynomials;
taking the first x minimum polynomials as a first fixed polynomial, wherein x and m are equal and are used for indicating the number of minimum polynomials in the first fixed polynomial;
performing a recursive operation until a minimum polynomial quantity of the fixed polynomial is closest to a minimum polynomial quantity of the first generator polynomial, with the first fixed polynomial as an initial value;
the recursive operation is: the product of the fixed polynomial and the last x least polynomials is calculated as the next fixed polynomial.
4. The method according to claim 2, wherein the setting a target error correction capability and the selecting at least one fixed polynomial in the set of fixed polynomials according to the target error correction capability comprises:
selecting a fixed polynomial of which the number is less than and closest to the target minimum polynomial number; the target minimum polynomial number is the minimum polynomial number of the second generator polynomial with the target error correction capability.
5. An apparatus for generating a generator polynomial of a BCH code, the apparatus comprising:
a maximum generator polynomial generating module for determining a first generator polynomial with a predetermined maximum error correction capability, the first generator polynomial being a product of a plurality of minimum polynomials; the minimum polynomial set is used for expressing the product of one or more minimum polynomials, and each minimum polynomial set is a fixed polynomial;
a fixed polynomial generation module for dividing at least one of the fixed polynomials in the first generator polynomial to form a set of fixed polynomials; the set of fixed polynomials comprises one or more of the fixed polynomials;
the fixed polynomial selection module is used for setting target error correction capability and selecting at least one fixed polynomial in the fixed polynomial set according to the target error correction capability; the target error correction capability is less than or equal to the maximum error correction capability;
calculating the difference value between the number of the selected fixed polynomials and the target error correction capability, and multiplying the minimum polynomial of the number corresponding to the difference value to obtain a variable polynomial;
and the variable polynomial generating module is used for dividing a second generator polynomial with target error correction capability by the selected fixed polynomial to obtain a remainder as a method of the variable polynomial, and the second generator polynomial with target error correction capability is obtained by multiplying the variable polynomial and the fixed polynomial.
6. The apparatus of claim 5, wherein the set of fixed polynomials comprises: n +1 fixed polynomials of P (0) to P (n); wherein p (n) is the product of the first m × (n +1) smallest polynomials that generate the polynomials; m is the minimum polynomial number P (0) has; n is a positive integer.
7. The apparatus of claim 6, wherein the fixed polynomial generation module is specifically configured to:
averagely dividing the minimum polynomial sequence of the first generated polynomial into k minimum polynomial groups, wherein k is a positive integer; each set of minimum polynomials comprises either x or x-1 minimum polynomials;
taking the first x minimum polynomials as a first fixed polynomial, wherein x and m are equal and are used for indicating the number of minimum polynomials in the first fixed polynomial;
performing a recursive operation until a minimum polynomial quantity of the fixed polynomial is closest to a minimum polynomial quantity of the first generator polynomial, with the first fixed polynomial as an initial value;
the recursive operation is: the product of the fixed polynomial and the last x least polynomials is calculated as the next fixed polynomial.
8. The apparatus of claim 6, wherein the fixed polynomial selection module is specifically configured to:
selecting a fixed polynomial of which the number is less than and closest to the target minimum polynomial number; the target minimum polynomial number is the minimum polynomial number of the second generator polynomial with the target error correction capability.
9. An encoder for generating a polynomial using the method of claim 1, comprising:
an input circuit that receives input information;
an output circuit that outputs the encoded information;
the coding circuit executes BCH code coding operation; the encoding circuit includes: a first encoding unit for performing a fixed polynomial based encoding operation and a second encoding unit for performing a variable polynomial based encoding operation.
10. The encoder of claim 9, further comprising:
a storage circuit to store the set of fixed polynomials;
one or more fixed polynomials in the set of fixed polynomials are selected and provided to a first selector of the first encoding unit.
11. The encoder according to claim 10, wherein the storage circuit stores n +1 fixed polynomials of P (0) to P (n);
p (n) is the product of the first m (n +1) smallest polynomials of the first generator polynomial; m is the minimum polynomial number P (0) has; n is a positive integer.
12. The encoder of claim 11, wherein the fixed polynomial selected by the first selector is a fixed polynomial having a minimum polynomial number less than and closest to a target minimum polynomial number; the target minimum polynomial number is the minimum polynomial number of the second generator polynomial with the target error correction capability.
13. The encoder according to claim 10, characterized in that the encoder further comprises a polynomial computation unit; the polynomial calculation unit is configured to calculate the variable polynomial from the fixed polynomial provided to the first encoding unit and provide the variable polynomial to the second encoding unit.
14. The encoder according to claim 9, wherein the first encoding unit comprises: the first multiplier circuit, r first adders and r stages of linear feedback shift registers execute multiplication of a fixed polynomial; the first multiplication circuit is used for determining the feedback of the r-stage linear feedback shift register;
the second encoding unit includes: a second multiplication circuit for executing multiplication operation of variable polynomial, d +1 second adders and a d-stage linear feedback shift register; the second multiplication circuit is used for determining the feedback of the d-stage linear feedback shift register;
the output end of the nth first adder is connected with the nth stage register of the r stages of linear feedback shift registers; the output end of the nth second adder is connected with the nth stage register of the d-stage linear feedback shift register;
the (d +1) th second adder is connected with the (d) th second adder, and the (d) th second adder is connected with the r-stage linear feedback shift register and the last stage register of the d-stage linear feedback shift register respectively; wherein r and d are both positive integers, and n is less than or equal to r or d + 1.
15. The encoder according to claim 14, wherein the input circuit is connected to an r-th first adder of the first encoding unit and a d + 1-th second adder of the second encoding unit;
the output circuit is connected with the input circuit through a second selector to form a first output path; the output circuit is also connected with a d second adder through the second selector to form a second output path;
the second selector determines whether the output circuit is the first output path or the second output path according to the clock timing.
16. A controller for a non-volatile memory, the controller comprising an encoder according to any one of claims 9 to 15, for performing BCH encoding on input information.
17. An electronic device characterized in that it comprises a non-volatile memory to which the controller of claim 16 is applied for storing data information.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611041572.XA CN106603085B (en) | 2016-11-21 | 2016-11-21 | Generating method and generating device for generating polynomial, encoder, controller and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611041572.XA CN106603085B (en) | 2016-11-21 | 2016-11-21 | Generating method and generating device for generating polynomial, encoder, controller and electronic equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106603085A CN106603085A (en) | 2017-04-26 |
| CN106603085B true CN106603085B (en) | 2020-04-14 |
Family
ID=58591911
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611041572.XA Active CN106603085B (en) | 2016-11-21 | 2016-11-21 | Generating method and generating device for generating polynomial, encoder, controller and electronic equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106603085B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114124111A (en) * | 2020-09-01 | 2022-03-01 | 华为技术有限公司 | Coding method and device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102272728A (en) * | 2008-12-31 | 2011-12-07 | 诺基亚公司 | Method, apparatus, and computer program product for polynomial-based data transformation and utilization |
| CN102761340A (en) * | 2012-08-10 | 2012-10-31 | 济南微晶电子技术有限公司 | Broadcast channel (BCH) parallel coding circuit |
| CN102811066A (en) * | 2012-07-17 | 2012-12-05 | 记忆科技(深圳)有限公司 | Syndrome calculating device and decoder |
| CN105553485A (en) * | 2015-12-08 | 2016-05-04 | 西安电子科技大学 | FPGA-based BCH encoding and decoding device and encoding and decoding method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8464141B2 (en) * | 2008-08-13 | 2013-06-11 | Infineon Technologies Ag | Programmable error correction capability for BCH codes |
-
2016
- 2016-11-21 CN CN201611041572.XA patent/CN106603085B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102272728A (en) * | 2008-12-31 | 2011-12-07 | 诺基亚公司 | Method, apparatus, and computer program product for polynomial-based data transformation and utilization |
| CN102811066A (en) * | 2012-07-17 | 2012-12-05 | 记忆科技(深圳)有限公司 | Syndrome calculating device and decoder |
| CN102761340A (en) * | 2012-08-10 | 2012-10-31 | 济南微晶电子技术有限公司 | Broadcast channel (BCH) parallel coding circuit |
| CN105553485A (en) * | 2015-12-08 | 2016-05-04 | 西安电子科技大学 | FPGA-based BCH encoding and decoding device and encoding and decoding method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106603085A (en) | 2017-04-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8954828B2 (en) | Memory controller | |
| KR101264061B1 (en) | Error correction mechanisms for flash memories | |
| US4928280A (en) | Fast processor for multi-bit error correction codes | |
| KR100953884B1 (en) | Raid system and galois field product computation method | |
| US8261176B2 (en) | Polynomial division | |
| CN1095122C (en) | Circuit for calculating error position polynomial at high speed | |
| KR20180059150A (en) | ECC encoder and encoding method capable of encoding during one clock cycle and memory controller having the ECC encoder | |
| EP3202045A1 (en) | Method and device for calculating a crc code in parallel | |
| US10903859B2 (en) | Error detection by means of group errors | |
| CN106603085B (en) | Generating method and generating device for generating polynomial, encoder, controller and electronic equipment | |
| CN110941505A (en) | Method for generating error correction circuit | |
| WO2015116184A1 (en) | Constant hamming weight coding | |
| US20080140740A1 (en) | Systems and methods for processing data sets in parallel | |
| KR20180059149A (en) | ECC decoder, memory controller including the ECC decoder, and ECC decoding method | |
| WO2019214266A1 (en) | Method and device for calculating crc code | |
| KR101923116B1 (en) | Apparatus for Encoding and Decoding in Distributed Storage System using Locally Repairable Codes and Method thereof | |
| EP0991196B1 (en) | Method of correcting lost data and circuit thereof | |
| RU2605672C1 (en) | Reconfigurable reed-solomon coder | |
| US9287898B2 (en) | Method and circuit for shortening latency of Chien'S search algorithm for BCH codewords | |
| WO2016181978A1 (en) | Matrix operation device, matrix operation method, and program | |
| JPH0476540B2 (en) | ||
| WO2008069465A1 (en) | Method and apparatus for checking correction errors using cyclic redundancy check | |
| TWI514778B (en) | Method and circuit for shortening latency of chien's search algorithm for bch codewords | |
| Lee et al. | Implementation of parallel BCH encoder employing tree-type systolic array architecture | |
| US11342939B2 (en) | Processing of data read from a memory |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20200110 Address after: 518000 District 652, district a, huameiju business center, Xinhu Road, Haiyu community, Xin'an street, Bao'an District, Shenzhen City, Guangdong Province Applicant after: Jian Rong semiconductor (Shenzhen) Co., Ltd. Address before: 518000 Guangdong city of Shenzhen province Nanshan District Gao Xin Road No. 013 Fu technology building B block 5 layer 505 Applicant before: Jian Rong semiconductor (Shenzhen) Co., Ltd. Applicant before: Jianrong Integrated Circuit Technology (Zhuhai) Co., Ltd. Applicant before: ZHUHAI HUANGRONG INTEGRATED CIRCUIT TECHNOLOGY CO., LTD. |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant |