CN106603085A - Method and device for generating BCH code generator polynomial, encoder, controller, and electronic device - Google Patents
Method and device for generating BCH code generator polynomial, encoder, controller, and electronic device Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
- H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
- H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes
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Abstract
The embodiment of the invention discloses a method and device for generating a BCH code generator polynomial, an encoder, a controller, and an electronic device. The encoder includes an input circuit for receiving input information, an output circuit for outputting encoded information, an encoding circuit for performing a BCH code encoding operation and comprising a first encoding unit for performing encoding operation based on a fixed polynomial and a second encoding unit for performing encoding operation based on a variable polynomial. The encoder constructs the generator polynomial by using the fixed polynomial and the variable polynomial so as to effectively reduce the occupied area of the pre-stored polynomials and the delay of a selection circuit while outputting a cyclic code with a variable error correction capability.
Description
Technical field
The present invention relates to cyclic code coding techniques field, more particularly to a kind of generation method of BCH code generator polynomial,
Generating means, encoder, Memory Controller Hub and electronic equipment.
Background technology
Bose-Chaudhuri Hocquenghem error correction codes are a kind of cyclic check codes for being generally used for correcting random error.By R.C.Bose,
D.K.Chaudhuri and A.Hocquenghem are proposed jointly.It is a kind of with strict Algebraic Structure, and error correcting capability is strong, structure
Make simple, coding is easier to the linear block codes of the features such as realizing.
Bose-Chaudhuri Hocquenghem error correction codes (hereinafter referred to as BCH code) belong to one kind of the cyclic code in linear block codes, and it can be very easy to
On circuit realize and be widely used.Used as a kind of cyclic code, BCH code can be by specific polynomial repressentation.Should
Multinomial is known as generator polynomial g (x) of BCH code again.For the BCH code with different design error correcting capabilities, its
Generator polynomial g (x) is also what is differed.
In actual use, it may be necessary to using various BCH codes with different error correcting capabilities.One can support
Or realize that the variable encoder of error correcting capability meets target requirement.As shown in figure 1, in Chinese patent, " a kind of parameter can
The BCH code encoder of change and decoder " (Patent document number：CN101567696A various differences are prestored there is provided one kind in)
The encoder of generator polynomial g (x) of error correcting capability.When in use, encoder can switch as needed the g (x) that uses from
And realize that the error correcting capability of encoder is variable.
In process of the present invention is realized, inventor has found that correlation technique has problems with：Above-mentioned error correcting capability is variable
In encoder, it is desirable to provide many circuit areas are storing and switch different generator polynomials g (x).
For example, in flash controller, the error correcting capability demand of different model flash is all different, it usually needs deposit in advance
At least 56 kinds different generator polynomials g (x) of storage.Finite field gf (2m) the item number r of generator polynomial g (x) of BCH code be equal to
Error correcting capability t is multiplied by information bit m (in flash applications, usual m is 17-72 for 14, t).Therefore, in general flash controller
In, the item number r of g (x) is 238～1008.
Can be seen that the above-mentioned 56 different g (x) of storage based on the computing of the above needs altogether the storage of 34888 bits empty
Between, such selection circuit area occupied is very big.Furthermore, it is contemplated that the quantity of generator polynomial g (x) is more, selection circuit
Delay also can be longer, and thus can cause the operating frequency of encoder reduces.
The content of the invention
The embodiment of the present invention is mainly solving the technical problems that provide a kind of generation method, the life of BCH code generator polynomial
Into device, encoder, Memory Controller Hub and electronic equipment, can solve the problem that and generator polynomial occupancy is prestored in prior art
Memory space is big, the problem that encoder operating frequency declines.
To solve above-mentioned technical problem, the embodiment of the present invention provides a kind of generator polynomial generation method of BCH code.The party
Method includes：It is determined that the first generator polynomial with predetermined maximum error correcting capability, first generator polynomial is several
The product of minimal polynomial；At least one fixed polynomial is divided in first generator polynomial, fixed polynomial is formed
Set；The fixed polynomial set includes one or more fixed polynomial；According to target error correcting capability, in the fixation
At least one fixed polynomial is selected in multinomial set；The target error correcting capability is less than or equal to maximum error correcting capability；Will tool
There is the second generator polynomial of target error correcting capability divided by the fixed polynomial chosen, the residue of acquisition is used as Variable polynomial.
Alternatively, the fixed polynomial set includes：The n fixed polynomial of P (0) to P (n)；Wherein, P (n) is the
One product for generating polynomial front m × (n+1) individual minimal polynomial；M is the minimal polynomial quantity that P (0) has；N is for just
Integer.
Alternatively, it is described to divide at least one fixed polynomial in first generator polynomial, specifically include：By institute
The minimal polynomial for stating the first generator polynomial is sequentially equally divided into k part minimal polynomial groups, and k is positive integer；Per portion most
Little multinomial group includes x or x-1 minimal polynomial；Using front x minimal polynomial as the first fixed polynomial；With institute
It is initial value to state the first fixed polynomial, performs the minimal polynomial quantity of recursive operation to the fixed polynomial closest to institute
Till stating the minimal polynomial quantity of the first generator polynomial；The recursive operation is：Calculate fixed polynomial minimum with latter x
Polynomial product is used as next fixed polynomial.
Alternatively, it is described according to target error correcting capability, select at least one to fix many in the fixed polynomial set
Item formula, specifically includes：Minimal polynomial quantity is chosen to be less than and closest to the fixed polynomial of target minimal polynomial quantity；
The target minimal polynomial quantity is the minimal polynomial quantity of the second generator polynomial with target error correcting capability.
To solve above-mentioned technical problem, the embodiment of the present invention provides a kind of generator polynomial generating means of BCH code.The life
Include into device：Maximum generator polynomial generation module is more for determining the with predetermined maximum error correcting capability first generation
Item formula, first generator polynomial is the product of several minimal polynomials；Fixed polynomial generation module, for described
At least one fixed polynomial is divided in first generator polynomial, fixed polynomial set is formed；The fixed polynomial set
Including one or more fixed polynomial；Fixed polynomial selecting module, for according to target error correcting capability, in the fixation
At least one fixed polynomial is selected in multinomial set；The target error correcting capability is less than or equal to maximum error correcting capability；And
Variable polynomial generation module, for the second generator polynomial with target error correcting capability is multinomial divided by the fixation chosen
Formula, the residue of acquisition is used as Variable polynomial.
Alternatively, the fixed polynomial set includes：The n fixed polynomial of P (0) to P (n)；Wherein, P (n) makes a living
Into the product of polynomial front m × (n+1) individual minimal polynomial；M is the minimal polynomial quantity that P (0) has；N is positive integer.
Alternatively, the fixed polynomial generation module specifically for：By the minimum multinomial of first generator polynomial
Formula is sequentially equally divided into k part minimal polynomial groups, and k is positive integer；Per portion minimal polynomial group comprising x or x-1
Minimal polynomial；Using front x minimal polynomial as the first fixed polynomial；With first fixed polynomial as initial value,
The minimal polynomial quantity for performing recursive operation to the fixed polynomial is more closest to the minimum of first generator polynomial
Till item formula quantity；The recursive operation is：The product that fixed polynomial is calculated with rear x minimal polynomial is used as next fixation
Multinomial.
Alternatively, the fixed polynomial selecting module specifically for：Minimal polynomial quantity is chosen to be less than and most connect
The fixed polynomial of close-target minimal polynomial quantity；The target minimal polynomial quantity is with target error correcting capability
The minimal polynomial quantity of two generator polynomials.
To solve above-mentioned technical problem, a kind of volume using generator polynomial as above is embodiments provided
Code device.The encoder includes：The input circuit of receives input information；The output circuit and execution BCH code of output coding information
The coding circuit of encoding operation；
The coding circuit includes：First coding unit, for performing the encoding operation and the based on fixed polynomial
Two coding units, for performing based on the encoding operation of Variable polynomial.
Alternatively, the encoder also includes：Store the storage circuit of the fixed polynomial set；Select the fixation
One or more fixed polynomial in multinomial set, there is provided to the first selector of first coding unit.
Alternatively, the storage circuit is stored with the n fixed polynomial of P (0) to P (n)；P (n) is that the first generation is multinomial
The product of the front m of formula × (n+1) individual minimal polynomial；M is the minimal polynomial quantity that P (0) has；N is positive integer.
Alternatively, the fixed polynomial that the first selector is selected is that minimal polynomial quantity is less than and closest to mesh
The fixed polynomial of mark minimal polynomial quantity；The target minimal polynomial quantity is the with target error correcting capability second life
Into polynomial minimal polynomial quantity.
Alternatively, the encoder also includes polynomial computation unit；The polynomial computation unit is used for according to described
The fixed polynomial of the first coding unit is supplied to, the Variable polynomial is calculated and is supplied to second coding unit.
Alternatively, first coding unit includes：Perform the first mlultiplying circuit, the r of the multiplying of fixed polynomial
Individual first adder and r level linear feedback shift registers；First mlultiplying circuit is to determine the r levels linear feedback
The feedback of shift register；
Second coding unit includes：Perform the second mlultiplying circuit, the d+1 individual second of the multiplying of Variable polynomial
Adder and d level linear feedback shift registers；Second mlultiplying circuit is posted to determine the d levels linear feedback shift
The feedback of storage；
The output end of n-th first adder is connected with n-th grade of register of the r levels linear feedback shift register；
The output end of n-th second adder is connected with n-th grade of register of the d levels linear feedback shift register；
The d+1 second adder is connected with d-th second adder, d-th second adder with it is linear with r levels respectively
The afterbody register connection of feedback shift register and d level linear feedback shift registers；Wherein, r and d is just whole
Number, n is less than or equal to r or d+1.
Alternatively, r-th first adder and the second coding unit of the input circuit and the first coding unit
The d+1 second adder connection；
The output circuit is connected by second selector with the input circuit, forms the first outgoing route；It is described defeated
Go out circuit to be also connected with d-th second adder by the second selector, form the second outgoing route；
The second selector determines output circuit for the first outgoing route or the second outgoing route according to clocked sequential.
To solve above-mentioned technical problem, a kind of controller of the nonvolatile memory is embodiments provided.
The storage control includes encoder as above, and to input information Bose-Chaudhuri-Hocquenghem Code is performed.
To solve above-mentioned technical problem, a kind of electronic equipment is embodiments provided.The electronic equipment includes should
With the nonvolatile memory of controller as above, to data storage information.
The generator polynomial generation method provided in the embodiment of the present invention, generator polynomial is split according to associative law of multiplication
For some fixed polynomials and the form of Variable polynomial.When needing to realize different error correcting capabilities, can be by selecting not
With fixed polynomial and the Variable polynomial and mode that is combined constructs corresponding generator polynomial, it is not necessary to independent deposits
Store up each generator polynomial, reduce the multinomial quantity for prestoring, so as to reduce well storage circuit occupancy area with
And shorten the time delay of selection circuit.
Description of the drawings
One or more embodiments are illustrative by the picture in corresponding accompanying drawing, these exemplary theorys
Bright not constitute the restriction to embodiment, the element with same reference numbers label is expressed as similar element in accompanying drawing, removes
Non- to have especially statement, composition is not limited the figure in accompanying drawing.
Fig. 1 is the coding circuit figure of the variable BCH of output error correcting capability of prior art；
Fig. 2 is the method flow diagram in construction fixed polynomial set stage provided in an embodiment of the present invention；
Fig. 3 is the method flow diagram in calculating Variable polynomial stage provided in an embodiment of the present invention；
Fig. 4 is the coding circuit figure that Bose-Chaudhuri-Hocquenghem Code is realized according to generator polynomial provided in an embodiment of the present invention；
Fig. 5 is the functional block diagram of the variable Bose-Chaudhuri-Hocquenghem Code device of error correcting capability provided in an embodiment of the present invention；
Fig. 6 is the circuit diagram of the variable Bose-Chaudhuri-Hocquenghem Code device of error correcting capability provided in an embodiment of the present invention；
Fig. 7 is the combination diagram of the generator polynomial that error correcting capability provided in an embodiment of the present invention is 17；
Fig. 8 is the combination diagram of the generator polynomial that error correcting capability provided in an embodiment of the present invention is 11；
Fig. 9 for generator polynomial that error correcting capability provided in an embodiment of the present invention is 4 combination diagram；
Figure 10 for generator polynomial that the error correcting capability that another embodiment of the present invention is provided is 27 combination diagram；
Figure 11 for generator polynomial that the error correcting capability that another embodiment of the present invention is provided is 6 combination diagram；
Figure 12 is the schematic device of the generating means of generator polynomial provided in an embodiment of the present invention.
Specific embodiment
In order that the objects, technical solutions and advantages of the present invention become more apparent, it is right below in conjunction with drawings and Examples
The present invention is further elaborated.It should be appreciated that specific embodiment described herein is only to explain the present invention, not
For limiting the present invention.
The error correcting capability of error correcting code is the more important parameter of error correcting code one of which.Usual, first structure during use
An error correcting code is produced, its minimum range is then calculated.And in BCH code construction process provided in an embodiment of the present invention, then it is first
First consider that the BCH code is desired with the number (i.e. error correcting capability) of error correction, it is then (i.e. repairable according to the target error correcting capability
Random error number) constructing corresponding BCH code.
According to the characteristics of cyclic code, for (n, k) cyclic code (n is total code length, and k is information bit length), all of code word
Multinomial is all the multiple of certain n-k order polynomials g (x), and g (x) is xn+ 1 factor.Thus, it is known that the highest of g (x)
Secondary term coefficient is 1.
For arbitrary information sequence m=(m1, m2..., mk) can be defined as：
M (x)=m1xk-1+m2xk-2+...+mk-1x+mk
Discussion according to more than, codeword polynome c (x) of the corresponding information sequence m in information sequence can be by c
X ()=m (x) g (x) is given.Wherein, g (x) is just referred to as the generator polynomial of cyclic code.Obvious, determining message polynomial
In the case of m (x), the codeword polynome can be obtained by generator polynomial, realize the coding to information.
For example, for one, (7,4) for cyclic code, its generator polynomial can be x3+x2+ 1 or x3+x+1.According to
Above description, it can be seen that to realize that cyclic code is encoded, the generator polynomial for determining cyclic code is its most important target.
After generator polynomial g (x) is determined, corresponding system circulation code can be accordingly generated.For example, in finite field gf
(2m) on, the coding polynomial of the system form coding of BCH code can be defined by formula (1)：
C (x)=m (x) xn-k+Rem(m(x)xn-k,g(x)) (1)
Wherein, m (x) is input information, and g (x) is generator polynomial, and Rem (a, b) represents the residue of a/b, and n is total for BCH's
Code length, k be information bit length, m (x) xn-kM (x) is moved to left (n-k) position by expression.
Assume that input message is (1001), using generator polynomial g (x)=x3+ x+1 codings (7,4) circulates the tool of code word
Body method is as follows：
1) the message multinomial of (1001) is：M (x)=m3x3+m2x2+m1x+m0=x3+ 1,
2)m(x)xn-kFor x6+x3
3) it is c (x)=x to circulate code polynomial c (x)6+x3+x2+x.Therefore, the circulation code word for obtaining is (1001110), is wrapped
Include information bit and redundant digit.
As can be seen that in cyclic code coding, generator polynomial is related to the error correcting capability of code word.Therefore, determining
After being desirable to the error correction number (the random independent mistake that can be corrected) realized, for BCH code, it may be determined that can
(generator polynomial of hereinafter referred to as error correcting capability t) is to correct t random independent mistake：
G (x)=LCM { m1(x)m2(x)m3(x)...m2t-1(x)m2t(x)} (2)
Wherein, LCM represents minimal common multiple, miFor minimal polynomial.Minimal polynomial is irreducible, in finite field gf
(2m) in, with ai(power of a is represented in GF (2m) in any nonzero element) be root minimum number of times multinomial.Based on binary system
The known properties of BCH code, the minimal polynomial of even order terms is inevitable identical with the minimal polynomial of certain odd item.Therefore, formula
(2) generator polynomial for representing can be with abbreviation：
G (x)=LCM { m1(x)m3(x)...m2t-3(x)m2t-1(x)}
The close phase of minimal polynomial quantity of error correcting capability t and generator polynomial g (x) is can be seen that with reference to formula (2)
Close, the minimal polynomial that generator polynomial g (x) is calculated is more, and error correcting capability t is bigger.
In generator polynomial g (x), it is understood that there may be identical minimal polynomial mi(x), such as m1(x)m3X () is identical, can be with
Remove the minimal polynomial (only retaining one of them) for repeating.It is minimum many identical in g (x) is removed as shown in formula (1)
Xiang Shihou, the minimal common multiple of remaining minimal polynomial is the product of minimal polynomial.Thus, g (x) can be by multiple mutual
(easy for statement, the generator polynomial in following examples is with different for the product representation of the minimal polynomial for differing
Minimal polynomial represent).
According to associative law of multiplication, g (x) can be divided into the product of arbitrary several groups of minimal polynomials, for example, make g (x)
={ m1(x)m3(x)}{m5(x)m2t-3(x)m2t-1(x)}.It will be appreciated by persons skilled in the art that such divide or divide
Tearing open need not meet any restrictive condition and can arbitrarily carry out, and can both be divided into several groups and have equal number most
Little polynomial product, it is also possible to be divided into the product of the minimal polynomial with varying number.It is easy for statement, use " most
Little multinomial group " is representing the product comprising one or more minimal polynomial.The product of each minimal polynomial group is g
(x)。
The property of the generator polynomial of BCH code as described above (i.e. can be by being divided into arbitrary minimal polynomial
The product representation of group), during coding is realized, corresponding minimal polynomial group can be set and given according to actual demand
To store (such as by the minimal polynomial group of part as fixed polynomial set).
When needing to adjust error correcting capability t, select the satisfactory minimal polynomial group for prestoring and be combined, obtain
Must have certain amount of minimal polynomial (i.e. the generator polynomial of error correcting capability t) and accordingly output with predetermined design code distance
BCH code.Here, using term as " fixed polynomial set " to represent prestore a series of constant minimum multinomial
Formula group.Wherein, each minimal polynomial group is a fixed polynomial.
It is above-mentioned to be combined with multiple minimal polynomial groups, so as to the mode for realizing generator polynomial can be reduced effectively
The data volume that needs are prestored.For example, in order to export BCH code of error correcting capability t between 17-72, using original independence
The method of storage generator polynomial needs storage all possible generator polynomials (60 kinds).And adopt above-mentioned minimal polynomial group
The mode being combined, then may only need to store 5 kinds, 3 kinds or less fixed polynomial.
In certain embodiments, it is the quantity of the minimal polynomial group for further reducing prestoring, there is provided more flexible
Combination or simplification realize the design of circuit, except above-mentioned minimal polynomial group is set to into fixed polynomial storage
Outward, can be with as Variable polynomial.The Variable polynomial is a multinomial obtained by logical calculated, with fixation
Multinomial is compared, with more preferable flexibility.For example, can be many with fixation by the generator polynomial with target error correcting capability t
, used as Variable polynomial, such mode can be in the case of the fixed polynomial of storage equal number, energy for the residue of item formula
It is enough that more generator polynomials with different error correcting capabilities t are provided.
Such, Variable polynomial is determined according to the fixed polynomial for using.Also namely be based on Variable polynomial with
The product of fixed polynomial is limited as the generator polynomial with target error correcting capability and calculates acquisition.
It should be noted that increasing the Variable polynomial for arranging can bring extra computing consumption, should be in computing consumption
Suitable balance is obtained between the amount of storage of amount and storage fixed polynomial.
Hereinafter the generator polynomial with specific error correcting capability t is constituted with a fixed polynomial and a Variable polynomial
As a example by stated in detail：
The maximum error correcting capability that assuming the encoder can realize is Tmax.In finite field gf (2m) in, correspondence maximum error correction
Ability TmaxGenerator polynomial by TmaxThe product representation of individual mutually different minimal polynomial.Whole method includes that construction is fixed
Multinomial set and calculating two stages of Variable polynomial.
1) for the construction fixed polynomial set stage, as shown in Fig. 2 the step can include：
201：The minimal polynomial is sequentially equally divided into into k minimal polynomial group, is wrapped in each minimal polynomial group
The minimal polynomial number for containing is x or x-1 is (easy for statement, it can be assumed that the minimal polynomial of k-th minimal polynomial group
Number is x-1, and the minimal polynomial number of remaining minimal polynomial group is for x).
202：(i.e. front x minimal polynomial is stored using first minimal polynomial group as the first fixed polynomial P (0)
Product).
203：Using the product of second minimal polynomial group and the first fixed polynomial P (0) as the second fixed polynomial P
(1) and store.
For next fixed polynomial, step 203 (i.e. the strategy of recursive operation) is repeated.Can summarize and draw,
For n-th minimal polynomial group, its product with previous fixed polynomial P (n-1) is used as fixed polynomial P (n)
Storage.
204：Repeat, until -2 minimal polynomial groups of kth.It can be with fixed polynomial P of kth -3 (k-3) phase
Take advantage of, obtain fixed polynomial P (k-2).Wherein, the minimal polynomial number of fixed polynomial P (k-2) is x (k-2+1).
Above-mentioned steps 203 show the recursive operation process during construction fixed polynomial, first based on each
Fixed polynomial generate next fixed polynomial.The stop condition of recurrence be until penultimate minimal polynomial group,
Till generating fixed polynomial P (k-2).
In this way, multiple minimal polynomial quantity fixed polynomial incremented by successively can be generated, can will be upper
The multiple fixed polynomials stated are stored as a set.
2) for the Variable polynomial stage is calculated, as shown in figure 3, the stage may include steps of：
301：The target error correcting capability for assuming to need the BCH code for generating is that (t is less than or equal to T to tmax).As described above,
The target minimal polynomial quantity that can determine the generator polynomial with target error correcting capability should be t.
302：In the fixed polynomial of above-mentioned storage, select minimal polynomial quantity closest and the fixation less than t
Fixed polynomial part of multinomial P (n) as generator polynomial.In this case, fixed polynomial is minimum with target
Difference between multinomial quantity is t-x (n+1).
303：By online logical operation, the product of the individual minimal polynomial of remaining t-x (n+1) is calculated, as variable many
Item formula.It should be noted that according to the description of step 204, it may be determined that calculative maximum minimal polynomial quantity is
X-1.
Step 303 is calculated after finishing, and Variable polynomial and fixed polynomial are determined.Therefore, with accordingly entangling
The generator polynomial of wrong ability t can also uniquely determine, in being applied to encoder, BCH of the output with target error correcting capability t
Code.
In the generating process of the generator polynomial of the present embodiment, it is only necessary to which storing k-1 fixed polynomial i.e. can group
Close and obtain error correcting capability in 0-TmaxBetween change generator polynomial, greatly reduce need storage data volume.
On the other hand, in the above-described embodiments, encoder is realized being carried required for the variable generator polynomial of the error correcting capability
For resource (be presented as realize circuit take area) be：The amount of storage and calculating Variable polynomial of storage fixed polynomial
Amount of calculation.
For fixed Tmax, but increasing the value of k can increase amount of storage can reduce amount of calculation, reduce k values then phase
Instead, it is a function that there is flex point.Therefore, those skilled in the art can pass through experiment repeatedly or suitable optimization
Algorithm obtains optimum k values (at flex point) so that realize that the area that circuit takes is minimum.
As described above, these are only the reality that generator polynomial is divided into a fixed polynomial and a Variable polynomial
Apply example.In actual application, the fixed polynomial of two or more can also be divided into.Specific partition strategy
Can be adjusted according to actual conditions, be can be any combination for each minimal polynomial in generator polynomial
Or adjust and there is no any restriction.Such is any of elementary cell based on minimal polynomial or minimal polynomial group
Partition strategy belongs to the scope of the present invention.
The embodiment of the present invention additionally provides a kind of generator polynomial generating means to perform said method step.As schemed
Shown in 12, the device includes：Maximum generator polynomial generation module 10, the choosing of fixed polynomial generation module 20, fixed polynomial
Select module 30 and Variable polynomial generation module 40.
Wherein, the maximum generator polynomial generation module 10 is used to determine with predetermined maximum error correcting capability first
Generator polynomial, first generator polynomial is the product of several minimal polynomials.The fixed polynomial generation module
20 are used to divide at least one fixed polynomial in first generator polynomial, form fixed polynomial set；It is described solid
Multinomial set is determined including one or more fixed polynomial.The fixed polynomial selecting module 30 is used to be entangled according to target
Wrong ability, in the fixed polynomial set at least one fixed polynomial is selected；The target error correcting capability is less than or equal to
Maximum error correcting capability.The Variable polynomial generation module 40 is used to remove the second generator polynomial with target error correcting capability
With the fixed polynomial chosen, the residue of acquisition is used as Variable polynomial.
Alternatively, the maximum generator polynomial generation module 10 of the embodiment of the present invention, fixed polynomial generation module 20, solid
Determine multinomial selecting module 30 and Variable polynomial generation module 40 can also further to perform said method embodiment
Described in arbitrary concrete step or multiple steps between combination, for example, fixed polynomial generation module 20 will be fixed
Multinomial is divided into the n fixed polynomial of P (0) to P (n).Wherein, P (n) is more to generate the individual minimums of polynomial front m × (n+1)
The product of item formula；M is the minimal polynomial quantity that P (0) has；N is positive integer；Or, fixed polynomial selecting module 30 is selected
Middle minimal polynomial quantity is less than and closest to the minimal polynomial quantity of the generator polynomial with target error correcting capability
Fixed polynomial.Because the generating means of the embodiment of the present invention are conceived with generation method based on identical application, therefore, method reality
The corresponding contents or technical scheme applied in example are equally applicable to device embodiment, no longer describe in detail herein.
Multiple different fixed polynomials and Variable polynomial can be generated by above-mentioned generation method and generating means,
And accordingly composition has the generator polynomial of specific error correcting capability (i.e. minimal polynomial quantity).Data in step are (as fixed
Multinomial) data storage device of any suitable type can be stored in, such as local storage medium or online storage
Medium.
Professional should further appreciate that, with reference to each example of the embodiments described herein description
Unit and algorithm steps, can with electronic hardware, computer software or the two be implemented in combination in, it is hard in order to clearly demonstrate
The interchangeability of part and software, according to function has generally described the composition and step of each example in the above description.
These functions are performed with hardware or software mode actually, depending on the application-specific and design constraint of technical scheme.
Professional and technical personnel can use different methods to realize described function to each specific application, but this realization
It is not considered that exceeding scope of the present application.Described computer software can be stored in computer read/write memory medium, the journey
Sequence is upon execution, it may include such as the flow process of the embodiment of above-mentioned each method.Wherein, described storage medium can for magnetic disc, CD,
Read-only memory or random access memory etc..
Usual, after determining generator polynomial, it is possible to use the digital circuit based on linear feedback shift register
The encoder of cyclic code.For example, generator polynomial g (x) of BCH code is calculated according to error correcting capability t of design, and uses length
For the linear feedback shift register (LFSR) of r, it determines feedback, all deposits of LFSR according to generator polynomial g (x)
Device initial value is 0.
With the input of data, the highest order of input data and LFSR is performed into XOR, until the input number of k bits
According to being fully completed XOR.Now, the value in LFSR is the redundant code of BCH code, long with the input data of k bits composition one
Spend the system form code word for k+r bits.
Certainly, in actual use, it is also possible to realize BCH code using other suitable digital circuits or encoder
Coding.
Describe in detail below in conjunction with the circuit diagram shown in Fig. 4 and realize that BCH is compiled based on the mlultiplying circuit of multi-level register
The general principle of code.In the circuit diagram shown in Fig. 4, it is possible to use the linear shift register with feedback is realized.The base
This encoder circuit can include multistage linear shift register, multiplier (generator polynomial g (x) mlultiplying circuit) and add
Musical instruments used in a Buddhist or Taoist mass.
Assume that corresponding generator polynomial g (x) of mlultiplying circuit is：
G (x)=1+g1x+g2x2+...+gn-k-1xn-k-1+xn-k
The 1st to k clock along when, gate circuit S2 be in position 2, now while output end output information position, meter
(each " 1 " removes from register and enters in feedback line, realizes by except in formula to calculate residue (the Rem items in formula 1)-redundant digit
Deduct except formula).
Kth+1 to n clock along when, gate circuit S2 be in position 1, simultaneously switch off feedback line (gate circuit S1 be in position
Put 1), export redundant digit.
Based on the realize principle similar with Fig. 4, the embodiment of the present invention additionally provides a kind of application as above generation method reality
The generator polynomial of the example offer Bose-Chaudhuri-Hocquenghem Code device variable so as to realize error correcting capability is provided.
Fig. 5 is the functional block diagram of Bose-Chaudhuri-Hocquenghem Code device provided in an embodiment of the present invention.As shown in figure 5, its main body includes：First
Coding unit 100, the second coding unit 200 and the part of polynomial computation unit 300 3.
In the present embodiment, the generator polynomial building method for being provided based on above-described embodiment, polynomial computation unit 300
Calculate specific Variable polynomial and provide it to the second coding unit 200 and by the second coding unit 200 perform it is above-mentioned can
Become polynomial computing.First coding unit 100 selects the fixed polynomial for prestoring to perform then according to actual conditions
Multiplying.
The various fixed polynomials to be formed are divided by above-described embodiment can be stored in various suitable, deposit with data
In the storage circuit of storage function.The storage circuit can be used as a portion of the first coding unit 100, it is also possible to used as only
Vertical part is arranged on outside the first coding unit.
Above-mentioned polynomial computation unit 300 can be realized by the Variable polynomial generation module 400 of above-mentioned generating means.Its
Can be realized by software approach, it would however also be possible to employ independent hardware circuit is realized, used as one of function mould of encoder
Block independent is arranged on outside encoder.
That is, encoder can only have the first coding unit and the second coding unit, and be held according to the multinomial of input
The corresponding logical operation of row further exports operation result.The encoder can add or economization some other different modules
(storage circuit described above, polynomial computation unit etc.).
The coding unit 200 of first coding unit 100 and second specifically can be using any suitable, according to multinomial
The digital circuit for generating corresponding coding information realized, such as the above-mentioned implementation based on LFSR.
In the first coding unit 100, fixed polynomial can be considered as generator polynomial, generate corresponding coding letter
Breath.And in the second coding unit 200, Variable polynomial is considered as into generator polynomial.Therefore, compile by comprehensive first and second
The computing output result of code unit, it is possible to obtain the generator polynomial being made up of fixed polynomial and Variable polynomial product
The system coding of BCH code.
It should be noted that generator polynomial to be divided into two groups or more minimal polynomial groups as fixation at some
In the case of polynomial, reality can be given by setting up the first coding unit of respective amount in encoder as shown in Figure 5
It is existing.In certain embodiments, further generator polynomial can also be divided into into more minimal polynomial groups and is regarded as
Fixed polynomial is so as to replacing above-mentioned Variable polynomial.
In these have the embodiment of the encoder of greater number of first coding unit, due to increasing extra fixation
Polynomial code unit (i.e. the first coding unit) can cause logical construction complicated and operation frequency decline.And, in reality
In the operation of border, in order to accelerate coding, it will usually while concatenating multiple coding units carries out parallel computation, can so cause encoder
Operation frequency further decline.Therefore, it is a kind of strategy do not recommended to arrange more first coding units, and it is for coding
The negative effect of efficiency is much larger than its positive effect.
Alternatively, as shown in fig. 6, the first coding unit 100 can include：For storing the storage circuit of fixed polynomial
(not shown), first selector 120, the first multiplier 130, multi-level register 140 and first adder 150.
Analogously, second coding unit 200 can include：Second multiplier 230, the second multi-level register 240
And second adder 250.
Above-mentioned selector 120, the first multiplier 130 constitute the mlultiplying circuit of fixed polynomial, and first adder 150 sets
Put between multi-level register.Its operation principle is similar with the generator polynomial mlultiplying circuit shown in Fig. 4.Distinguish,
The fixed polynomial device for selection generated in the storage circuit storage said method embodiment is selected.The selector 120
Error correcting capability t of output can be actually needed according to encoder, suitable fixed polynomial is selected from storage circuit to hold
The multiplying of row and input data.
For the second coding unit, its Variable polynomial is provided by polynomial computation unit 300, the second multiplier 240,
Principle is similar with realizing shown in Fig. 4 for the concrete logical operation process of the second multi-level register 240 and second adder 250
Seemingly.In the second coding unit, on the one hand, it is provided to the multinomial for performing multiplication calculating by polynomial computation unit 300
(i.e. Variable polynomial).On the other hand, it has the second adder 250 of more than the series than multi-level register, to whole
(i.e. last adder output of the first coding unit connects to close the output information of the first coding unit and the second coding unit
Enter in the second adder).
In actual coding operating process, according to error correcting capability t, after determining fixed polynomial and Variable polynomial,
Respectively as the first coding unit and the feedback of the second coding unit, by the encoder shown in Fig. 6, perform following steps so as to
Realize the BCH code encoding operation with target error correcting capability t.
Wherein, as shown in fig. 6, register is multi-level register, it is connected with an adder after each register, finally
The register of one adder also by feedback line as the first order connects, input information.For the input circuit of input information
It is connected with r-th first adder of the first coding unit and the d+1 second adder of the second coding unit.To defeated
The output circuit for going out information is then connected by second selector with the input circuit.It is similar with the principle shown in Fig. 4, selector
Switching selects to export redundant digit through the first outgoing route output information position or through the second outgoing route.
The specific switching mode of selector is：First, output source is switched to into input, and is coupled with the first coding
In r-th first adder and the d+1 second adder of the coding unit 200 of unit 100 and second, each clock is along renewal
Once, output end output information position (register series is related to polynomial item number).
Then, after full detail is input into and finishes, output source is switched to d-th with the second coding unit 200
In second adder 250 (in second second adder 250 i.e. from right side).D-th second adder 250 is coupled with
The d+1 second adder (i.e. of the rightmost side of r-th first adder of the first coding unit and the second coding unit
Two adders), each clock edge updates once, so as to export redundant digit in output end.
Finally, until the redundant digit output of whole is completed, Bose-Chaudhuri-Hocquenghem Code is completed.
Further to state the variable coding method of error correcting capability provided in an embodiment of the present invention and its code device, carry
For following some examples.
For example, it is assumed that the maximum error correcting capability of the output of code device support is Tmax=17, corresponding generator polynomial by
The product representation of 17 different minimal polynomials：
G (x)=m1(x)m3(x)...m31(x)m33(x)
If k values are 3 (being divided into 3 parts), two fixed polynomials can be divided into
P (0)=m1(x)m3(x)...m9(x)m11(x)
P (1)=m1(x)m3(x)...m21(x)m23(x)
As shown in fig. 7, if desired exporting the BCH code that error correcting capability t is 17, selector can select fixed polynomial P
(1), for the feedback link of the first coding unit 100, and it is multinomial to calculate remaining 5 minimums by polynomial computation unit
The product of formula, as Variable polynomial S (x), for the feedback link of the second coding unit 200.
As shown in figure 8, if desired exporting the BCH code that error correcting capability t is 11, selector selects closest and many less than target
Fixed polynomial P (0) of item formula quantity (equal with error correcting capability t), for the feedback link of the first coding unit 100, and
The product of remaining 5 minimal polynomials is calculated by polynomial computation unit, it is single for the second coding as Variable polynomial
The feedback link of unit 200.
As shown in figure 9, if desired exporting the BCH code that error correcting capability t is 4, (now not disclosure satisfy that in storage circuit will
The fixed polynomial asked) fixed polynomial can be set to complete zero, for the feedback link of the first coding unit 100, and
The product of 4 minimal polynomials for needing is calculated by polynomial computation unit, it is single for the second coding as Variable polynomial
The feedback link of unit 200.
In further embodiments, if the maximum error correcting capability of the output of code device support is Tmax=30, corresponding life
Into multinomial by 30 different minimal polynomials product representation：
G (x)=m1(x)m3(x)...m57(x)m59(x)
If generator polynomial is divided into into 5 fixed polynomials and a Variable polynomial.Wherein, including it is following 5 it is solid
Determine multinomial：
P (0)=m1(x)m3(x)...m9(x)m11(x)
P (1)=m1(x)m3(x)...m21(x)m23(x)
P (2)=m1(x)m3(x)...m33(x)m35(x)
P (3)=m1(x)m3(x)...m45(x)m47(x)
P (4)=m1(x)m3(x)...m57(x)m59(x)
As shown in Figure 10, if the BCH code that error correcting capability t is 27 need to be exported, selector can select the 4th fixed polynomial p
(3) for the feedback link of the first coding unit 100, and it is multinomial to calculate remaining 3 minimums by polynomial computation unit
Formula m49(x)m51(x)m53Product s (x) of (x), for the feedback link of the second coding unit 200.
As shown in figure 11, if error correcting capability need to be exported for the BCH code that t is 6, selector can select the 1st fixed polynomial p
(0) for the feedback link of the first coding unit 100, and Variable polynomial is set to into complete zero, for the second coding unit
200 feedback link.
Such set-up mode, it is only necessary to store 5 fixed polynomials and polynomial computation unit max calculation is multinomial
Formula quantity is less than or equal to 5, you can combination obtains the generator polynomial that maximum error correcting capability is 30.
Using the encoder of the above under the ability variable with error correcting capability, need storage fixed polynomial quantity compared with
It is few, during the occasion with different error correcting capability demands can be conveniently applied to, for example, in existing non-volatile memory medium
In the controller of (such as flash memory), the error correcting capability demand of the flash memory of different model is differed, and using the encoder of the above BCH is performed
Code coding disclosure satisfy that the demand of these flash controllers, and effectively reduce circuit consumption, improve the work of encoder
Working frequency.
The encoder of the embodiment of the present invention can apply in any suitable BCH code encoding device, be also used as be
BCH code encoding function module in system, combination or it is independent be applied in any suitable system, for example, realize it is higher can
The property depend on is needed in the flash memory device for using BCH code to read and write data, or the electronic equipment of flash memory device as other application,
Such as smart mobile phone, PC, wearable device, laptop computer.Nonvolatile memory as the electronic apparatus application,
To the data message for storing various suitable types, such as computer executable program.
Embodiments of the present invention are the foregoing is only, the scope of the claims of the present invention is not thereby limited, it is every using this
Equivalent structure or equivalent flow conversion that description of the invention and accompanying drawing content are made, or directly or indirectly it is used in other correlations
Technical field, is included within the scope of the present invention.
Claims (17)
1. the generator polynomial generation method of a kind of BCH code, it is characterised in that include：
It is determined that the first generator polynomial with predetermined maximum error correcting capability, first generator polynomial is that several are minimum
Polynomial product；
At least one fixed polynomial is divided in first generator polynomial, fixed polynomial set is formed；The fixation
Multinomial set includes one or more fixed polynomial；
According to target error correcting capability, in the fixed polynomial set at least one fixed polynomial is selected；The target is entangled
Wrong ability is less than or equal to maximum error correcting capability；
By the second generator polynomial with target error correcting capability divided by the fixed polynomial chosen, the residue of acquisition is used as variable
Multinomial.
2. method according to claim 1, it is characterised in that the fixed polynomial set includes：The n of P (0) to P (n)
Individual fixed polynomial；Wherein, P (n) is the product of front m × (n+1) individual minimal polynomial of the first generator polynomial；M is P (0)
The minimal polynomial quantity having；N is positive integer.
3. method according to claim 2, it is characterised in that described to divide at least in first generator polynomial
Individual fixed polynomial, specifically includes：
The minimal polynomial of first generator polynomial is sequentially equally divided into into k part minimal polynomial groups, k is positive integer；
Per portion minimal polynomial group comprising x or x-1 minimal polynomial；
Using front x minimal polynomial as the first fixed polynomial；
With first fixed polynomial as initial value, the minimal polynomial quantity of recursive operation to the fixed polynomial is performed
Till the minimal polynomial quantity of closest first generator polynomial；
The recursive operation is：The product that fixed polynomial is calculated with rear x minimal polynomial is used as next fixed polynomial.
4. method according to claim 2, it is characterised in that described according to target error correcting capability, it is multinomial in the fixation
At least one fixed polynomial is selected in formula set, is specifically included：
Minimal polynomial quantity is chosen to be less than and closest to the fixed polynomial of target minimal polynomial quantity；The target is most
Little multinomial quantity is the minimal polynomial quantity of the second generator polynomial with target error correcting capability.
5. generator polynomial generating means of a kind of BCH code, it is characterised in that described device includes：
Maximum generator polynomial generation module, for determining the first generator polynomial with predetermined maximum error correcting capability, institute
State the product that the first generator polynomial is several minimal polynomials；
Fixed polynomial generation module, for dividing at least one fixed polynomial in first generator polynomial, forms
Fixed polynomial set；The fixed polynomial set includes one or more fixed polynomial；
Fixed polynomial selecting module, for according to target error correcting capability, in the fixed polynomial set at least one being selected
Individual fixed polynomial；The target error correcting capability is less than or equal to maximum error correcting capability；
Variable polynomial generation module, for the second generator polynomial with target error correcting capability is more divided by the fixation chosen
Item formula, the residue of acquisition is used as Variable polynomial.
6. device according to claim 5, it is characterised in that the fixed polynomial set includes：The n of P (0) to P (n)
Individual fixed polynomial；Wherein, P (n) is the product for generating polynomial front m × (n+1) individual minimal polynomial；M has for P (0)
Minimal polynomial quantity；N is positive integer.
7. device according to claim 6, it is characterised in that the fixed polynomial generation module specifically for：
The minimal polynomial of first generator polynomial is sequentially equally divided into into k part minimal polynomial groups, k is positive integer；
Per portion minimal polynomial group comprising x or x-1 minimal polynomial；
Using front x minimal polynomial as the first fixed polynomial；
With first fixed polynomial as initial value, the minimal polynomial quantity of recursive operation to the fixed polynomial is performed
Till the minimal polynomial quantity of closest first generator polynomial；
The recursive operation is：The product that fixed polynomial is calculated with rear x minimal polynomial is used as next fixed polynomial.
8. device according to claim 6, it is characterised in that the fixed polynomial selecting module specifically for：
Minimal polynomial quantity is chosen to be less than and closest to the fixed polynomial of target minimal polynomial quantity；The target is most
Little multinomial quantity is the minimal polynomial quantity of the second generator polynomial with target error correcting capability.
9. the encoder of the generator polynomial that a kind of application the method for claim 1 is generated, it is characterised in that include：
The input circuit of receives input information；
The output circuit of output coding information；
Perform the coding circuit of BCH code encoding operation；The coding circuit includes：First coding unit, for performing based on solid
Fixed polynomial encoding operation and the second coding unit, for performing based on the encoding operation of Variable polynomial.
10. encoder according to claim 9, it is characterised in that the encoder also includes：
Store the storage circuit of the fixed polynomial set；
Select one or more fixed polynomial in the fixed polynomial set, there is provided to first coding unit
First selector.
11. encoders according to claim 10, it is characterised in that the storage circuit is stored with the n of P (0) to P (n)
Individual fixed polynomial；
P (n) is the product of front m × (n+1) individual minimal polynomial of the first generator polynomial；M be P (0) have it is minimum multinomial
Formula quantity；N is positive integer.
12. encoders according to claim 11, it is characterised in that the fixed polynomial that the first selector is selected is
Minimal polynomial quantity is less than and closest to the fixed polynomial of target minimal polynomial quantity；The target minimal polynomial
Quantity is the minimal polynomial quantity of the second generator polynomial with target error correcting capability.
13. encoders according to claim 10, it is characterised in that the encoder also includes polynomial computation unit；
The polynomial computation unit is used for according to the fixed polynomial for being supplied to the first coding unit, calculates described variable multinomial
Formula is simultaneously supplied to second coding unit.
14. encoders according to claim 9, it is characterised in that first coding unit includes：Perform fixation multinomial
First mlultiplying circuit of the multiplying of formula, r first adder and r level linear feedback shift registers；Described first takes advantage of
Method circuit is to determine the feedback of the r levels linear feedback shift register；
Second coding unit includes：Perform the second mlultiplying circuit, d+1 second addition of the multiplying of Variable polynomial
Device and d level linear feedback shift registers；Second mlultiplying circuit is to determine the d levels linear feedback shift register
Feedback；
The output end of n-th first adder is connected with n-th grade of register of the r levels linear feedback shift register；N-th
The output end of second adder is connected with n-th grade of register of the d levels linear feedback shift register；
The d+1 second adder is connected with d-th second adder, d-th second adder with respectively with r level linear feedbacks
The afterbody register connection of shift register and d level linear feedback shift registers；Wherein, r and d is positive integer, n
Less than or equal to r or d+1.
15. encoders according to claim 14, it is characterised in that the r of the input circuit and the first coding unit
The d+1 second adder connection of individual first adder and the second coding unit；
The output circuit is connected by second selector with the input circuit, forms the first outgoing route；The output electricity
Road is also connected by the second selector with d-th second adder, forms the second outgoing route；
The second selector determines output circuit for the first outgoing route or the second outgoing route according to clocked sequential.
16. a kind of controllers of nonvolatile memory, it is characterised in that the controller is included as claim 9-15 is arbitrary
Described encoder, to input information Bose-Chaudhuri-Hocquenghem Code is performed.
17. a kind of electronic equipment, it is characterised in that the electronic equipment is included using controller as claimed in claim 16
Nonvolatile memory, to data storage information.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102272728A (en) * | 2008-12-31 | 2011-12-07 | 诺基亚公司 | Method, apparatus, and computer program product for polynomial-based data transformation and utilization |
| CN102761340A (en) * | 2012-08-10 | 2012-10-31 | 济南微晶电子技术有限公司 | Broadcast channel (BCH) parallel coding circuit |
| CN102811066A (en) * | 2012-07-17 | 2012-12-05 | 记忆科技(深圳)有限公司 | Syndrome calculating device and decoder |
| US20130275839A1 (en) * | 2008-08-13 | 2013-10-17 | Infineon Technologies Ag | Programmable Error Correction Capability for BCH Codes |
| CN105553485A (en) * | 2015-12-08 | 2016-05-04 | 西安电子科技大学 | FPGA-based BCH encoding and decoding device and encoding and decoding method thereof |
-
2016
- 2016-11-21 CN CN201611041572.XA patent/CN106603085B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130275839A1 (en) * | 2008-08-13 | 2013-10-17 | Infineon Technologies Ag | Programmable Error Correction Capability for BCH Codes |
| CN102272728A (en) * | 2008-12-31 | 2011-12-07 | 诺基亚公司 | Method, apparatus, and computer program product for polynomial-based data transformation and utilization |
| CN102811066A (en) * | 2012-07-17 | 2012-12-05 | 记忆科技(深圳)有限公司 | Syndrome calculating device and decoder |
| CN102761340A (en) * | 2012-08-10 | 2012-10-31 | 济南微晶电子技术有限公司 | Broadcast channel (BCH) parallel coding circuit |
| CN105553485A (en) * | 2015-12-08 | 2016-05-04 | 西安电子科技大学 | FPGA-based BCH encoding and decoding device and encoding and decoding method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022048431A1 (en) * | 2020-09-01 | 2022-03-10 | 华为技术有限公司 | Coding method and device |
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