CN1065662C - 半导体芯片封装及其制造方法 - Google Patents

半导体芯片封装及其制造方法 Download PDF

Info

Publication number
CN1065662C
CN1065662C CN96109458A CN96109458A CN1065662C CN 1065662 C CN1065662 C CN 1065662C CN 96109458 A CN96109458 A CN 96109458A CN 96109458 A CN96109458 A CN 96109458A CN 1065662 C CN1065662 C CN 1065662C
Authority
CN
China
Prior art keywords
lead
substrate
chip
substrate lead
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN96109458A
Other languages
English (en)
Other versions
CN1153997A (zh
Inventor
宋致仲
李柱华
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
LG Semicon Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LG Semicon Co Ltd filed Critical LG Semicon Co Ltd
Publication of CN1153997A publication Critical patent/CN1153997A/zh
Application granted granted Critical
Publication of CN1065662C publication Critical patent/CN1065662C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201—Structure
    • H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32014—Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1029—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being a lead frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本发明公开的改进封装增加了存储容量，改善了热辐射效果，并且是比较薄的。该封装包括若干条引线，其中每条引线包括具有上和下表面的第一衬底引线和第二衬底引线。集成芯片，例如半导体芯片附着在第一衬底引线上表面的区域。芯片和引线被模制以致第一衬底引线的下表面和第二衬底引线的上表面被露出。

Description

半导体芯片封装及其制造方法
本发明涉及半导体芯片封装以及制备这种半导体封装的方法，特别涉及这样一种半导体芯片封装，其引一的上或下表面的预定区域向外暴露。
图1示出了美国专利第5，428，248号公开的暴露引线的半导体封装，该申请已转让给LG半导体株式会社。半导体芯片11通过粘附元件13安装在衬底引线12a的上表面。从衬底引线12a扩展的芯片引线12b具有近似于半导体芯片11上表面的高度的预定高度。在半导体芯片11上形成的若干键合焊盘和芯片引线12b通过引线14相连接。包括半导体芯片11和若干引线12a和12b的预定区域用树脂模制，衬底引线12a的下表面从封装的下表面区域露出以电连接电路衬底(未示出)的金属图形。
传统的露线式半导体封装的缺点是，由于衬底引线朝封装的下表面暴露，因而该封装不能层叠很多半导体芯片，从而限制了存储容量的增加。此外，由于传统的露线式半导体封装具有只朝暴露的衬底引线辐射热的结构，因此不能实现所期望的热辐射效果。另外，由于引线焊接要在半导体芯片下部区域完成以及包括半导体上部的预定区域要由树脂模制，因此封装的厚度需要增加。
所以，本发明的目的是提出能解决上述问题的露线式半导体封装。
本发明的优点是提供了较薄的露线式半导体封装。
本发明另一个优点是增加了半导体封装的存储芯片容量。
本发明再一个优点是改善了封装中的由半导体封装产生的热辐射。
上述目的和优点部分地由集成芯片封装来实现，一种半导体芯片封装，包括：
一个半导体芯片，其中具有多个键合焊盘，一个引线框架，具有多个各自具有下表面和上表面的引线，每个引线具有第一和第二衬底引线，第二衬底引线的上表面的一部分平行于第一衬底引线的下表面的一部分；粘附元件，用于将半导体芯片固定到引线框架上；多个导电元件，用于将芯片上的所述多个键合焊盘与多个引线相连；模制体，用于封装所述半导体芯片、引线框架、粘附元件和导电元件；其特征在于：所述第二衬底引线的上表面的所述平行部分和所述第一衬底引线的下表面的所述平行部分向外暴露并具有相似的面积。
为实现上述目的和优点，本发明提供的制造上述半导体封装的方法，包括：模键合步骤，用于将一半导体芯片用粘附元件固定到一引线框架的第一衬底引线的上表面上，所述引线框架具有多个各自具有下表面和上表面的引线，每个引线具有第一和第二衬底引线，第二衬底引线的上表面的一部分平行于第一衬底引线的下表面的一部分；电性连接步骤，利用导电元件使所述半导体芯片上的键合焊盘与引线框架的引线的一个表面相连；模制步骤，用于封装半导体芯片、粘附元件、导电元件和引线，其中使引线框架的第二衬底引线的上表面的所述平行部分和引线框架的第一衬底引线的下表面的所述平行部分向外暴露并具有相似的面积。
本发明的附加优点、目的和其他特点将在下文中说明，对本领域的普通技术人员来说，根据对下文的分析将会清楚这些特点(附加优点，目的和其它特点)或者能够从本发明的实践中了解这些特点(附加优点、目的和其它特点)。本发明的目的和优点能够象权利要求书特别指出的那样实现和达到。
下面参照附图详细说明本发明，在图中相同的参考标号指相同的元件。
图1是美国专利第5，428，248号公开的露线式半导体封装的剖面图；
图2是本发明实施例的露线式半导体封装的剖面图；
图3是图2所示的露线式半导体封装的底(仰)视图；
图4是本发明另一实施例的暴露引线式半导体封装的剖面图；
图5是根据本发明层叠图2所示半导体封装的增加集成芯片容量的结构的剖面图；
图6是根据本发明层叠图4所示半导体封装的增加集成芯片容量的结构的剖面图．
图2是根据具有示出底部视图的图3的本发明实施例所示的露线式半导体封装的剖面图。半导体芯片21在其下表面形成有若干键合焊盘。引线框架22设置在半导体芯片21的下部，它包括若干条引线。每条引线包括第一衬底引线22a和第二衬底引线22b。第二衬底引线的预定长度在从第一衬底引线22a的一端上向弯曲之后平行于第一衬底引线22a伸展。
若干个粘附元件23用于固定或安装半导体芯片21到第一衬底引线22a另一端部分的上表面。粘附元件23可以是双面绝缘带或者基于聚酰胺或环氧树脂的绝缘胶。若干导线24把半导体芯片下表面上的若干键合焊盘电连接到第二衬底引线22b的下表面。
树脂制作的模制体26采用模制工艺形成以封装半导体芯片21、若干导线24、粘附元件23、第一衬底引线22a的上表面和第二衬底引线22b的下表面。尽管这样，第一衬底引线22a的下表面和第二衬底引线22b的上表面仍被暴露并且实质上与模制体26的外表面共面。所以，从第一衬底引线22a的下表面到第二衬底引线22b的上表面的高度等于半导体封装的厚度。第一衬底引线22a的被暴露下表面的面积可以相似于第二衬底引线22b的被暴露上表面的面积。此后，第一衬底引线22a的被暴露的下表面或第二衬底引线22b的被暴露上表面连接到印刷电路板的金属图形(未示出)。
图4示出了根据本发明另一个实施例的露线式半导体封装的剖面图。图4的实施例类似于图2的实施例。在该实施例中，不是用若干导线24而是用若干焊料块25把键合焊盘连接到第一衬底引线22a的上表面。
本发明的第一和第二实例的露线式半导体封装的加工方法是类似的。在图2所示的实施例中，该方法包括：用于把半导体芯片21从晶片中分离的锯开步骤；用于利用粘附元件23把半导体芯片21安装在第一衬底引线22a上表面的模键合步骤；用于使用像金或铝那样的导线24连接半导体芯片21的若干键合焊盘和衬底引线22a的导线焊接步骤；和模制步骤，它用于采用模制树脂封装焊接引线的半导体芯片21和衬底引线22a以便引线22可以部分地暴露于封装体的上和下表面。在图4所示的实施例中，导线连接工序用焊接工序可替换。在两个实施例中，成型和修整工序不再需要，从而节省了制造封装的费用。
如图2和图4所示，封装的高度被减小。此外，由于引线被暴露在半导体封装的上、下表面上，因此引线又成为了散热片，从而改善了热辐射，增强了抵抗热损坏的芯片可靠性。从上所述不难看到，本发明可以容易地实现封装的小型化，能够非常容易地完成芯片的安装。并且还能够容易地完成电特性试验，这样就增强了电气可靠性。
在上述实施例中，所述的表面指便于说明附图视图中的本发明的上表面和下表面。也可以理解为依据封装定向的参考表面。此外，上述实施例只不过是示范，不能作为限定本发明来作解释。例如，图2和图4实施例示出了密封的半导体芯片，但本领域的普通技术人员可以容易地封装具有暴露芯片上表面的芯片。本领域的技术人员将会明白本发明的许多变形和变化的任一种。

Claims (18)

1．一种半导体芯片封装，包括：
一个半导体芯片，其中具有多个键合焊盘，
一个引线框架，具有多个各自具有下表面和上表面的引线，每个引线具有一和第二衬底引线，第二衬底引线的上表面的一部分平行于第一衬底引线的下表面的一部分；
粘附元件，用于将半导体芯片固定到引线框架上；
多个导电元件，用于将芯片上的所述多个键合焊盘与多个引线相连；
模制体，用于封装所述半导体芯片、引线框架、粘附元件和导电元件；
其特征在于：
所述第二衬底引线的上表面的所述平行部分和所述第一衬底引线的下表面的所述平行部分向外暴露并具有相似的面积。
2．根据权利要求1的半导体芯片封装，其中所述粘附元件至少是双面绝缘胶带和绝缘膏中的一种。
3．根据权利要求1的半导体芯片封装，其特征在于所述导电元件包括多根引线。
4．根据权利要求1的半导体芯片封装，其特征在于所述导电元件包括多个焊料块。
5．根据权利要求3的半导体封装，其特征在于所述多根引线用于将芯片上的键合焊盘到连接到相应的第二衬底引线的下表面。
6．根据权利要求4的半导体封装，其特征在于所述多个焊料块将芯片上的键合焊盘连接到相应的第一衬底引线的上表面。
7．根据权利要求1的半导体封装，其特征在于所述第一和第二衬底引线的向外暴露部分与所述模制体的外表面共面。
8．根据权利要求1的半导体封装，其特征在于所述半导体芯片被部分地由模制体封装，至少芯片的一个表面向外暴露。
 9．根据权利要求1的半导体封装，其特征在于所述第二衬底引线与第一衬底引线的一端弯折后的那部分平行。
10．用于制造半导体芯片封装的方法，包括以下步骤：
模键合步骤，用于将一半导体芯片用粘附元件固定到一引线框架的第一衬底引线的上表面上，所述引线框架具有多个各自具有下表面和上表面的引线，每个引线具有第一和第二衬底引线，第二衬底引线的上表面的一部分平行于第一衬底引线的下表面的一部分；
电性连接步骤，利用导电元件使所述半导体芯片上的键合焊盘与引线框架的引线的一个表面相连；
模制步骤，用于封装半导体芯片、粘附元件、导电元件和引线，其中使引线框架的第二衬底引线的上表面的所述平行部分和引线框架的第一衬底引线的下表面的所述平行部分向外暴露并具有相似的面积。
11．根据权利要求10的方法，其中所述粘附元件至少是双面绝缘胶带和绝缘膏中的一种。
12．根据权利要求10的方法，其中所述导电元件包括多根引线。
13．根据权利要求10的方法，其中所述导电元件包括多个焊料块。
14．根据权利要求12的方法，其中所述多根引线用于将芯片上的键合焊盘到连接到相应的第二衬底引线的下表面。
15．根据权利要求13的方法，其中所述多个焊料块将芯片上的键合焊盘连接到相应的第一衬底引线的上表面。
16．根据权利要求10的方法，其中所述第一和第二衬底引线的向外暴露部分与所述模制体的外表面共面。
17．根据权利要求10的方法，其中所述半导体芯片被部分地由模制体封装，至少芯片的一个表面向外暴露。
18．根据权利要求10的方法，其中所述第二衬底引线与第一衬底引线的一端弯折后的那部分平行。
CN96109458A 1995-12-29 1996-08-23 半导体芯片封装及其制造方法 Expired - Fee Related CN1065662C (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR67335/95 1995-12-29
KR1019950067335A KR0179803B1 (ko) 1995-12-29 1995-12-29 리드노출형 반도체 패키지
KR67335/1995 1995-12-29

Publications (2)

Publication Number Publication Date
CN1153997A CN1153997A (zh) 1997-07-09
CN1065662C true CN1065662C (zh) 2001-05-09

Family

ID=19447662

Family Applications (1)

Application Number Title Priority Date Filing Date
CN96109458A Expired - Fee Related CN1065662C (zh) 1995-12-29 1996-08-23 半导体芯片封装及其制造方法

Country Status (5)

Country Link
US (1) US5770888A (zh)
JP (1) JP2992814B2 (zh)
KR (1) KR0179803B1 (zh)
CN (1) CN1065662C (zh)
TW (1) TW344887B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101636728A (zh) * 2007-01-02 2010-01-27 阿苏克斯有限公司 用于不同通信标准间切换的***和方法

Families Citing this family (114)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09260538A (ja) 1996-03-27 1997-10-03 Miyazaki Oki Electric Co Ltd 樹脂封止型半導体装置及び製造方法とその実装構造
US5731244A (en) 1996-05-28 1998-03-24 Micron Technology, Inc. Laser wire bonding for wire embedded dielectrics to integrated circuits
KR100242994B1 (ko) * 1996-12-28 2000-02-01 김영환 버텀리드프레임 및 그를 이용한 버텀리드 반도체 패키지
KR100237051B1 (ko) * 1996-12-28 2000-01-15 김영환 버텀리드 반도체 패키지 및 그 제조 방법
KR100214544B1 (ko) * 1996-12-28 1999-08-02 구본준 볼 그리드 어레이 반도체 패키지
KR100214561B1 (ko) * 1997-03-14 1999-08-02 구본준 버틈 리드 패키지
JP2954110B2 (ja) * 1997-09-26 1999-09-27 九州日本電気株式会社 Ｃｓｐ型半導体装置及びその製造方法
US6168975B1 (en) * 1998-06-24 2001-01-02 St Assembly Test Services Pte Ltd Method of forming extended lead package
US6143981A (en) 1998-06-24 2000-11-07 Amkor Technology, Inc. Plastic integrated circuit package and method and leadframe for making the package
KR100293815B1 (ko) * 1998-06-30 2001-07-12 박종섭 스택형 패키지
DE19844966A1 (de) * 1998-09-30 2000-01-13 Siemens Ag Halbleiterbauteil sowie dieses umfassender Chipkartenmodul
KR100319616B1 (ko) * 1999-04-17 2002-01-05 김영환 리드프레임 및 이를 이용한 버텀리드 반도체패키지
US6265761B1 (en) * 1999-05-07 2001-07-24 Maxim Integrated Products, Inc. Semiconductor devices with improved lead frame structures
US6420779B1 (en) 1999-09-14 2002-07-16 St Assembly Test Services Ltd. Leadframe based chip scale package and method of producing the same
KR100344927B1 (ko) * 1999-09-27 2002-07-19 삼성전자 주식회사 적층 패키지 및 그의 제조 방법
KR100379089B1 (ko) 1999-10-15 2003-04-08 앰코 테크놀로지 코리아 주식회사 리드프레임 및 이를 이용한 반도체패키지
JP3602997B2 (ja) * 1999-12-15 2004-12-15 松下電器産業株式会社 半導体装置及び半導体装置の製造方法
KR100421774B1 (ko) * 1999-12-16 2004-03-10 앰코 테크놀로지 코리아 주식회사 반도체패키지 및 그 제조 방법
KR100370851B1 (ko) * 1999-12-30 2003-02-05 앰코 테크놀로지 코리아 주식회사 반도체패키지
US7042068B2 (en) 2000-04-27 2006-05-09 Amkor Technology, Inc. Leadframe and semiconductor package made using the leadframe
JP4637380B2 (ja) * 2001-02-08 2011-02-23 ルネサスエレクトロニクス株式会社 半導体装置
US6545345B1 (en) 2001-03-20 2003-04-08 Amkor Technology, Inc. Mounting for a package containing a chip
KR100369393B1 (ko) 2001-03-27 2003-02-05 앰코 테크놀로지 코리아 주식회사 리드프레임 및 이를 이용한 반도체패키지와 그 제조 방법
US6603196B2 (en) * 2001-03-28 2003-08-05 Siliconware Precision Industries Co., Ltd. Leadframe-based semiconductor package for multi-media card
JP4598316B2 (ja) * 2001-07-06 2010-12-15 パナソニック株式会社 樹脂封止型半導体装置およびその製造方法
DE10147376B4 (de) * 2001-09-26 2009-01-15 Infineon Technologies Ag Elektronisches Bauteil und Systemträger sowie Verfahren zur Herstellung derselben
DE10147375B4 (de) * 2001-09-26 2006-06-08 Infineon Technologies Ag Elektronisches Bauteil mit einem Halbleiterchip und Verfahren zur Herstellung desselben
US6608366B1 (en) 2002-04-15 2003-08-19 Harry J. Fogelson Lead frame with plated end leads
US6919620B1 (en) 2002-09-17 2005-07-19 Amkor Technology, Inc. Compact flash memory card with clamshell leadframe
US6905914B1 (en) 2002-11-08 2005-06-14 Amkor Technology, Inc. Wafer level package and fabrication method
US7723210B2 (en) 2002-11-08 2010-05-25 Amkor Technology, Inc. Direct-write wafer level chip scale package
US20040124508A1 (en) * 2002-11-27 2004-07-01 United Test And Assembly Test Center Ltd. High performance chip scale leadframe package and method of manufacturing the package
US8129222B2 (en) 2002-11-27 2012-03-06 United Test And Assembly Test Center Ltd. High density chip scale leadframe package and method of manufacturing the package
US6798047B1 (en) 2002-12-26 2004-09-28 Amkor Technology, Inc. Pre-molded leadframe
US6750545B1 (en) 2003-02-28 2004-06-15 Amkor Technology, Inc. Semiconductor package capable of die stacking
US6927483B1 (en) 2003-03-07 2005-08-09 Amkor Technology, Inc. Semiconductor package exhibiting efficient lead placement
US6794740B1 (en) 2003-03-13 2004-09-21 Amkor Technology, Inc. Leadframe package for semiconductor devices
US20060201709A1 (en) * 2003-04-07 2006-09-14 Mciver Chandler H Low profile small outline leadless semiconductor device package
US6879034B1 (en) 2003-05-01 2005-04-12 Amkor Technology, Inc. Semiconductor package including low temperature co-fired ceramic substrate
US6921967B2 (en) 2003-09-24 2005-07-26 Amkor Technology, Inc. Reinforced die pad support structure
US7568059B2 (en) * 2004-07-08 2009-07-28 Asocs Ltd. Low-power reconfigurable architecture for simultaneous implementation of distinct communication standards
JP2006190972A (ja) * 2004-12-08 2006-07-20 Mitsubishi Electric Corp 電力用半導体装置
KR100630741B1 (ko) * 2005-03-04 2006-10-02 삼성전자주식회사 다중 몰딩에 의한 적층형 반도체 패키지 및 그 제조방법
US7968377B2 (en) * 2005-09-22 2011-06-28 Stats Chippac Ltd. Integrated circuit protruding pad package system
US7507603B1 (en) 2005-12-02 2009-03-24 Amkor Technology, Inc. Etch singulated semiconductor package
US7572681B1 (en) 2005-12-08 2009-08-11 Amkor Technology, Inc. Embedded electronic component package
US7385299B2 (en) * 2006-02-25 2008-06-10 Stats Chippac Ltd. Stackable integrated circuit package system with multiple interconnect interface
US7902660B1 (en) 2006-05-24 2011-03-08 Amkor Technology, Inc. Substrate for semiconductor device and manufacturing method thereof
US7968998B1 (en) 2006-06-21 2011-06-28 Amkor Technology, Inc. Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package
US7683461B2 (en) * 2006-07-21 2010-03-23 Stats Chippac Ltd. Integrated circuit leadless package system
US7687892B2 (en) * 2006-08-08 2010-03-30 Stats Chippac, Ltd. Quad flat package
US7687893B2 (en) 2006-12-27 2010-03-30 Amkor Technology, Inc. Semiconductor package having leadframe with exposed anchor pads
US7829990B1 (en) 2007-01-18 2010-11-09 Amkor Technology, Inc. Stackable semiconductor package including laminate interposer
US7982297B1 (en) 2007-03-06 2011-07-19 Amkor Technology, Inc. Stackable semiconductor package having partially exposed semiconductor die and method of fabricating the same
US7977774B2 (en) 2007-07-10 2011-07-12 Amkor Technology, Inc. Fusion quad flat semiconductor package
US7687899B1 (en) 2007-08-07 2010-03-30 Amkor Technology, Inc. Dual laminate package structure with embedded elements
US7868471B2 (en) * 2007-09-13 2011-01-11 Stats Chippac Ltd. Integrated circuit package-in-package system with leads
US7777351B1 (en) 2007-10-01 2010-08-17 Amkor Technology, Inc. Thin stacked interposer package
US8089159B1 (en) 2007-10-03 2012-01-03 Amkor Technology, Inc. Semiconductor package with increased I/O density and method of making the same
JP2009094118A (ja) * 2007-10-04 2009-04-30 Panasonic Corp リードフレーム、それを備える電子部品及びその製造方法
US7847386B1 (en) 2007-11-05 2010-12-07 Amkor Technology, Inc. Reduced size stacked semiconductor package and method of making the same
US7977782B2 (en) * 2007-11-07 2011-07-12 Stats Chippac Ltd. Integrated circuit package system with dual connectivity
US7956453B1 (en) 2008-01-16 2011-06-07 Amkor Technology, Inc. Semiconductor package with patterning layer and method of making same
US7723852B1 (en) 2008-01-21 2010-05-25 Amkor Technology, Inc. Stacked semiconductor package and method of making same
US8063474B2 (en) 2008-02-06 2011-11-22 Fairchild Semiconductor Corporation Embedded die package on package (POP) with pre-molded leadframe
US8067821B1 (en) 2008-04-10 2011-11-29 Amkor Technology, Inc. Flat semiconductor package with half package molding
US7768135B1 (en) 2008-04-17 2010-08-03 Amkor Technology, Inc. Semiconductor package with fast power-up cycle and method of making same
US7808084B1 (en) 2008-05-06 2010-10-05 Amkor Technology, Inc. Semiconductor package with half-etched locking features
US8125064B1 (en) 2008-07-28 2012-02-28 Amkor Technology, Inc. Increased I/O semiconductor package and method of making same
US8184453B1 (en) 2008-07-31 2012-05-22 Amkor Technology, Inc. Increased capacity semiconductor package
US7847392B1 (en) 2008-09-30 2010-12-07 Amkor Technology, Inc. Semiconductor device including leadframe with increased I/O
US7989933B1 (en) 2008-10-06 2011-08-02 Amkor Technology, Inc. Increased I/O leadframe and semiconductor device including same
US8008758B1 (en) 2008-10-27 2011-08-30 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe
US8089145B1 (en) 2008-11-17 2012-01-03 Amkor Technology, Inc. Semiconductor device including increased capacity leadframe
US8072050B1 (en) 2008-11-18 2011-12-06 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe including passive device
US7875963B1 (en) 2008-11-21 2011-01-25 Amkor Technology, Inc. Semiconductor device including leadframe having power bars and increased I/O
US7982298B1 (en) 2008-12-03 2011-07-19 Amkor Technology, Inc. Package in package semiconductor device
US8487420B1 (en) 2008-12-08 2013-07-16 Amkor Technology, Inc. Package in package semiconductor device with film over wire
CN101764127B (zh) * 2008-12-23 2012-01-04 日月光封装测试(上海)有限公司 无外引脚的半导体封装体及其堆迭构造
US20170117214A1 (en) 2009-01-05 2017-04-27 Amkor Technology, Inc. Semiconductor device with through-mold via
US8680656B1 (en) 2009-01-05 2014-03-25 Amkor Technology, Inc. Leadframe structure for concentrated photovoltaic receiver package
US8058715B1 (en) 2009-01-09 2011-11-15 Amkor Technology, Inc. Package in package device for RF transceiver module
US8026589B1 (en) 2009-02-23 2011-09-27 Amkor Technology, Inc. Reduced profile stackable semiconductor package
US7960818B1 (en) 2009-03-04 2011-06-14 Amkor Technology, Inc. Conformal shield on punch QFN semiconductor package
US8575742B1 (en) 2009-04-06 2013-11-05 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe including power bars
USRE48111E1 (en) 2009-08-21 2020-07-21 JCET Semiconductor (Shaoxing) Co. Ltd. Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect
US8383457B2 (en) 2010-09-03 2013-02-26 Stats Chippac, Ltd. Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect
US8169058B2 (en) 2009-08-21 2012-05-01 Stats Chippac, Ltd. Semiconductor device and method of stacking die on leadframe electrically connected by conductive pillars
US8796561B1 (en) 2009-10-05 2014-08-05 Amkor Technology, Inc. Fan out build up substrate stackable package and method
US9391005B2 (en) * 2009-10-27 2016-07-12 Alpha And Omega Semiconductor Incorporated Method for packaging a power device with bottom source electrode
US8937381B1 (en) 2009-12-03 2015-01-20 Amkor Technology, Inc. Thin stackable package and method
US9691734B1 (en) 2009-12-07 2017-06-27 Amkor Technology, Inc. Method of forming a plurality of electronic component packages
US8324511B1 (en) 2010-04-06 2012-12-04 Amkor Technology, Inc. Through via nub reveal method and structure
US8294276B1 (en) 2010-05-27 2012-10-23 Amkor Technology, Inc. Semiconductor device and fabricating method thereof
US8440554B1 (en) 2010-08-02 2013-05-14 Amkor Technology, Inc. Through via connected backside embedded circuit features structure and method
JP2012069764A (ja) 2010-09-24 2012-04-05 On Semiconductor Trading Ltd 回路装置およびその製造方法
US8487445B1 (en) 2010-10-05 2013-07-16 Amkor Technology, Inc. Semiconductor device having through electrodes protruding from dielectric layer
US8791501B1 (en) 2010-12-03 2014-07-29 Amkor Technology, Inc. Integrated passive device structure and method
US8390130B1 (en) 2011-01-06 2013-03-05 Amkor Technology, Inc. Through via recessed reveal structure and method
TWI557183B (zh) 2015-12-16 2016-11-11 財團法人工業技術研究院 矽氧烷組成物、以及包含其之光電裝置
US8648450B1 (en) 2011-01-27 2014-02-11 Amkor Technology, Inc. Semiconductor device including leadframe with a combination of leads and lands
BRPI1103019A2 (pt) * 2011-06-21 2013-07-16 Whirlpool Sa conector para compressores hermÉticos
US8552548B1 (en) 2011-11-29 2013-10-08 Amkor Technology, Inc. Conductive pad on protruding through electrode semiconductor device
CN103187381B (zh) * 2011-12-30 2015-09-16 联咏科技股份有限公司 导线架封装结构
US9704725B1 (en) 2012-03-06 2017-07-11 Amkor Technology, Inc. Semiconductor device with leadframe configured to facilitate reduced burr formation
US9129943B1 (en) 2012-03-29 2015-09-08 Amkor Technology, Inc. Embedded component package and fabrication method
US9048298B1 (en) 2012-03-29 2015-06-02 Amkor Technology, Inc. Backside warpage control structure and fabrication method
KR101486790B1 (ko) 2013-05-02 2015-01-28 앰코 테크놀로지 코리아 주식회사 강성보강부를 갖는 마이크로 리드프레임
KR101563911B1 (ko) 2013-10-24 2015-10-28 앰코 테크놀로지 코리아 주식회사 반도체 패키지
US9673122B2 (en) 2014-05-02 2017-06-06 Amkor Technology, Inc. Micro lead frame structure having reinforcing portions and method
JP6262086B2 (ja) * 2014-07-04 2018-01-17 アルプス電気株式会社 圧力検出装置
CN104600045B (zh) * 2015-01-30 2017-06-06 无锡中感微电子股份有限公司 电路***、芯片封装及其封装方法
US9917041B1 (en) * 2016-10-28 2018-03-13 Intel Corporation 3D chip assemblies using stacked leadframes
FR3104317A1 (fr) * 2019-12-04 2021-06-11 Stmicroelectronics (Tours) Sas Procédé de fabrication de puces électroniques

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5471088A (en) * 1992-11-07 1995-11-28 Goldstar Electron Co., Ltd. Semiconductor package and method for manufacturing the same

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6089945A (ja) * 1983-10-24 1985-05-20 Matsushita Electric Works Ltd 封止半導体装置
JPH071793B2 (ja) * 1985-07-23 1995-01-11 松下電器産業株式会社 ハイブリツド光ｉｃ装置
US4857989A (en) * 1986-09-04 1989-08-15 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
JPS63182845A (ja) * 1987-01-23 1988-07-28 Nec Ic Microcomput Syst Ltd 半導体装置
JPH01232753A (ja) * 1988-03-14 1989-09-18 Matsushita Electron Corp 半導体装置
JP2530056B2 (ja) * 1989-09-14 1996-09-04 株式会社東芝 樹脂封止型半導体装置及びその製造方法
JPH03250657A (ja) * 1990-02-28 1991-11-08 Hitachi Ltd 表裏両面実装可能な樹脂封止型半導体装置
US5157480A (en) * 1991-02-06 1992-10-20 Motorola, Inc. Semiconductor device having dual electrical contact sites
FR2673042A1 (fr) * 1991-02-18 1992-08-21 Em Microelectronic Marin Sa Module electronique resistant aux deformations mecaniques pour carte a microcircuits.
JPH04284661A (ja) * 1991-03-13 1992-10-09 Toshiba Corp 半導体装置
US5214307A (en) * 1991-07-08 1993-05-25 Micron Technology, Inc. Lead frame for semiconductor devices having improved adhesive bond line control
KR930014916A (ko) * 1991-12-24 1993-07-23 김광호 반도체 패키지
JP3124381B2 (ja) * 1992-07-07 2001-01-15 株式会社日立製作所 半導体装置及び実装構造体
KR0128251Y1 (ko) * 1992-08-21 1998-10-15 문정환 리드 노출형 반도체 조립장치
US5406124A (en) * 1992-12-04 1995-04-11 Mitsui Toatsu Chemicals, Inc. Insulating adhesive tape, and lead frame and semiconductor device employing the tape
KR0152901B1 (ko) * 1993-06-23 1998-10-01 문정환 플라스틱 반도체 패키지 및 그 제조방법

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5471088A (en) * 1992-11-07 1995-11-28 Goldstar Electron Co., Ltd. Semiconductor package and method for manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101636728A (zh) * 2007-01-02 2010-01-27 阿苏克斯有限公司 用于不同通信标准间切换的***和方法

Also Published As

Publication number Publication date
KR0179803B1 (ko) 1999-03-20
US5770888A (en) 1998-06-23
TW344887B (en) 1998-11-11
KR970053679A (ko) 1997-07-31
JP2992814B2 (ja) 1999-12-20
JPH09326452A (ja) 1997-12-16
CN1153997A (zh) 1997-07-09

Similar Documents

Publication Publication Date Title
CN1065662C (zh) 半导体芯片封装及其制造方法
US5864174A (en) Semiconductor device having a die pad structure for preventing cracks in a molding resin
CN1064780C (zh) 底部引线半导体芯片堆式封装
US6080264A (en) Combination of semiconductor interconnect
US6239366B1 (en) Face-to-face multi-chip package
US7595551B2 (en) Semiconductor package for a large die
CN102201388B (zh) 方形扁平无引线半导体封装及其制作方法
US7723839B2 (en) Semiconductor device, stacked semiconductor device, and manufacturing method for semiconductor device
US5821615A (en) Semiconductor chip package having clip-type outlead and fabrication method of same
JP2644711B2 (ja) 金属の回路基板を有するチップスケールのパッケージ
CN102341899B (zh) 具有多种ic封装构造的无引线阵列塑料封装
EP0862217A2 (en) Semiconductor device and semiconductor multi-chip module
CN1833317A (zh) 用于引线接合焊球阵列的接地拱顶
US5796038A (en) Technique to produce cavity-up HBGA packages
CN1129184C (zh) 用于半导体器件的引线框架
CN1169033A (zh) 一种改进的半导体封装
CN1099131C (zh) 栅阵列球半导体封装
KR100422608B1 (ko) 적층칩패키지
KR100437821B1 (ko) 반도체 패키지 및 그 제조방법
KR100481927B1 (ko) 반도체패키지및그제조방법
CN2619367Y (zh) 应用于高频ic的导线架
JPH11145319A (ja) プラスチックｂｇａパッケージ
KR20010009337A (ko) 볼 그리드 어레이 패키지 및 그 제조 방법
KR19980035064A (ko) 적층형 반도체 칩 패키지
KR20010008947A (ko) 테이프 멀티칩 패키지 방법과 구조

Legal Events

Date Code Title Description
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C06 Publication
PB01 Publication
C14 Grant of patent or utility model
FG4A Grant of patent
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20010509

Termination date: 20130823