CN106529067B - A kind of low power consuming clock dynamic management circuit and management method - Google Patents

Abstract

The invention discloses a kind of low power consuming clock dynamic management circuit and management methods, are related to IC design field.The method of the present invention includes being sent to clock selection circuit, selected flip-flop operation clock, functional simulation and timing inspection by function classification trigger, formation SR topological structure, the generation of clock control sequence, control sequence and generating netlist step.The present invention provides the clock trigger structures that one kind can carry out work clock selection, pass through the control of clock selecting position, the work clock of adjustable trigger is quick clock or Slow Clock, the working clock frequency of trigger is adjusted flexibly according to Design of Digital Circuit functional requirement, both the correctness of design function had been can guarantee, the working frequency for reducing partial circuit in design to the greatest extent simultaneously, reduces power consumption.

Description

A kind of low power consuming clock dynamic management circuit and management method

Technical field

The present invention relates to IC design field more particularly to a kind of low power consuming clock based on doubleclocking trigger are dynamic State manages circuit and management method.

Background technique

CMOS technology is occupied an leading position in VLSI design at present.As integrated circuit constantly develops and new work The continuous use of skill so that the integrated level of circuit is higher and higher, while also obtaining higher system clock frequency.It is highly integrated The technique of degree, high clock frequency and small size has inevitably led to the increase of circuit power consumption.Caused by power consumption increase A series of problems finally makes the size of power consumption become a main indicator for measuring modern integrated circuits.Low power dissipation design also at One emergency technical demand of IC design.And power consumption, it is either dynamic or static, have become constraint Device performance, a key factor in service life and integrated level.

In low-power consumption VLSI Design, wherein meaningful one piece is how to reduce same clock network phase The power consumption of this partial circuit closed, because data show that, the power consumption of this part circuit accounts for the 20%-50% of entire chip power-consumption As many as.And wherein power consumption consumed by trigger accounts for the 90% of clock network power consumption.Therefore reached by reducing trigger power consumption Reducing chip total power consumption seems very important.

Trigger is a basic digital circuit component simultaneously, they are universal and are employed for digital circuit in large quantities and set In meter.Since they are large number of, the Save power consumption of any point of each trigger can lead to a digital circuit The considerable Save power consumption of system, this is also a major reason for carrying out Low Power Flip-flops research.

Summary of the invention

Technical problem to be solved by the invention is to provide a kind of, and the low power consuming clock dynamic based on doubleclocking trigger is managed Circuit and management method are managed, achieve the purpose that reduce trigger power consumption and then reduces chip total power consumption.

To solve above-mentioned technical field, the technical solution adopted by the present invention is that: a kind of doubleclocking trigger, including main latch Device, from latch, clock selection circuit, main latch is for receiving external data, and output is to from latch after latch；From latch Device is used for output data；Clock selection circuit is used to receive the clock signal of two-way different frequency, in the control of clock selection signal Wherein clock signal exports respectively to main latch and from latch the lower selection of system all the way.

A kind of low power consuming clock dynamic management circuit based on doubleclocking trigger, including doubleclocking trigger, displacement are posted Storage topological structure and control sequence generator, control sequence generator are used to receive control under the control of external timing signal Sequence, and according to the dynamic change of shift register topological structure change control sequence, by the control sequence after change export to Shift register topological structure；Shift register topological structure be used for will change after control sequence each as clock choosing Signal is selected to export to one or more doubleclocking trigger；Doubleclocking trigger be used for according to clock selection signal two-way not Selected in the clock signal of same frequency wherein all the way clock signal as work clock；The control sequence is according to shift LD Device topological structure generates.

A kind of low power consuming clock dynamic management approach based on doubleclocking trigger, comprising the following steps:

Step 1: classifying according to the functional requirement of low power consuming clock dynamic management circuit to all doubleclocking triggers；

Step 2: of a sort doubleclocking trigger will be belonged to and be connected to the same shift register, form shift register Topological structure；

Step 3: control sequence generator receives control sequence under the control of external timing signal, and according to shift LD The dynamic change of device topological structure changes control sequence, and the control sequence after change is exported to shift register topological structure； The control sequence is generated according to shift register topological structure；

Step 4: shift register topological structure sends out each of the control sequence after change as clock selection signal It is sent to the clock selection circuit of corresponding doubleclocking trigger；

Step 5: doubleclocking trigger selects wherein in the clock signal of two-way different frequency according to clock selection signal Clock signal is as work clock all the way；

Step 6: functional simulation and timing inspection are carried out to low power consuming clock dynamic management circuit；

Step 7: to the low power consuming clock dynamic management circuit evolving netlist for meeting functional simulation and timing inspection requirements.

It has the benefit that by adopting the above technical scheme

1. passing through clock selecting the present invention provides a kind of novel trigger structure that can carry out work clock selection The control of position, the work clock of adjustable trigger are quick clock or Slow Clock；

2. the working clock frequency of trigger can be adjusted flexibly in the present invention according to Design of Digital Circuit functional requirement, can Guarantee the correctness of design function, while reducing the working frequency of partial circuit in design to the greatest extent, reduces power consumption；

3. passing through control sequence the present invention provides the low-power consumption Dynamic clock management circuit structure to trigger in design Generator and reasonable control circuit topological structure, reach and are precisely controlled to each trigger.

Detailed description of the invention

Fig. 1 is low power consuming clock dynamic management approach flow chart of the invention；

Fig. 2 is the structural schematic diagram of doubleclocking trigger of the invention；

Fig. 3 is low power consuming clock dynamic management circuit structure figure of the invention.

Specific embodiment

As shown in Figure 1, a kind of low power consuming clock dynamic management approach based on doubleclocking trigger, including walk in detail below It is rapid:

Step 1: press function classification trigger: according to low power consuming clock dynamic management circuit functional requirement to it is all double when Ms filp flop is classified；

It in the present embodiment, will be partially or all in the netlist of generation after Design of Digital Circuit carries out logic synthesis Novel low power consumption doubleclocking trigger (as shown in Figure 2) in trigger alternative costs invention.The doubleclocking trigger and common Trigger the difference is that, it include two input end of clock mouths (Slow Clock port and quick clock port), when double The structure i.e. clock selection circuit of similar clock selector is embedded in ms filp flop, by the low and high level of clock selecting port Variation, can be using the work clock of flexible choice doubleclocking trigger as Slow Clock or quick clock.

Step 2: forming SR topological structure: of a sort doubleclocking trigger will be belonged to and be connected to the same shift LD Device forms shift register topological structure；

The i.e. SR of class shift register cell can be mounted outside the clock selection signal end of each doubleclocking trigger to open up Structure (as shown in Figure 3) is flutterred, i.e. SR topological structure can be constructed according to the difference of each doubleclocking trigger function demand for these Reasonable topological structure can satisfy the clock of various complicated architectures in Design of Digital Circuit by with different levels series control Selection control.In specific control process, the control sequence that control sequence generator issues is input to SR topology knot by the port CO Structure selects to complete quick, Slow Clock to the trigger of entire digital circuit in shortest clock periodicity, guarantees number The power consumption of the reduction trigger of high degree while word circuit function.

Step 3: clock control sequence generates: control sequence generator receives control sequence under the control of external timing signal Column, and control sequence is changed according to the dynamic change of shift register topological structure, the control sequence after change is exported to shifting Bit register topological structure；

After the clock control SR topological structure of entire digital circuit trigger is built in completion, to be opened up according to established SR It flutters structure and generates corresponding clock selecting control sequence in control sequence generator block, this sequence can be in module Inside, which generates and control is added, to improve, and can also be input from the outside by the port CI, meet different application demands.

Step 4: control sequence is sent to clock selection circuit: shift register topological structure is by the control sequence after change Each the clock selection circuit of corresponding doubleclocking trigger is sent to as clock selection signal；

After having control sequence, each doubleclocking trigger is sent for the sequence by external TCLK clock by turn Clock selection circuit is completed to control the clock selecting of doubleclocking trigger.

Step 5: selected clock trigger work clock: doubleclocking trigger is according to clock selection signal in two-way different frequencies Selected in the clock signal of rate wherein all the way clock signal as work clock；

Step 6: functional simulation and timing inspection: functional simulation being carried out to low power consuming clock dynamic management circuit and timing is examined It looks into；

It, be to the netlist of completion after the trigger replacement and quick, Slow Clock selection of completing entire digital circuit for the first time File carries out functional simulation, sees whether meet the needs of design function or design function has occurred intolerable change Become.Time-Series analysis is carried out to the netlist later, guarantee that design meets timing requirements.

Step 7: generating netlist: raw to the low power consuming clock dynamic management circuit for meeting functional simulation and timing inspection requirements At netlist.

If the netlist design after change is not able to satisfy the demand of design function, need on this basis to SR topological structure Design planning is re-started with control sequence generator, is iterated, until design structure is best, and meets initial function need It asks.

Finally, generative circuit net meter file, so that the rear end of digital integrated electronic circuit is designed.

The foregoing is merely a kind of specific embodiments of the invention.Scope of protection of the present invention is not limited thereto, In the technical scope disclosed by the present invention, any changes or substitutions that can be easily thought of by anyone skilled in the art, It should be covered by the protection scope of the present invention.

Claims (2)

1. a kind of low power consuming clock dynamic management circuit based on doubleclocking trigger, it is characterised in that: triggered including doubleclocking Device, shift register topological structure and control sequence generator, the doubleclocking trigger include main latch, from latch and Clock selection circuit, main latch is for receiving external data, and output is extremely from latch after latch；From latch for exporting number According to；Clock selection circuit is used to receive the clock signal of two-way different frequency, selects wherein under the control of clock selection signal Clock signal is exported respectively to main latch and from latch all the way；The clock signal of the two-way different frequency is one quick Clock signal and a slow clock signal；Control sequence generator is used to receive control sequence under the control of external timing signal Column, and control sequence is changed according to the dynamic change of shift register topological structure, the control sequence after change is exported to shifting Bit register topological structure；Shift register topological structure be used for will change after control sequence each as clock selecting Signal is exported to one or more doubleclocking trigger；Doubleclocking trigger is used for according to clock selection signal in two-way difference Selected in the clock signal of frequency wherein all the way clock signal as work clock；The control sequence is according to shift register Topological structure generates.

2. a kind of low power consuming clock dynamic management approach based on doubleclocking trigger, which comprises the following steps:

Step 1: classifying according to the functional requirement of low power consuming clock dynamic management circuit to all doubleclocking triggers；

Step 2: of a sort doubleclocking trigger will be belonged to and be connected to the same shift register, form shift register topology Structure；

Step 3: control sequence generator receives control sequence under the control of external timing signal, and is opened up according to shift register The dynamic change change control sequence for flutterring structure, the control sequence after change is exported to shift register topological structure；It is described Control sequence according to shift register topological structure generate；

Step 4: shift register topological structure sends each of the control sequence after change to as clock selection signal The clock selection circuit of corresponding doubleclocking trigger；

Step 5: doubleclocking trigger selects wherein all the way in the clock signal of two-way different frequency according to clock selection signal Clock signal as work clock, the clock signal of the two-way different frequency be a fast clock signal and one at a slow speed when Clock signal；

Step 6: functional simulation and timing inspection are carried out to low power consuming clock dynamic management circuit；

Step 7: to the low power consuming clock dynamic management circuit evolving netlist for meeting functional simulation and timing inspection requirements.