CN106529067A - Double-clock flip-flop, and low-power clock dynamic management circuit and management method - Google Patents

Abstract

The invention discloses a double-clock flip-flop, a low-power clock dynamic management circuit and a low-power clock dynamic management method, and relates to the field of integrated circuit design. The method comprises the steps of classifying flip-flops by function, forming an SR topological structure, generating a clock control sequence, sending the control sequence to a clock selection circuit, selecting a working clock of a flip-flop, performing function simulation and time sequence check, and generating a netlist. The invention provides a clock flip-flop structure capable of performing working clock selection; through control of clock selection bits, the working clock of the flip-flop can be adjusted to a quick clock or a slow clock; and the working clock frequency of the flip-flop is flexibly adjusted according to a design function demand of a digital circuit, so that the correctness of the design function can be ensured, the working frequencies of part of circuits in design are reduced to the maximum extent, and the power consumption is reduced.

Description

A kind of doubleclocking trigger, low power consuming clock dynamic management circuit and management method

Technical field

The present invention relates to IC design field, more particularly to a kind of doubleclocking trigger, based on doubleclocking trigger Low power consuming clock dynamic management circuit and management method.

Background technology

CMOS technology is occupied an leading position in VLSI designs at present.As integrated circuit constantly develops and new work The continuous employing of skill so that the integrated level more and more higher of circuit, while also obtain higher system clock frequency.It is highly integrated Degree, high clock frequency and undersized technique have inevitably led to the increase of circuit power consumption.Caused by increasing because of power consumption Series of problems, finally makes the size of power consumption become a leading indicator for weighing modern integrated circuits.Low power dissipation design also into One emergency technical demand of IC design.And power consumption, either dynamic or static state, have become constraint One key factor of device performance, life-span and integrated level.

In low-power consumption VLSI Design, wherein a piece highly significant is how to reduce same clock network phase The power consumption of this partial circuit for closing, because there is data to show, the power consumption of this part circuit accounts for the 20%-50% of whole chip power-consumption As many as.And the wherein power consumption consumed by trigger accounts for the 90% of clock network power consumption.Therefore reached by reducing trigger power consumption Reduce chip total power consumption and seem very important.

Trigger is a basic digital circuit component simultaneously, and they are employed for digital circuit generally and in large quantities and set In meter.As they are large number of, therefore the Save power consumption of any point of each trigger can cause a digital circuit The considerable Save power consumption of system, this is also a major reason for carrying out Low Power Flip-flops research.

The content of the invention

The technical problem to be solved is to provide a kind of doubleclocking trigger, the low work(based on doubleclocking trigger Time-consuming clock dynamic management circuit and management method, reduce trigger power consumption and then reduce the purpose of chip total power consumption.

To solve above-mentioned technical field, the technical solution used in the present invention is：A kind of doubleclocking trigger, including main latch Device, from latch, clock selection circuit, main latch is used to receive external data, is exported to from latch after latch；From latch Device is used for output data；Clock selection circuit is used for the clock signal for receiving two-way different frequency, in the control of clock selection signal Wherein clock signal is exported to main latch and from latch the lower selection of system respectively all the way.

A kind of low power consuming clock dynamic based on doubleclocking trigger manages circuit, including doubleclocking trigger, displacement are posted Storage topological structure and control sequence generator, control sequence generator are controlled for receiving under the control of external timing signal Sequence, and according to the dynamic change of shift register topological structure change control sequence, by the control sequence after change export to Shift register topological structure；Shift register topological structure for using the control sequence after change each as clock select Signal output is selected to one or more doubleclocking trigger；Doubleclocking trigger for according to clock selection signal in two-way not Select in the clock signal of same frequency wherein all the way clock signal as work clock；Described control sequence is according to shift LD Device topological structure is produced.

A kind of low power consuming clock dynamic management approach based on doubleclocking trigger, comprises the following steps：

Step 1：Functional requirement according to low power consuming clock dynamic management circuit is classified to all doubleclocking triggers；

Step 2：Of a sort doubleclocking trigger will be belonged to and be connected to same shift register, form shift register Topological structure；

Step 3：Control sequence generator receives control sequence under the control of external timing signal, and according to shift LD The dynamic change change control sequence of device topological structure, the control sequence after change is exported to shift register topological structure； Described control sequence is produced according to shift register topological structure；

Step 4：Shift register topological structure using the control sequence after change each as clock selection signal send out It is sent to the clock selection circuit of corresponding doubleclocking trigger；

Step 5：Doubleclocking trigger is selected wherein in the clock signal of two-way different frequency according to clock selection signal Clock signal is used as work clock all the way；

Step 6：Functional simulation and sequential inspection are carried out to low power consuming clock dynamic management circuit；

Step 7：Low power consuming clock dynamic management circuit evolving netlist to meeting functional simulation and sequential inspection requirements.

Using the beneficial effect that above-mentioned technical proposal is brought it is：

1. the invention provides a kind of new trigger structure that can be operated clock selecting, by clock selecting The control of position, the work clock that can adjust trigger are quick clock or Slow Clock；

2. the present invention can be adjusted flexibly the working clock frequency of trigger according to Design of Digital Circuit functional requirement, can Ensure the correctness of design function, while farthest reducing the operating frequency of partial circuit in design, reduce power consumption；

3. the invention provides low-power consumption Dynamic clock management circuit structure to trigger in design, by control sequence Generator and rational control circuit topological structure, reach and each trigger are precisely controlled.

Description of the drawings

Fig. 1 is the low power consuming clock dynamic management approach flow chart of the present invention；

Fig. 2 is the structural representation of the doubleclocking trigger of the present invention；

Fig. 3 is the low power consuming clock dynamic management circuit structure figure of the present invention.

Specific embodiment

As shown in figure 1, a kind of low power consuming clock dynamic management approach based on doubleclocking trigger, including walking in detail below Suddenly：

Step 1：By function classification trigger：During according to the functional requirement of low power consuming clock dynamic management circuit to all pairs Ms filp flop is classified；

In the present embodiment, after Design of Digital Circuit carries out logic synthesis, part or all of in the netlist that will be generated Novel low power consumption doubleclocking trigger (as shown in Figure 2) in trigger alternative costs invention.The doubleclocking trigger with it is common The difference of trigger is that it includes two input end of clock mouths (Slow Clock port and quick clock port), when double The structure i.e. clock selection circuit of similar clock selector is embedded in ms filp flop, through the low and high level of clock selecting port Change, the work clock that can flexibly select doubleclocking trigger are Slow Clock or quick clock.

Step 2：Form SR topological structures：Of a sort doubleclocking trigger will be belonged to and be connected to same shift LD Device, forms shift register topological structure；

An i.e. SR of class shift register cell can be mounted to open up outside the clock selection signal end of each doubleclocking trigger Structure (as shown in Figure 3) is flutterred, these are that SR topological structures can be built according to the difference of each doubleclocking trigger function demand Rational topological structure, is controlled by with different levels series connection, can meet the clock of various complicated architectures in Design of Digital Circuit Select control.In concrete control process, the control sequence that control sequence generator sends is input to SR topology knots by CO ports Structure, to the trigger of whole digital circuit is completed in most short clock periodicity quickly, Slow Clock select, it is ensured that number The power consumption of the reduction trigger of high degree while word circuit function.

Step 3：Clock control sequence is produced：Control sequence generator receives control sequence under the control of external timing signal Row, and control sequence is changed according to the dynamic change of shift register topological structure, the control sequence after change is exported to shifting Bit register topological structure；

After completing to build the clock control SR topological structures of whole digital circuit trigger, to be opened up according to established SR Flutter structure and corresponding clock selecting control sequence is produced in control sequence generator block, this sequence can be in module It is internal to produce and add control to improve, it is also possible to by CI ports by outside input, to meet different application demands.

Step 4：Control sequence is sent to clock selection circuit：Shift register topological structure is by the control sequence after change Each the clock selection circuit of corresponding doubleclocking trigger is sent to as clock selection signal；

After possessing control sequence, the sequence is sent to by turn by each doubleclocking trigger by outside TCLK clocks Clock selection circuit, completes the clock selecting to doubleclocking trigger and controls.

Step 5：Selected clock trigger work clock：Doubleclocking trigger is according to clock selection signal in the different frequencies of two-way Select in the clock signal of rate wherein all the way clock signal as work clock；

Step 6：Functional simulation and sequential inspection：Functional simulation and sequential inspection are carried out to low power consuming clock dynamic management circuit Look into；

The trigger for completing whole digital circuit for the first time is replaced and after quick, Slow Clock is selected, be to the netlist that completes File carries out functional simulation, sees whether the demand or design function that whether meet design function there occurs intolerable changing Become.Time-Series analysis to be carried out to the netlist afterwards, it is ensured that design meets timing requirements.

Step 7：Generate netlist：Low power consuming clock dynamic management circuit life to meeting functional simulation and sequential inspection requirements Into netlist.

If the netlist design after change can not meet the demand of design function, need on this basis to SR topological structures Design planning is re-started with control sequence generator, is iterated, until design structure is optimal, and meet initial function need Ask.

Finally, generative circuit net meter file, so that the rear end of digital integrated electronic circuit is designed.

The foregoing is only a kind of specific embodiment of the present invention.Protection scope of the present invention is not limited thereto, Any those familiar with the art the invention discloses technical scope in, the change or replacement that can be readily occurred in, Should all be included within the scope of the present invention.

Claims (3)

1. a kind of doubleclocking trigger, including main latch and from latch, it is characterised in that：Also include clock selection circuit, Main latch is used to receive external data, is exported to from latch after latch；It is used for output data from latch；Clock selecting electricity Road is used to receive the clock signal of two-way different frequency, and wherein clock signal point all the way is selected under the control of clock selection signal Do not export to main latch and from latch.

2. a kind of low power consuming clock dynamic based on doubleclocking trigger manages circuit, it is characterised in that：Including such as claim 1 Described doubleclocking trigger, shift register topological structure and control sequence generator, control sequence generator are used for outside Control sequence is received under the control of portion's clock signal, and according to the dynamic change of shift register topological structure change control sequence Row, the control sequence after change is exported to shift register topological structure；After shift register topological structure is used to change Each of control sequence export to one or more doubleclocking trigger as clock selection signal；Doubleclocking trigger For according to clock selection signal select in the clock signal of two-way different frequency wherein all the way clock signal as work when Clock；Described control sequence is produced according to shift register topological structure.

3. a kind of low power consuming clock dynamic management approach based on doubleclocking trigger, it is characterised in that comprise the following steps：

Step 1：Functional requirement according to low power consuming clock dynamic management circuit is classified to all doubleclocking triggers；

Step 2：Of a sort doubleclocking trigger will be belonged to and be connected to same shift register, form shift register topology Structure；

Step 3：Control sequence generator receives control sequence under the control of external timing signal, and is opened up according to shift register The dynamic change change control sequence of structure is flutterred, the control sequence after change is exported to shift register topological structure；It is described Control sequence according to shift register topological structure produce；

Step 4：Each of control sequence after change is sent to by shift register topological structure as clock selection signal The clock selection circuit of corresponding doubleclocking trigger；

Step 5：Doubleclocking trigger is selected in the clock signal of two-way different frequency wherein all the way according to clock selection signal Clock signal is used as work clock；

Step 6：Functional simulation and sequential inspection are carried out to low power consuming clock dynamic management circuit；

Step 7：Low power consuming clock dynamic management circuit evolving netlist to meeting functional simulation and sequential inspection requirements.