CN106486342B - 用于将绝缘衬底焊接在载体上的方法 - Google Patents

用于将绝缘衬底焊接在载体上的方法 Download PDF

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CN106486342B
CN106486342B CN201610607821.0A CN201610607821A CN106486342B CN 106486342 B CN106486342 B CN 106486342B CN 201610607821 A CN201610607821 A CN 201610607821A CN 106486342 B CN106486342 B CN 106486342B
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insulating substrate
solder
carrier
insulating
temperature
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CN106486342A (zh
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C·兰贝尔-里维埃
J-L·德波尔德
M·哈勒尔
N·A·扎纳特拉
V·瓦托罗梅
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Infineon Technologies AG
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Abstract

本发明涉及一种用于借助预先给定的焊料(4)将绝缘衬底(2)焊接在载体(3)的衬底安装部段(32)上的方法,其中绝缘衬底(2)具有介电的绝缘载体(20),上侧(2t)以及与上侧(2t)对置的下侧(2b)。在该方法中根据标准选择绝缘衬底(2),该标准由此推断,即当绝缘衬底(2)具有焊料(4)的固相线温度时,绝缘衬底(2)具有正的不均匀度(UE2)。在绝缘衬底(2)的下侧(2b)处将所选择的绝缘衬底(2)与衬底安装部段(32)焊接在一起,使得固化的焊料(4)在焊接之后贯穿地从绝缘衬底(2)的下侧(2b)延伸到衬底安装部段(32);在焊接之前或之后,在绝缘衬底(2)的上侧(2t)装配至少一个半导体芯片(1)。

Description

用于将绝缘衬底焊接在载体上的方法
技术领域
本发明涉及一种用于将绝缘衬底焊接在载体上的方法。
背景技术
绝缘衬底通常用作用于电路的电路载体并且例如为了制造功率半导体模块而借助于大面积的焊接连接被焊接在载体上。一般地,绝缘衬底由两个或多个组成部分接合而成。取决于所涉及的接合过程以及(通常是有不同的)组成部分的热延展系数,电路载体能够具有很难事先预测的温度相关的曲率。被相同地构造的两个衬底,当它们假定根据相同的制造方法以相同的过程参数被制造并且因此应该展现实质上相同的温度相关的曲率特性,然而其自身在之后也能够展现出不同的温度相关的曲率特性。不能预测的温度相关的曲率特性引起,为了将绝缘衬底焊接在载体上而使用的焊料的厚度以及焊料的厚度分布也是不能预测的。这例如可以导致该焊料在电路载体与功率半导体芯片装配在一起的区域中具有局部的增大的厚度。因此导致在绝缘衬底和载体之间的局部的热过渡电阻,当在功率半导体芯片中升高的工作热量经由绝缘衬底和焊料被输送到载体时,这是不利的。
一旦具有十分不均匀的厚度分布的焊料层被视作对于特定的结构不利时,则在焊料层的制造之后需要伦琴射线技术的检查,其往往与较大的耗费相关。当在检查中确定了待均匀的厚度分布的焊料层,需放弃与载体、与绝缘衬底以及(如存在)与绝缘衬底装配在一起的电子组件或对它们进行耗费的再加工。
发明内容
本发明的目的在于,提供一种用于将绝缘衬底焊接在载体上的方法,相比较现有技术的方法,该方法能够减少由于产生的焊料层的不均匀的厚度分布而导致的次品。
该目的通过一种用于将绝缘衬底焊接在载体的衬底安装部段上的方法来实现。本发明的实施方式和变型是从属权利要求的内容。
本发明的一个方面涉及用于借助预先给定的焊料将绝缘衬底焊接在载体的衬底安装部段上的方法。绝缘衬底具有介电的绝缘载体,上侧以及与上侧对置的下侧。在该方法中根据标准选择绝缘衬底,该标准由此推断,即当绝缘衬底具有焊料的固相线温度时,绝缘衬底具有正的不均匀度(Unebenheit)。在绝缘衬底的下侧处将所选择的绝缘衬底与衬底安装部段焊接在一起,使得固化的焊料在焊接之后贯穿地从绝缘衬底的下侧延伸到衬底安装部段;在焊接之前或之后,在绝缘衬底的上侧装配至少一个半导体芯片。
附图说明
本发明在下文中根据实施例并结合附图被进一步描述。在附图中的示图并不一定是按照比例尺绘制的。在附图中示出:
图1示出了载体和焊接在载体上的绝缘衬底的截面图,该绝缘衬底具有负的不均匀度。
图2示出了载体的具有衬底安装部段的侧面的俯视图。
图3示出了载体、绝缘衬底以及处在它们之间的焊料在焊接之前的截面图。
图4示出了载体、绝缘衬底以及使该载体和绝缘衬底材料配合地连接的焊料的截面图。
图5示出了具有两条曲线的图表,其示出了在温度循环的过程中,对于焊接适用的以及对于焊接不适用的绝缘衬底各自的不均匀度。
图6示出绝缘衬底的截面图,其具有负的不均匀度并且被挑出。
具体实施方式
图1示出了载体3和焊接在载体上的绝缘衬底2的截面图。载体3例如可以具有平坦的或近似平坦的平面的设计。载体3具有带有衬底安装部段32的上侧3t,在其上稍后焊接有绝缘衬底2.
载体3的厚度例如能够处于2mm至5mm的区域中更小或更大的值也是可能的。载体3例如可以由金属构成,或由金属-基质-复合材料(MMC-Material)。对于由金属制成的载体3来说适合的材料例如是铜、铜合金、铝或铝合金。同样载体3例如能够具有由铜、铜合金、铝或铝合金或其他材料制成的载体层。载体层为了更好的焊接性被设置有薄的涂层,其形成衬底安装部段32的背向载体层的侧面。对于为了更好的焊接性设置的涂层所适合的材料例如是镍、银、金和铂。这样的涂层的设置能够在载体层上借助电离、借助喷溅或借助气相沉积来实现。
绝缘衬底2包括介电的绝缘载体20,其被构造成平的薄板并且具有上部的主表面以及与其相对置的下部的主表面。在绝缘载体20的上部的主表面上安装有上部金属化层21,其选择性的用于构成导体轨道和/或导体面。此外在绝缘载体20的下部的主表面上,可选的设置有下部金属化层22,其为非结构化的或也可选的能够是结构化的。上部金属化层21的背向绝缘载体20的侧面形成绝缘衬底2的上侧2t。如果存在下部金属化层22,其背向绝缘载体20的侧面形成绝缘衬底2的下侧2b。通常上侧2t表示为绝缘衬底2的装配侧(也就是说其已经装配有一个或多个电子组件和/或待装配有一个或多个电子组件),绝缘衬底2的下侧2b与上侧2t对置。
金属化层21和22与绝缘载体20固定的并且材料配合的连接。特别是上部金属化层21能够通过其共同的朝向绝缘载体20的侧面与绝缘载体20固定的并且材料配合的连接。相应的,下部金属化层22也能够通过其共同的朝向绝缘载体20的侧面与绝缘载体20固定的并且材料配合的连接。
绝缘载体20是电绝缘的,其例如可以由陶瓷材料制成,例如氮化铝(AlN)、氧化铝(Al2O3)、氮化硅(Si3N4)、碳化硅(SiC)或氧化铍(BeO)。上部金属化层21和下部金属化层22例如能够由铜、铜合金、铝或铝合金制成。
根据一个实例绝缘衬底2例如能够是DCB-衬底(DCB=direct copper bonded,直接铜键合),其中通过表面氧化的、预先制成的铜薄膜通过DCB过程与陶瓷的绝缘载体20(例如氧化铝)连接,来制造上部金属化层21和下部金属化层22(如存在)。
图1示出了在起始温度T0,例如在室温下(20℃)的载体3和绝缘衬底2。在起始温度T0下绝缘载体20具有负的不均匀度UE2(T0)。在这种意义下,当绝缘载体20在其下侧2b处(如在图1中示出的)凹陷地弯曲时,绝缘载体20的不均匀度UE2为负。如果存在下部金属化层22,由此绝缘衬底2的下侧2b通过下部金属化层22的背向绝缘载体20的侧面给出。如果不存在下部金属化层22,下侧2b通过绝缘载体20的背向上部金属化层21的侧面给出。如果绝缘衬底2在另一种情况下在其下侧2b凸起地弯曲,那么其不均匀度UE2为正。不管绝缘衬底2不均匀度UE2为正还是为负,不均匀度UE2的值通过在两个平行的平面E1和E2之间的尽可能小的间距给出,在其之间下侧2b能够不仅紧贴着平面E1也紧贴着平面E2延伸,而不与平面E1与平面E2中的一个相交。
如图1同样可以获得的是,例如在本发明的所有其他的实施方式中,载体3能够在衬底安装部段32的区域中凹陷地弯曲。图2示出了载体的包括预先给定的衬底安装部段32的上侧3t的俯视图。衬底安装部段32的位置由点状线表示。衬底安装部段32例如能够具有最少为6cm2的面A32。
为了将绝缘衬底2焊接在衬底安装部段32上,要使用焊料4,其在图3中示出。焊料4能够被构造成软焊料并且具有小于450℃的液相线温度TL。为了焊接,将焊料4引入绝缘衬底2的下侧2b和衬底安装部段32之间。例如该焊料4能够作为焊膏涂覆在衬底安装部段32上或绝缘衬底2的下侧2b上。同样的焊料能够构造成预制的焊板(预成型焊料),其敷设在衬底安装部段32上。基本上,能够以任意的焊接技术实现焊接。例如焊接能够由负压(也就是相较于大气压力来说下降的压力)实现,例如在小于400hPa的绝对压力下,以避免形成空穴。
在任何情况下,焊料4为了焊接加热到超出其液相线温度TL,从而使其熔化。在液态的焊料4下,绝缘衬底2通过其自身的重量和/或微小的外部按压力沿着衬底安装部段32的方向按压,从而该液态的焊料4贯穿地从下侧2b延伸到衬底安装部段32。之后焊料4被冷却到其固相线温度TS之下,由此其被固化并且绝缘衬底2与衬底安装部段32进而与载体3形状适配地连接。同样的,该固化的焊料4贯穿地从下侧2b延伸到衬底安装部段32。图4示出了焊接在衬底安装部段32上的绝缘衬底2。在本发明的意义下,焊料4的固相线温度TS被视作为这样的焊料4的固相线温度TS,即当焊接绝缘衬底2和载体3时引起从绝缘衬底2和/或从载体3的材料的扩散的情况下,焊料4的固相线温度TS在本发明的意义下不改变。
能够在焊接期间或已经在之间将绝缘衬底2加热到温度T,其高于焊料4的固相线温度TS。其例如在图3中被示出,在图3的示例中绝缘衬底2被预加热,也就是说,在其与焊料4接触之前,其被加热到高于焊料4的固相线温度TS的温度T甚至被加热到高于焊料4的液相线温度TL。然而可选的是,绝缘衬底2首先与仍是固态的焊料4接触并且在之后才加热到高于焊料4的固相线温度TS的温度T甚至被加热到高于焊料4的液相线温度TL
如还在图3中示出的,绝缘衬底2能够在更高的温度T下,例如在高于焊料4的固相线温度TS的温度下具有正的不均匀度UE2,也就是说,存在UE2>0。当绝缘衬底2至少在更高的温度T下具有正的不均匀度UE2并且载体3在在衬底安装部段32的区域中凹陷地弯曲,下侧2b和衬底安装部段32在焊接期间至少几乎平行地延伸,由此,在焊接之后得到具有与传统方法相比比较均匀的厚度的焊料层。
由此本发明的方面在于,为了焊接在衬底安装部段32上只使用这样的绝缘载体20,其在其具有在之后用于焊接的焊料4的固相线温度TS时具有固有的正的不均匀度UE2。联系上下文,“固有的”含义在于没有外力作用在绝缘衬底2上。
在温度循环的变化走向中,绝缘衬底2的不均匀度UE2变化。其例如根据图5被进一步阐述。图5示出了具有实线和虚线的曲线的图标。这两条曲线示出了不同的绝缘衬底2,其分别从小于预先给定的焊料4的固相线温度TS的起始温度T0开始(例如在室温下20℃),被加热直到达到最大温度TMAX并且在之后再次冷却到预先给定的焊料4的固相线温度TS之下。该变化走向由箭头给出。
在起始温度T0下,两个绝缘衬底2均具有不均匀度UE2<0,也就是其在下侧2b处-如图1所示-凹陷地弯曲。随着温度T的升高,不均匀度UE2同样升高,其中首先存在的负的不均匀度UE2转变为正的不均匀度UE2,这在实线曲线中出现在大约120℃的情况下,而在虚线曲线中出现在大约175℃的情况下。该不均匀度UE2继续上升直到达到最大温度TMAX。总体来说,在从起始温度T0到达到最大温度TMAX的加热期间,不均匀度UE2的值连续地增大。在达到最大温度TMAX之后,绝缘衬底2再次冷却到预先给定的焊料4的固相线温度TS之下,例如冷却到起始温度T0
当绝缘衬底2第一次经受温度循环,也就是第一次从起始温度T0到最大温度TMAX的加热过程,以及在之后第一次从最大温度TMAX到焊料4的固相线温度TS之下,例如到起始温度T0冷却过程,第一次加热过程的曲线走向(也就是与温度相关的不均匀度UE2的变化走向)能够明显地与第一次冷却过程的曲线走向区分开。在接下来的每一次温度循环中(假设相同的起始温度T0和最大温度TMAX),与在相关的绝缘衬底2的第一次温度循环相比,其在这次温度循环中的加热过程的曲线走向与冷却过程的曲线走向彼此稍微存在偏差。
如本发明的发明人已经确定的,其他的温度循环的曲线走向(也就是具有相同的起始温度T0和最大温度TMAX的第二次以及所有其他的温度循环)以良好的近似接近第一次冷却过程的曲线走向。由此使得能够利用第一次或其他的温度循环的曲线走向,判定绝缘衬底2是否在高质量的焊接连接的构造下与载体3焊接在一起。
由此本发明的方面在于,根据标准选择适合与载体3焊接的绝缘衬底2,由此推断出该标准,即当绝缘衬底2具有焊料4的固相线温度时,绝缘衬底2具有正的不均匀度UE2。
在最简单的情况下,选出特定的绝缘衬底2由此实现,即从起始温度T0开始加热到最大温度TMAX并且在之后再次至少冷却到达到预先给定的(也就是在之后用来将绝缘衬底2与载体3焊接在一起的)焊料4的固相线温度TS。当在此确定,即绝缘衬底2,当其在冷却达到预先给定的焊料4的固相线温度TS时,具有正的不均匀度UE2,则其适合于与载体3的焊接。当不均匀度UE2在达固相线温度TS时为负或为零,则绝缘衬底2是不适合的并因此被挑出。在图6中示出了这种绝缘衬底2的实例。在图5中,实线的曲线示出了适合的绝缘衬底2,因为其在冷却期间在达到预先给定的焊料4的固相线温度TS时具有正的不均匀度UE2(在实例中例如大于100μm)。相反的,虚线的曲线示出了不适合并因此被挑出的绝缘衬底2,因为其在冷却期间在达到预先给定的焊料4的固相线温度TS时具有负的不均匀度UE2(在实例中大约是-60μm,也称作负的60μm)。
如本发明的发明人已经进一步确定的,绝缘衬底2示出取决于温度T的相近的不均匀度UE2的变化曲线,其中绝缘衬底被相同地构造并且源自同样的生产批次,也就是说,在其中上部以及如果存在的下部金属化层21以及22同时地施加在相同的过程中以及关于相关的绝缘载体20的相同的过程环境中。由此的另一种可能性在于,该绝缘衬底2由相同的生产批次的绝缘衬底2中作为适合于与载体3进行焊接的而被选择,如果在包括来自该生产批次的N个样本-绝缘衬底(Stichproben-Isoliersubstrate)的数量的样本的情况下,对于N个样本-绝缘衬底中的每一个确定,N个样本-绝缘衬底,当其从小于焊料4的固相线温度TS的起始温度T0开始加热到高于焊料4的液相线温度TL的给定的最大温度TMAX并且在之后被冷却,使得绝缘衬底2再次达到焊料4的所述固相线温度TS,在再次达到焊料4的所述固相线温度TS的情况下具有正的不均匀度UE2。另外的表述意味着,当从带有生产批次的N个绝缘衬底2中的样本中,样本的每个绝缘衬底2都经受上述的温度循环,并当确定了,样本的绝缘衬底2中的每一个适合用于与载体3的焊接,则该生产批次的全部绝缘衬底2被视作适合用于与载体3的焊接。N例如能够是等于1,大于或等于1,大于或等于2,大于或等于3等等。可选的或附加的,N至少为制造批次的绝缘衬底2的数量的十分之一。
一旦确定了,绝缘衬底2适合用于与载体3的焊接,绝缘衬底2就能够与载体3焊接在一起。在此绝缘衬底2在其使用预先给定的焊料4与载体3焊接在一起的期间是未装配的,或者其可以在焊接之前装配有一个或多个电子组件。图1、3和4示例性地示出了用虚线表示的电子组件,例如二极管、或可控的半导体开关例如IGBT(绝缘栅双极型晶体管),MOSFET(金属氧化物半导体场效应晶体管),JFET(结型场效应晶体管),半导体闸流管。在所有所谓的实例中,其可以特别是所谓的垂直组件,在其背向绝缘衬底2的下侧处(例如借助焊接、烧结或粘合连接)导电地与上部金属化层21的部段连接。此外,这种垂直组件能够在其背向绝缘衬底2的上侧处以任意的方式导电地连接并且例如与上部金属化层21的其他部段或半导体模块的其他部分连接。在图1、3、4中示例性地示出了这种键合线连接,其中键合线8通过导线键合在键合位置处直接地键合在组件1的上侧的金属化部处,以及在其他的键合位置直接地键合在上部金属化层21的其他部段处。超声线键合特别地适合作为线键合方法。
所有上述的方法可以选择性地在考虑下列的标准中的一个或多个来实施:
(a)在焊接期间,焊料4能够被加热到预先给定的最大温度TMAX
(b)预先给定的最大温度TMAX能够至少为190℃。
(c)焊料4的固相线温度TS能够至少为180℃,和/或小于或等于350℃。
(d)上部金属化层21的厚度能够至少为0.15mm,和/或小于或等于1.5mm。
(e)如存在下部金属化层22,其厚度能够至少为0.15mm,和/或小于或等于1.5mm。
(f)绝缘载体20的厚度能够至少为0.2mm,和/或小于或等于1.5mm。
(g)载体3的厚度能够至少为2mm,和/或小于或等于5mm。
(h)适用于与载体3焊接在一起的绝缘衬底2的下侧2b,能够在当其从最大温度TMAX冷却到焊料4的固相线温度TS时,在达到焊料4的固相线温度TS的情况下具有至少10μm的正的不均匀度。

Claims (10)

1.一种用于借助预先给定的焊料(4)将绝缘衬底(2)焊接在载体(3)的衬底安装部段(32)上的方法,其中所述绝缘衬底(2)具有介电的绝缘载体(20),上侧(2t)以及与所述上侧(2t)对置的下侧(2b),并且其中所述方法包括:
根据标准选择绝缘衬底(2),所述标准由当所述绝缘衬底(2)具有所述焊料(4)的固相线温度时,所述绝缘衬底(2)具有正的不均匀度(UE2)来推断;
在所述绝缘衬底(2)的所述下侧(2b)处将所选择的绝缘衬底(2)与所述衬底安装部段(32)焊接在一起,使得固化的所述焊料(4)在焊接之后贯穿地从所述绝缘衬底(2)的所述下侧(2b)延伸到所述衬底安装部段(32);
在所述焊接之前或之后,在所述绝缘衬底(2)的所述上侧(2t)装配至少一个半导体芯片(1),其中进行所述选择所依据的所述标准或者在于,
在所述焊接之前,所选择的绝缘衬底(2)从小于所述焊料(4)的所述固相线温度(TS)的起始温度(T0)开始加热到高于所述焊料(4)的液相线温度(TL)的预先给定的最大温度(TMAX)并且在之后被冷却,使得所选择的绝缘衬底(2)再次达到所述焊料(4)的所述固相线温度(TS),并且使得所选择的绝缘衬底(2)基于确定被选择,即在再次达到所述焊料(4)的所述固相线温度(TS)的情况下,其具有正的不均匀度(UE2);或者在于,
在所述焊接之前,来自生产批次中的包括N个样本-绝缘衬底的样本中的每一个从小于所述焊料(4)的所述固相线温度(TS)的起始温度(T0)开始加热到高于所述焊料(4)的液相线温度(TL)的预先给定的最大温度(TMAX)并且在之后被冷却,使得所选择的绝缘衬底(2)再次达到所述焊料(4)的所述固相线温度(TS),并且使得所选择的绝缘衬底(2)基于确定从生产批次中被选择,即N个样本-绝缘衬底中的每一个在再次达到所述焊料(4)的所述固相线温度(TS)的情况下具有正的不均匀度(UE2)。
2.根据权利要求1所述的方法,其中在再次达到所述焊料(4)的所述固相线温度(TS)的情况下,所述绝缘衬底(2)具有的正的不均匀度(UE2)至少为10μm。
3.根据权利要求1或2所述的方法,所述焊料(4)在所述焊接期间被加热到所述预先给定的最大温度(TMAX)。
4.根据权利要求1或2所述的方法,所述预先给定的最大温度(TMAX)至少为400℃。
5.根据权利要求1或2所述的方法,其中
所述衬底安装部段(32)具有至少为6cm2的面(A32);以及
在所述焊接之后,固化的所述焊料(4)邻近所述衬底安装部段(32)的每个位置。
6.根据权利要求1或2所述的方法,其中所述绝缘载体(20)具有陶瓷或由陶瓷构成。
7.根据权利要求1或2所述的方法,所述绝缘衬底(2)具有上部金属化层(21),所述上部金属化层(21)被施加在所述绝缘载体(20)上并且所述上部金属化层(21)背向所述绝缘载体(20)的侧面形成所述绝缘载体(20)的所述上侧(2t)。
8.根据权利要求1或2所述的方法,其中
所述绝缘载体(20)由氧化铝组成;
所述绝缘衬底(2)具有由铜组成的上部金属化层(21),所述上部金属化层(21)直接与所述绝缘载体(20)连接并且所述上部金属化层(21)背向所述绝缘载体(20)的侧面形成所述绝缘载体(20)的所述上侧(2t);
所述绝缘衬底(2)具有由铜组成的下部金属化层(22),所述下部金属化层(22)直接与所述绝缘载体(20)连接并且所述下部金属化层(22)背向所述绝缘载体(20)的侧面形成所述绝缘载体(20)的所述下侧(2b)。
9.根据权利要求8所述的方法,所述绝缘衬底(2)具有下部金属化层(22),所述下部金属化层(22)被施加在所述绝缘载体(20)上并且所述下部金属化层(22)背向所述绝缘载体(20)的侧面形成所述绝缘载体(20)的所述下侧(2b)。
10.根据权利要求1或2所述的方法,所述载体(3)在所述衬底安装部段(32)的区域中凹陷地弯曲。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08288637A (ja) * 1995-04-13 1996-11-01 Matsushita Electric Ind Co Ltd 電子部品および電子部品の半田付け方法
WO2012172251A1 (fr) * 2011-06-16 2012-12-20 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede pour la realisation d'un composant microelectronique courbe par effet bilame, et composant microelectronique ainsi obtenu
CN103920956A (zh) * 2013-01-11 2014-07-16 无锡华润安盛科技有限公司 一种回流工艺焊接方法
CN104084658A (zh) * 2014-07-01 2014-10-08 北京工业大学 一种镁合金与钢的接触反应扩散钎焊连接方法
CN104254909A (zh) * 2012-04-27 2014-12-31 日产自动车株式会社 半导体装置的制造方法、隔热负荷夹具及其设置方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5461774A (en) 1994-03-25 1995-10-31 Motorola, Inc. Apparatus and method of elastically bowing a base plate
JP3216620B2 (ja) * 1998-11-11 2001-10-09 日本電気株式会社 半導体装置
US6803653B1 (en) * 2001-12-07 2004-10-12 Advanced Micro Devices, Inc. Apparatus for suppressing packaged semiconductor chip curvature while minimizing thermal impedance and maximizing speed/reliability
JP4692708B2 (ja) 2002-03-15 2011-06-01 Dowaメタルテック株式会社 セラミックス回路基板およびパワーモジュール
JP4793622B2 (ja) 2005-03-04 2011-10-12 日立金属株式会社 セラミックス回路基板およびパワーモジュール並びにパワーモジュールの製造方法
FR2962594B1 (fr) * 2010-07-07 2012-08-31 Soitec Silicon On Insulator Procede de collage par adhesion moleculaire avec compensation de desalignement radial
EP3057125B1 (en) * 2013-10-10 2020-09-30 Mitsubishi Materials Corporation Substrate for heat sink-equipped power module, and production method for same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08288637A (ja) * 1995-04-13 1996-11-01 Matsushita Electric Ind Co Ltd 電子部品および電子部品の半田付け方法
WO2012172251A1 (fr) * 2011-06-16 2012-12-20 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede pour la realisation d'un composant microelectronique courbe par effet bilame, et composant microelectronique ainsi obtenu
CN104254909A (zh) * 2012-04-27 2014-12-31 日产自动车株式会社 半导体装置的制造方法、隔热负荷夹具及其设置方法
CN103920956A (zh) * 2013-01-11 2014-07-16 无锡华润安盛科技有限公司 一种回流工艺焊接方法
CN104084658A (zh) * 2014-07-01 2014-10-08 北京工业大学 一种镁合金与钢的接触反应扩散钎焊连接方法

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