CN106469690B - 电子封装件及其制法 - Google Patents

电子封装件及其制法 Download PDF

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Publication number
CN106469690B
CN106469690B CN201510534098.3A CN201510534098A CN106469690B CN 106469690 B CN106469690 B CN 106469690B CN 201510534098 A CN201510534098 A CN 201510534098A CN 106469690 B CN106469690 B CN 106469690B
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electronic component
electronic
encapsulated layer
packing piece
line structure
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CN106469690A (zh
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程吕义
马光华
陈仕卿
吕长伦
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Abstract

本申请公开了一种电子封装件及其制法，该电子封装件包括：第一线路结构、设于该第一线路结构表面上的第一电子元件、包覆这些第一电子元件的第一封装层、形成于该第一线路结构表面上并位于该第一封装层中的第一导电元件、包覆该第一电子元件与该第一导电元件的第一封装层、以及形成于该第一封装层上并电性连接该第一导电元件的第二线路结构。通过直接将高I/O功能的电子元件接置于该线路结构上，因而不需使用一含核心层的封装基板，故可减少该电子封装件的厚度。

Description

电子封装件及其制法
技术领域
本发明涉及一种电子封装件，特别是涉及一种具轻薄短小化的电子封装件及其制法。
背景技术
随着电子产业的蓬勃发展，电子产品也逐渐迈向多功能、高性能的趋势。目前应用于芯片封装领域的技术，例如芯片尺寸构装(Chip Scale Package，简称CSP)、芯片直接贴附封装(Direct Chip Attached，简称DCA)或多芯片模组封装(Multi－Chip Module，简称MCM)等覆晶型态的封装模组、或将芯片立体堆迭化整合为三维积体电路(3D IC)芯片堆迭技术等。
图1为现有3D芯片堆迭的半导体封装件1的剖面示意图。如图1所示，提供一硅中介板(Through Silicon interposer，简称TSI)10，该硅中介板10具有相对的置晶侧10a与转接侧10b、及连通该置晶侧10a与转接侧10b的多个导电硅穿孔(Through-silicon via，简称TSV)100，且该转接侧10b上具有多个线路重布层(Redistribution layer，简称RDL)101。将间距较小的半导体芯片19的电极垫190通过多个焊锡凸块102电性结合至该置晶侧10a上，再以底胶192包覆这些焊锡凸块102，且形成封装胶体18于该硅中介板10上，以覆盖该半导体芯片19。于该线路重布结构101上通过多个如凸块的导电元件103电性结合间距较大的封装基板17的焊垫170，并以底胶172包覆这些导电元件103。
制作该半导体封装件1时，先将该半导体芯片19置放于该硅中介板10上，再将该硅中介板10以这些导电元件103接置于该封装基板17上，之后形成该封装胶体18。
然而，现有半导体封装件1的制法中，使用该硅中介板10作为该半导体芯片19与该封装基板17之间信号传递的介质，因需具备一定深宽比的控制(即该导电硅穿孔100的深宽比为100um/10um)，才能制作出适用的硅中介板10，因而往往需耗费大量制程时间及化学药剂的成本，进而提高制程难度及制作成本。
此外，该封装基板17具有含玻纤材料的核心层，致使该封装基板17厚度相当厚，因而不利于产品的轻薄短小化。
又，当该半导体芯片19具有细线宽线距的高I/O数时，则需加大该硅中介板10的面积，因而相对应的封装基板17的面积也需加大，故不利于产品的轻薄短小化。
因此，如何克服上述现有技术的种种问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺点，本发明提供一种电子封装件及其制法，可减少该电子封装件的厚度
本发明的电子封装件，包括：第一线路结构，其具有相对的第一表面及第二表面；第一电子元件，其设于该第一线路结构的第一表面上；第一封装层，其形成于该第一线路结构的第一表面上，以包覆该第一电子元件；第一导电元件，其形成于该第一线路结构的第一表面上并位于该第一封装层中，且令该第一导电元件外露于该第一封装层；以及第二线路结构，其形成于该第一封装层上并电性连接该第一导电元件。
前述的电子封装件中，该第一封装层包覆该第一导电元件。
前述的电子封装件中，还包括第二电子元件，其设于该第一封装层上并电性连接该第二线路结构。又包括形成于该第一封装层上的第二封装层，其包覆该第二电子元件。
前述的电子封装件中，该第一封装层形成有开口，以令部分该第一线路结构的第一表面外露于该开口，且于外露出该开口中的第一线路结构上设有第三电子元件。例如，该第三电子元件电性连接该第二线路结构或该第二电子元件。
前述的电子封装件中，该第一封装层形成有开口，以令部分该第一线路结构的第一表面外露于该开口，且该第一导电元件容置于该开口中并连结至该第二线路结构。还包括形成于该第一封装层上与该开口中的第二封装层，以包覆该第二电子元件与该第一导电元件。又，该第二封装层形成有至少一开孔，以令该第二电子元件的部分表面外露于该开孔，以供结合第四电子元件于该第二电子元件上。
本发明还提供一种电子封装件的制法，包括：提供一具有相对的第一表面及第二表面的第一线路结构；形成第一导电元件于该第一线路结构的第一表面上，且设置第一电子元件于该第一线路结构的第一表面上；形成第一封装层于该第一线路结构的第一表面上，以包覆该第一电子元件与该第一导电元件，且令该第一导电元件外露于该第一封装层；形成第二线路结构于该第一封装层上，且该第二线路结构电性连接该第一导电元件；以及设置第二电子元件于该第一封装层上，且该第二电子元件电性连接该第二线路结构。
前述的制法中，还包括形成第二封装层于该第一封装层上，以包覆该第二电子元件。
本发明还提供一种电子封装件的制法，包括：提供一具有相对的第一表面及第二表面的第一线路结构；设置第一电子元件于该第一线路结构的第一表面上；形成第一封装层于该第一线路结构的第一表面上，以包覆该第一电子元件，且该第一封装层形成有至少一开口，以令部分该第一线路结构的第一表面外露于该开口；形成第二线路结构于该第一封装层上；设置第二电子元件于该第一封装层上，且该第二电子元件电性连接该第二线路结构；以及形成多个第一导电元件于该第二线路结构上与外露出该开口中的第一线路结构上。
前述的制法中，该第一封装层形成有多个该开口，且部分该开口容置有该第一导电元件，而部分该开口中设有第三电子元件。例如，该第三电子元件电性连接该第二电子元件或该第二线路结构。
前述的制法中，还包括形成第二封装层于该第一封装层上与该开口中，以包覆该第二电子元件与这些第一导电元件。例如，该第二封装层形成有至少一开孔，以令该第二电子元件的部分表面外露于该开孔，俾供结合第四电子元件于该第二电子元件上。
另外，前述的电子封装件及两种制法中，还包括形成多个第二导电元件于该第一线路结构的第二表面上。
由上可知，本发明的电子封装件及其制法，主要通过直接将高I/O功能的第一电子元件接置于该第一线路结构上，因而不需使用一含核心层的封装基板，故可减少该电子封装件的厚度。
此外，通过该第一导电元件外露于该第一封装层，使该第一封装层上的第二电子元件可电性连接该第一导电元件，故该第一电子元件能电性连通至该第二电子元件，因而能缩小该电子封装件的面积。
附图说明
图1为现有半导体封装件的剖面示意图；
图2A至图2G为本发明的电子封装件的制法的第一实施例的剖面示意图；
图3A至图3C为本发明的电子封装件的制法的第二实施例的剖面示意图；以及
图3C’为本发明的电子封装件的制法的第三实施例的剖面示意图；其中，图3C”为图3C’的另一实施例。
附图标记说明
1 半导体封装件
10 硅中介板
10a 置晶侧
10b 转接侧
100 导电硅穿孔
101,211 线路重布层
102,231 焊锡凸块
103 导电元件
17 封装基板
170 焊垫
172,192,260 底胶
18 封装胶体
19 半导体芯片
190 电极垫
2,3,3’,3” 电子封装件
20 承载件
200 结合层
21 第一线路结构
21a 第一表面
21b 第二表面
210 介电层
22,22’,32,32’,32” 第一导电元件
23,23’ 第一电子元件
24,24’,34 第一封装层
25 第二线路结构
26,36 第二电子元件
27,37 第二封装层
28 第二导电元件
340,340’ 开口
33 第三电子元件
330,360 粘着材
370 开孔
39 第四电子元件。
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”及“一”等的用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2A至图2G为本发明的电子封装件2的制法的第一实施例的剖面示意图。
如图2A所示，提供一设有第一线路结构21的承载件20。
在本实施例中，该承载件20为半导体板体，例如硅晶圆(Si wafer)或玻璃，且该承载件20上具有一结合层200，以结合该第一线路结构21。例如，该结合层200为热化二氧化硅层(thermal SiO2 layer)、离形层或保护层。于本实施例中，该承载件20为硅晶圆，而该结合层200为热化二氧化硅层。
此外，该第一线路结构21具有相对的第一表面21a与第二表面21b，并以该第二表面21b结合于该结合层200上，且该第一线路结构21包含至少一介电层210及形成于该介电层210上的线路重布层211(Redistribution layer，简称RDL)。
如图2B所示，设置多个第一电子元件23,23’于该第一线路结构21的第一表面21a上，且形成至少一第一导电元件22于该第一线路结构21的第一表面21a上。接着，形成第一封装层24于该第一线路结构21的第一表面21a上，以包覆这些第一电子元件23,23’与第一导电元件22。
在本实施例中，该第一电子元件23,23’为主动元件、被动元件或其组合者，其中，该主动元件为例如半导体芯片，而该被动元件为例如电阻、电容及电感。
此外，该第一电子元件23,23’以覆晶方式电性连接该第一线路结构21。具体地，该第一电子元件23通过多个焊锡凸块231电性结合至该第一线路结构21的线路重布层211上，并选择性地以底胶(图略)固定于该第一线路结构21的第一表面21a上。或者，该第一电子元件23,23’也可以打线方式电性连接该第一线路结构21的线路重布层211。
又，该第一导电元件22以打线制程所形成的焊线，故该第一导电元件22呈现拱形体，即弧线状。然而，该第一导电元件也可为导电柱(图略)。
另外，形成该第一封装层24的材质为聚酰亚胺(polyimide，简称PI)、干膜(dryfilm)、环氧树脂(expoxy)或封装材。
如图2C所示，于该第一封装层24上进行整平制程，即移除该第一封装层24的部分材质，且同时移除该第一导电元件22的部分材质，使经移除部分材质的第一导电元件22’变成两条线段，且该该第一导电元件22’的端面外露于经整平后的该第一封装层24’的表面。
在本实施例中，以研磨方式移除该第一封装层24的部分材质，且这些第一电子元件23,23’未外露于该第一封装层24’的表面。
如图2D所示，形成第二线路结构25于该第一封装层24’上，且该第二线路结构25接触该第一导电元件22’。接着，对该第一电子元件23,23’、第一导电元件22’、第一与第二线路结构21,25进行电性测试。
在本实施例中，该第二线路结构25为线路重布层(RDL)。
此外，可先接置这些第一电子元件23,23’(芯片及被动元件)后，再进行线路测试，待确认第一与第二线路结构21,25正常后，再接置良好裸晶粒(Known Good Die，简称KGD)，即后述的第二电子元件26，以防止最终封装件发生良率不佳的问题。
如图2E所示，设置多个第二电子元件26于该第二线路结构25上，再形成第二封装层27于该第一封装层24’上，以包覆这些第二电子元件26。
在本实施例中，该第二电子元件26为主动元件、被动元件或其组合者，其中，该主动元件为例如半导体芯片，而该被动元件为例如电阻、电容及电感。例如，该第二电子元件26以覆晶方式电性连接该第二线路结构25，并选择性地以底胶260固定于该第二线路结构25上。当然，该第二电子元件26也可以打线方式电性连接该第二线路结构25。
此外，该第二封装层27的材质与该第一封装层24’的材质为相同或不相同，且形成该第二封装层27的材质为聚酰亚胺(polyimide，简称PI)、干膜(dry film)、环氧树脂(expoxy)或封装材。
如图2F所示，移除该承载件20及该结合层200，以外露该第一线路结构21的第二表面21b。
如图2G所示，形成多个第二导电元件28于该第一线路结构21的第二表面21b上。
在本实施例中，该第二导电元件28为焊球、金属凸块或金属针等，且结合于该第一线路结构21的线路重布层211上并电性连接该线路重布层211。
图3A至图3C为本发明的电子封装件3的制法的第二实施例的剖面示意图。本实施例与第一实施例的方式大致相同，主要差异在于第一导电元件32,32’,32”的制程，故以下仅详述相异处，而相同处不再赘述。
如图3A所示，接续图2A的制程(以下省略该承载件20及该结合层200的说明)，设置多个第一电子元件23于该第一线路结构21的第一表面21a上，再形成第一封装层34于该第一线路结构21的第一表面21a上，以包覆这些第一电子元件23。接着，于该第一封装层34上形成多个开口340,340’，以令该第一线路结构21的部分第一表面21a(或部分该线路重布层211)外露于这些开口340,340’。
在本实施例中，形成该第一封装层34的材质为聚酰亚胺(polyimide，简称PI)、干膜(dry film)、环氧树脂(expoxy)或封装材。
如图3B所示，形成第二线路结构25于该第一封装层34上，且设置多个第二电子元件26,36于该第二线路结构25上。
在本实施例中，部分该第二电子元件36通过粘着材360设于该第一封装层34上。
此外，在设置这些第二电子元件26,36时，可于部分该开口340’中的第一线路结构21的第一表面21a上通过粘着材330设置第三电子元件33。具体地，该第三电子元件33为主动元件、被动元件或其组合者，其中，该主动元件为例如半导体芯片，而该被动元件为例如电阻、电容及电感。
另外，在其它方式中，可先形成第二线路结构25于该第一封装层34上，再于该第一封装层34上形成多个开口340,340’。
如图3C所示，形成多个第一导电元件32,32’,32”于该第二线路结构25、外露于该开口340中的线路重布层211、第二电子元件26,36、与第三电子元件33上，且形成多个第二导电元件28于该第一线路结构21的第二表面21b上。
在本实施例中，该第一导电元件32,32’,32”以打线制程所形成的焊线，故该第一导电元件32,32’,32”呈现拱形体，即弧线状。
此外，该第二线路结构25通过该第一导电元件32电性连接该第一线路结构21的线路重布层211，且部分该第二电子元件26以覆晶方式电性连接该第二线路结构25，而部分该第二电子元件36以打线方式(即通过该第一导电元件32’)相互电性连接或电性连接至该第二线路结构25。
又，该第三电子元件33以打线方式(即通过该第一导电元件32”)分别电性连接该第二线路结构25与部分该第二电子元件36。
图3C’为本发明的电子封装件3’的制法的第三实施例的剖面示意图。本实施例与第二实施例的方式大致相同，主要差异在于增加第二封装层，故以下仅详述相异处，而相同处不再赘述。
如图3C’所示，形成一第二封装层37于该第一封装层34上与这些开口340,340’中，以包覆这些第二电子元件26,36、第三电子元件33与这些第一导电元件32,32’,32”。
在本实施例中，该第二封装层37的材质与该第一封装层34的材质为相同或不相同，且形成该第二封装层37的材质为聚酰亚胺(polyimide，简称PI)、干膜(dry film)、环氧树脂(expoxy)或封装材。
此外，如图3C”所示，也可于该第二封装层37上形成有至少一开孔370，以令该第二电子元件36的部分表面外露于该开孔370，以供结合第四电子元件39于该第二电子元件36上。具体地，该第四电子元件39为感测芯片(sensor chip)，但不以此为限。
本发明的制法中，通过直接将高I/O功能的电子元件(第一电子元件23,23’与第三电子元件33)接置于该第一线路结构21上，因而不需使用一含核心层的封装基板，故可减少该电子封装件2,3,3’,3”的厚度。
此外，通过直接将高I/O功能的电子元件接置于该第一线路结构21上，使各电子元件(第一电子元件23,23’与第三电子元件33)间的传导线距(Pitch)缩小。
又，通过该第一导电元件22’,32外露于该第一封装层24’,34，且利用打线技术(该第一导电元件22’,32,32’,32”)，使各层堆迭的电子元件(第一电子元件23,23’、第二电子元件26,36及第三电子元件33)得以电性连结，即该第一电子元件23,23’及第三电子元件33能电性连通至该第二电子元件26,36，因而能缩小该电子封装件2,3,3’,3”的体积，且能降低制作成本。
本发明提供一种电子封装件2,3,3’,3”，包括：第一线路结构21、第一电子元件23,23’、第一封装层24’,34、第一导电元件22’,32、第二线路结构25、以及第二电子元件26,36。
所述的第一线路结构21具有相对的第一表面21a及第二表面21b。
所述的第一电子元件23,23’设于该第一线路结构21的第一表面21a上。
所述的第一封装层24’,34形成于该第一线路结构21的第一表面21a上，以包覆这些第一电子元件23,23’。
所述的第一导电元件22’,32形成于该第一线路结构21的第一表面21a上并位于该第一封装层24’,34中，且令该第一导电元件22’,32外露于该第一封装层24’,34。
所述的第二线路结构25形成于该第一封装层24’,34上并电性连接该第一导电元件22’,32。
所述的第二电子元件26,36设于该第一封装层24’,34上并电性连接该第二线路结构25。
在一电子封装件2的实施例中，该第一封装层24’包覆该第一导电元件22’。
在一实施例中，所述的电子封装件2还包括形成于该第一封装层24’上的第二封装层27，其包覆这些第二电子元件26。
在一电子封装件3,3’,3”的实施例中，该第一封装层34形成有开口340’，以令该第一线路结构21的部分第一表面21a外露于该开口340’，且该开口340’中的第一线路结构21上设有第三电子元件33，使该第三电子元件33电性连接该第二线路结构25或该第二电子元件36。
在一电子封装件3,3’,3”的实施例中，该第一封装层34形成有开口340，以令该第一线路结构21的部分第一表面21a外露于该开口340，且该第一导电元件32容置于该开口340中并连结至该第二线路结构25。此外，该电子封装件3’,3”还包括形成于该第一封装层34上与该开口340中的第二封装层37，以包覆这些第二电子元件26,36与该第一导电元件32。又，该第二封装层37形成有至少一开孔370，以令该第二电子元件36的部分表面外露于该开孔370，以供结合第四电子元件39于该第二电子元件36上。
在一实施例中，所述的电子封装件2,3,3’,3”还包括形成于该第一线路结构21的第二表面21b上的多个第二导电元件28。
综上所述，本发明的电子封装件及其制法，通过直接将高I/O功能的电子元件接置于该第一线路结构上，因而不需使用一含核心层的封装基板，故可减少该电子封装件的厚度。
此外，通过该第一导电元件外露于该第一封装层，使该第一封装层上的第二电子元件可电性连接该第一导电元件，故该第一电子元件能电性连通至该第二电子元件，因而能缩小该电子封装件的面积。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (14)

1.一种电子封装件，其特征为，该电子封装件包括：
第一线路结构，其具有相对的第一表面及第二表面；
第一电子元件，其设于该第一线路结构的第一表面上；
第一封装层，其形成于该第一线路结构的第一表面上，以包覆该第一电子元件，其中，该第一封装层形成有第一开口，以令部分该第一线路结构的第一表面外露于该第一开口；
第二电子元件，其设于外露出该第一开口中的第一线路结构上；
第一导电元件，其形成于该第一线路结构的第一表面上并位于该第一封装层中，且令该第一导电元件外露于该第一封装层；以及
第二线路结构，其形成于该第一封装层上并电性连接该第一导电元件。
2.如权利要求1所述的电子封装件，其特征为，该第二电子元件电性连接该第二线路结构。
3.如权利要求1所述的电子封装件，其特征为，该第一封装层形成有第二开口，以令部分该第一线路结构的第一表面外露于该第二开口，且该第一导电元件容置于该第二开口中并连结至该第二线路结构。
4.如权利要求3所述的电子封装件，其特征为，该电子封装件还包括形成于该第二开口中的第二封装层，以包覆该第一导电元件。
5.如权利要求1所述的电子封装件，其特征为，该电子封装件还包括第三电子元件，其设于该第一封装层上并电性连接该第二线路结构。
6.如权利要求5所述的电子封装件，其特征为，该电子封装件还包括形成于该第一封装层上的第二封装层，其包覆该第三电子元件。
7.如权利要求5所述的电子封装件，其特征为，该电子封装件还包括结合于该第三电子元件上的第四电子元件。
8.如权利要求1所述的电子封装件，其特征为，该电子封装件还包括形成于该第一线路结构的第二表面上的多个第二导电元件。
9.如权利要求5所述的电子封装件，其特征为，该第二电子元件电性连接该第三电子元件。
10.一种电子封装件的制法，其特征为，该制法包括：
提供一具有相对的第一表面及第二表面的第一线路结构；
设置第一电子元件于该第一线路结构的第一表面上；
形成第一封装层于该第一线路结构的第一表面上，以包覆该第一电子元件，且该第一封装层形成有第一开口及第二开口，以令部分该第一线路结构的第一表面外露于该第一开口，而该第一开口中设有第二电子元件；
形成第二线路结构于该第一封装层上；
设置第三电子元件于该第一封装层上，且该第三电子元件电性连接该第二线路结构；以及
形成多个第一导电元件于该第二线路结构上与外露出该第二开口中的第一线路结构上。
11.如权利要求10所述的电子封装件的制法，其特征为，该第二电子元件电性连接该第三电子元件或该第二线路结构。
12.如权利要求10所述的电子封装件的制法，其特征为，该制法还包括形成第二封装层于该第一封装层上与该第二开口中，以包覆该第三电子元件与这些第一导电元件。
13.如权利要求12所述的电子封装件的制法，其特征为，该第二封装层形成有至少一开孔，以令该第三电子元件的部分表面外露于该开孔，用来结合第四电子元件于该第三电子元件上。
14.如权利要求10所述的电子封装件的制法，其特征为，该制法还包括形成多个第二导电元件于该第一线路结构的第二表面上。
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