CN106463523A - 绝缘栅型半导体装置、以及绝缘栅型半导体装置的制造方法 - Google Patents
绝缘栅型半导体装置、以及绝缘栅型半导体装置的制造方法 Download PDFInfo
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- CN106463523A CN106463523A CN201580018795.1A CN201580018795A CN106463523A CN 106463523 A CN106463523 A CN 106463523A CN 201580018795 A CN201580018795 A CN 201580018795A CN 106463523 A CN106463523 A CN 106463523A
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Abstract
本发明涉及一种绝缘栅型半导体装置,其具有半导体基板、表面电极、以及背面电极,并且对表面电极与背面电极之间进行开关,且该绝缘栅型半导体装置具有:第一外周沟槽,其被形成在半导体基板的表面上;第二外周沟槽,其被形成在半导体基板的表面上,并与第一外周沟槽相比而较深;第二导电型的第五区域,其露出于第一外周沟槽的底面上;第二导电型的第六区域,其露出于第二外周沟槽的底面上,且表面侧的端部与第五区域的背面侧的端部相比而位于背面侧;第一导电型的第七区域,其使第五区域与第六区域分离。
Description
技术领域
(关联申请的相互参照)
本申请为2014年4月9日提出的日本专利申请特愿2014-080040的关联申请,并主张基于该日本专利申请的优先权,且援引该日本专利申请所记载的全部内容以作为构成本说明书的内容。
本说明书所公开的技术涉及一种绝缘栅型半导体装置。
背景技术
在日本专利公开第2008-135522号公报(以下,称为专利文献1)中,公开了一种具有形成有MOS(Metal Oxide Semiconductor:金属氧化物半导体)结构的元件区域和该区域的周围的外周区域的绝缘栅型半导体装置。在元件区域中形成有多个栅极沟槽,并且在栅极沟槽内形成有栅绝缘膜以及栅电极。在露出于栅极沟槽的底面上的范围内,形成有p型的底面围绕区域(以下称为元件部底面围绕区域)。在外周区域内,以包围元件区域的方式而形成有多个沟槽,并在各个沟槽内填充有绝缘层。在露出于外周区域的各个沟槽的底面上的范围内形成有p型的底面围绕区域(以下称为外周部底面围绕区域)。当将MOSFET(Metallic Oxide Semiconductor Field Effect Transistor:金属氧化物半导体场效应晶体管)断开时,在元件区域内,耗尽层将从元件部底面围绕区域向漂移区内扩展。由此,促进了元件区域内的漂移区的耗尽化。此外,在外周区域内,耗尽层从外周部底面围绕区域向漂移区内扩展。由此,促进了外周区域内的漂移区的耗尽化。因此,提高了绝缘栅型半导体装置的耐压。
发明内容
发明所要解决的课题
在专利文献1的绝缘栅型半导体装置中,在元件区域内,耗尽层大致同时地从各个元件部底面围绕区域进行扩展。由于被夹在两个元件部底面围绕区域之间的部分的漂移区的耗尽化从两侧开始进行,因此容易地被耗尽化。相对于此,在外周区域内,当从元件区域开始扩展的耗尽层到达至外周区域内的起始的外周部底面围绕区域(与元件区域最近的外周部底面围绕区域)时,耗尽层从起始的外周部底面围绕区域向第二个外周部底面围绕区域(从元件区域起的第二个外周部底面围绕区域)延伸。当耗尽层到达至第二个外周部底面围绕区域时,耗尽层从第二个外周部底面围绕区域向第三个外周部底面围绕区域延伸。如此,耗尽层经由各个外周部底面围绕区域而依次扩展下去。因此,在被夹在两个外周部底面围绕区域之间的部分的漂移区中,耗尽化仅从一侧进行。因此,为了将外周区域充分耗尽化,期望使外周部底面围绕区域的间隔较窄。但是,当使外周部底面围绕区域的间隔缩窄时,有时会由于制造工序的误差而使外周部底面围绕区域彼此连接,从而产生无法得到所需的耐压的问题。
用于解决课题的方法
本说明书公开的绝缘栅型半导体装置具有:半导体基板、被形成在所述半导体基板的表面上的表面电极、被形成在所述半导体基板的背面上的背面电极,并且,对所述表面电极与所述背面电极之间进行开关。所述半导体基板具有:第一导电型的第一区域,其与所述表面电极相接;第二导电型的第二区域,其与所述表面电极相接,并与所述第一区域相接;第一导电型的第三区域,其通过所述第二区域而与所述第一区域分离;栅极沟槽,其为多个,并被形成在所述表面上,且贯穿所述第二区域而到达所述第三区域;第二导电型的第四区域,其露出于所述栅极沟槽的底面上;第一外周沟槽,其在所述第二区域的外侧的区域内被形成在所述表面上;第二外周沟槽,其在所述第二区域的外侧的区域内被形成在所述表面上,且与第一外周沟槽相比而较深;第二导电型的第五区域,其露出于所述第一外周沟槽的底面上;第二导电型的第六区域,其露出于所述第二外周沟槽的底面上,且所述表面侧的端部与第五区域的所述背面侧的端部相比而位于所述背面侧;第一导电型的第七区域,其与所述第三区域连接,并使所述第五区域与所述第六区域分离。
另外,第二外周沟槽可以被形成在第一外周沟槽的外周侧(距第二区域较远的一侧),也可以被形成在第一外周沟槽的内周侧(距第二区域较近的一侧)。此外,第一导电型为n型与p型中的任意一方,而第二导电型为n型与p型中的任意的另一方。
在该绝缘栅型半导体装置中,通过露出于第一外周沟槽的底面上的第五区域和露出于第二外周沟槽的底面上的第六区域,从而促进了第二区域的外侧的区域中的耗尽层的伸展。在该绝缘栅型半导体装置中,第六区域的表面侧的端部与第五区域的背面侧的端部相比而位于背面侧。即,第五区域与第六区域的深度方向(即,半导体基板的厚度方向)上的位置不同。因此,即使由于制造误差而在半导体基板的平面方向(即,沿着半导体基板的表面的方向)上的第五区域与第六区域的相对位置上产生了偏移,也能够防止第五区域与第六区域连接。
附图说明
图1为半导体装置10的俯视图。
图2为图1的Ⅱ-Ⅱ线处的纵剖视图。
图3为半导体装置10的制造工序的说明图。
图4为半导体装置10的制造工序的说明图。
图5为半导体装置10的制造工序的说明图。
图6为半导体装置10的制造工序的说明图。
图7为半导体装置10的制造工序的说明图。
图8为第二外周沟槽54b相对于第一外周沟槽54a而位置偏移了的情况下的与图2对应的纵剖视图。
图9为第一改变例的半导体装置的与图2对应的纵剖视图。
图10为第二改变例的半导体装置的与图2对应的纵剖视图。
具体实施方式
首先,列述在下文中进行说明的实施例的绝缘栅型半导体装置的特征。另外,以下的各个特征均为独立且有用的特征。
(特征1)在从表面侧对半导体基板进行俯视观察时,第五区域相对于第六区域而部分重叠。通过以这样的方式对第五区域和第六区域进行配置,从而能够对两者以更接近的方式进行配置。由此,能够使绝缘栅型半导体装置的耐压进一步提高。此外,第五区域与第六区域的深度方向上的位置的制造误差小于平面方向上的位置的制造误差。因此,即使以上述的方式对第五区域和第六区域进行配置,也能够防止它们由于制造误差而连接在一起的情况。
(特征2)第六区域的厚度与第五区域的厚度相比而较厚。根据该结构,第六区域的界面的曲线与第五区域的界面的曲线相比而较为平缓。虽然由于第六区域与第五区域相比而向背面侧突出因而使电场容易集中,但通过以这种方式使第六区域的界面的曲线平缓从而能够缓和电场向第六区域的集中。
(特征3)在第五区域内含有第一种第二导电型杂质,在第六区域内含有在半导体基板中的扩散系数大于第一种第二导电型杂质的第二种第二导电型杂质。根据该结构,能够使第六区域的界面的曲线平缓。
(特征4)半导体基板由SiC构成,在第五区域与第六区域中含有碳和硼,第五区域的碳的浓度与第六区域的碳的浓度相比而较高。根据该结构,能够使第六区域的界面的曲线平缓。
(特征5)在第二区域的外侧的区域内,第一外周沟槽和第二外周沟槽被相互交替地形成有多个。
(特征6)绝缘栅型半导体装置可以通过以下方法进行制造。该方法具有:形成第一外周沟槽的工序;通过向第一外周沟槽的底面注入第二导电型杂质而形成第五区域的工序;形成第二外周沟槽的工序;通过向第二外周沟槽的底面注入第二导电型杂质而形成第六区域的工序。
(特征7)优先形成第一外周沟槽与第二外周沟槽中的任意一方的沟槽,在形成了所述一方的沟槽之后,形成第五区域与第六区域中的露出于所述一方的沟槽的底面上的区域,在形成了露出于所述一方的沟槽的底面上的所述区域之后,在所述一方的沟槽内形成绝缘层,在形成了所述绝缘层之后,形成第一外周沟槽与第二外周沟槽中的任意的另一方的沟槽,在形成了另一方的沟槽之后,形成第五区域与第六区域中的露出于另一方的沟槽的底面上的区域,在形成了露出于另一方的沟槽的底面上的所述区域之后,在所述另一方的沟槽内形成绝缘层。如此,通过在一方的沟槽内形成了绝缘层之后形成另一方的沟槽,从而能够防止在被这两个沟槽夹着的半导体层(隔开两个沟槽的隔壁)中产生裂纹等的情况。
(特征8)与形成第五区域的工序相比而优先实施形成第六区域的工序,在形成第六区域的工序中,在向第二外周沟槽的底面注入了第二导电型杂质之后对半导体基板进行退火,在形成第五区域的工序中,在向第一外周沟槽的底面注入了第二导电型杂质之后对半导体基板进行退火。在该方法中,由于第六区域与第五区域相比而更多地被进行退火,因此能够使第六区域的界面的曲线平缓。
(特征9)形成第六区域的工序中的退火的温度与形成第五区域的工序中的退火的温度相比而较高。根据该方法,能够使第六区域的界面的曲线更加平缓。
(特征10)在形成第五区域的工序中,向第一外周沟槽的底面注入第一种第二导电型杂质,在形成第六区域的工序中,向第二外周沟槽的底面注入在半导体基板中的扩散系数大于第一种第二导电型杂质的第二种第二导电型杂质。根据该方法,能够使第六区域的界面的曲线平缓。
(特征11)
半导体基板由SiC构成,在形成第五区域的工序中,向第一外周沟槽的底面注入碳和硼,在形成第六区域的工序中,向第二外周沟槽的底面注入硼。根据该方法,能够使第六区域的界面的曲线更加平缓。
(特征12)将栅极沟槽与第一外周沟槽同时形成。
(实施例1)
图1所示的半导体装置10具有由SiC组成的半导体基板12。半导体基板12具有单元区20与外周区域50。在单元区20内形成有MOSFET。外周区域50为单元区20与半导体基板12的端面12a之间的区域。
如图2所示,在半导体基板12的表面上形成有表面电极14和绝缘层16。绝缘层16对外周区域50内的半导体基板12的表面进行覆盖。表面电极14在单元区20内与半导体基板12相接。换言之,表面电极14与半导体基板12相接的接触区为单元区20,与接触区相比靠外周侧(端面12a侧)的区域为外周区域50。在半导体基板12的背面上形成有背面电极18。背面电极18覆盖着半导体基板12的大致整个背面。
在单元区20内形成有源极区22、体区23、漂移区28、漏极区30、p型浮置区32、以及栅极沟槽34。
源极区22(权利要求的第一区域的一个示例)为,以高浓度而含有n型杂质的n型区域。源极区22被形成在露出于半导体基板12的上表面上的范围内。源极区22与表面电极14相接,并且相对于表面电极14而欧姆连接。
体区23(权利要求的第二区域的一个示例)具有体接触区24和低浓度区26。体接触区24为以高浓度而含有p型杂质的p型区域。体接触区24以在未形成有源极区22的位置处露出于半导体基板12的上表面上的方式而形成。体接触区24与表面电极14相接,并相对于表面电极14而欧姆连接。低浓度区26为以低浓度而含有p型杂质的p型区域。低浓度区26的p型杂质浓度与体接触区24的p型杂质浓度相比而较低。低浓度区26被形成在源极区22以及体接触区24的下侧,并与这两个区域相接。
漂移区28(权利要求的第三区域的一个示例)为,以低浓度而含有n型杂质的n型区域。漂移区28的n型杂质浓度与源极区22的n型杂质浓度相比而较低。漂移区28被形成在体区23的下侧。漂移区28与体区23相接,并通过体区23而与源极区22分离。
漏极区30为以高浓度而含有n型杂质的n型区域。漏极区30的n型杂质浓度与漂移区28的n型杂质浓度相比而较高。漏极区30被形成在漂移区28的下侧。漏极区30与漂移区28相接,并通过漂移区28而与体区23分离。漏极区30被形成在露出于半导体基板12的下表面上的范围内。漏极区30相对于背面电极18而欧姆连接。
如图1、2所示,在单元区20内的半导体基板12的上表面上形成有多个栅极沟槽34。如图1所示,各个栅极沟槽34在半导体基板12的表面上相互平行且以直线状而延伸。如图2所示,各个栅极沟槽34以贯穿源极区22和体区23并到达漂移区28的方式而形成。在各个栅极沟槽34内形成有底部绝缘层34a、栅级绝缘膜34b、以及栅电极34c。底部绝缘层34a为被形成在栅极沟槽34的底部的较厚的绝缘层。底部绝缘层34a的上侧的栅极沟槽34的侧面被栅级绝缘膜34b覆盖。在底部绝缘层34a的上侧的栅极沟槽34内形成有栅电极34c。栅电极34c隔着栅级绝缘膜34b而与源极区22、体区23以及漂移区28对置。栅电极34c通过栅级绝缘膜34b以及底部绝缘层34a而与半导体基板12绝缘。栅电极34c的上表面被绝缘层34d覆盖。栅电极34c通过绝缘层34d而与表面电极14绝缘。
p型浮置区32(权利要求的第四区域的一个示例)位于半导体基板12内并被形成在露出于各个栅极沟槽34的底面上的范围(即,与该底面相接的范围)内。各个p型浮置区32的周围被漂移区28包围。各个p型浮置区32通过漂移区28而相互分离。此外,各个p型浮置区32通过漂移区28而与体区23分离。
在露出于外周区域50内的半导体基板12的表面上的范围内,形成有p型的表面区域51。表面区域51扩展到与体区23大致相同的深度。表面区域51的上表面整体被绝缘层16覆盖。因此,表面区域51不与表面电极14相接。上述的漂移区28以及漏极区30扩展到外周区域50。漂移区28和漏极区30扩展到半导体基板12的端面12a。漂移区28从下侧与表面区域51相接。
在外周区域50内的半导体基板12的上表面上形成有多个外周沟槽54(即,54a以及54b)。各个外周沟槽54以贯穿表面区域51并到达漂移区28的方式而形成。如图1所示,在从上侧对半导体基板12进行观察时,各个外周沟槽54被形成为围绕单元区20的周围一周的环状。如图2所示,表面区域51通过最内周侧的外周沟槽54而与体区23(即,与源极区22以及表面电极14相接的p型区域)分离。此外,各个表面区域51通过各个外周沟槽54而相互分离。换言之,最内周侧的外周沟槽54的内侧的p型区域为体区23,与最内周侧的外周沟槽54相比而靠外周侧的p型区域为表面区域51。因此,外周沟槽54被形成在体区23的外侧。在各个外周沟槽54内形成有绝缘层53。
外周沟槽54具有第一外周沟槽54a和第二外周沟槽54b。第一外周沟槽54a的深度与栅极沟槽34的深度大致相等。第二外周沟槽54b与第一外周沟槽54a相比而较深。最靠内周侧的外周沟槽54为第一外周沟槽54a。第一外周沟槽54a与第二外周沟槽54b从内周侧朝向外周侧而被交替地配置。
在半导体基板12内且露出于各个外周沟槽54的底面上的范围(即,与该底面相接的范围)内形成有p型的底面区域56(即,56a以及56b)。底面区域56以对外周沟槽54的整个底面进行覆盖的方式沿着外周沟槽54而形成。各个底面区域56的周围被外周区域50内的漂移区28(权利要求的第七区域的一个示例)包围。各个底面区域56通过外周区域50内的漂移区28而相互分离。
底面区域56具有露出于第一外周沟槽54a的底面上的第一底面区域56a(权利要求的第五区域的一个示例)、以及露出于第二外周沟槽54b的底面上的第二底面区域56b(权利要求的第六区域的一个示例)。第一底面区域56a被形成在与第二底面区域56b相比而较浅的位置处。即,第一底面区域56a的下端55a位于与第二底面区域56b的上端55b相比靠上侧处。因此,在第一底面区域56a的下端55a与第二底面区域56b的上端55b之间,于半导体基板12的深度方向上形成有间隔D1。在对半导体基板12的上表面进行俯视观察时(即,沿着半导体基板12的深度方向进行观察时),第一底面区域56a以与相邻的第二底面区域56b部分重叠的方式而配置。
在第一底面区域56a中,作为p型杂质而含有Al(铝)。在第二底面区域56b中,作为p型杂质而含有B(硼)。
第二底面区域56b的厚度Db与第一底面区域56a的厚度Da相比而较大。此外,第二底面区域56b的宽度Wb(从内周侧朝向外周侧的方向上的宽度)与第一底面区域56a的宽度Wa相比而较大。因此,第二底面区域56b的界面(与漂移区28的界面)的曲线与第一底面区域56a的界面(与漂移区28的界面)的曲线相比而较为平缓。即,第二底面区域56b的界面的曲率小于第一底面区域56a的界面的曲率。
接着,对半导体装置10的动作进行说明。在使半导体装置10进行动作时,在背面电极18与表面电极14之间被施加有使背面电极18成为正极的电压。并且,通过对栅电极34c施加栅极导通电压,从而使单元区20内的MOSFET导通。即,在与栅电极34c对置的位置的体区23内形成有沟道,并使电子从表面电极14起经由源极区22、沟道、漂移区28、以及漏极区30而朝向背面电极18流动。
当停止朝向栅电极34c的栅极导通电压的施加时,沟道将消失,且MOSFET断开。当MOSFET断开时,耗尽层将从体区23与漂移区28的边界部的pn结向漂移区28内扩展。当耗尽层到达单元区20内的p型浮置区32时,耗尽层还会从p型浮置区32向漂移区28内扩展。因此,位于两个p型浮置区32之间的漂移区28通过从两侧的p型浮置区32开始扩展的耗尽层而被耗尽化。如此,通过耗尽层向单元区20内延伸,从而实现了单元区20内的较高的耐压。
此外,上述的从pn结起延伸的耗尽层到达位于最靠单元区20侧的第一外周沟槽54a的下侧的第一底面区域56a。于是,耗尽层从第一底面区域56a向其周围的漂移区28内扩展。由于第一底面区域56a与其相邻(与外周侧相邻)的第二底面区域56b之间的间隔较窄,因此从第一底面区域56a延伸出的耗尽层会到达相邻的第二底面区域56b。于是,耗尽层从该第二底面区域56b起向其周围的漂移区28内扩展。由于第二外周沟槽54b与其相邻(与外周侧相邻)的第一底面区域56a之间的间隔较窄,因此从第二底面区域56b延伸出的耗尽层会到达相邻的第一底面区域56a。如此,耗尽层经由第一底面区域56a与第二底面区域56b而向外周侧伸展。如此,耗尽层从最靠内周侧的底面区域56延伸至最靠外周侧的底面区域56。如此,耗尽层广泛地伸展至外周区域50内的漂移区28内。底面区域56彼此通过漂移区28而相互分离。因此,在各个底面区域56之间产生电位差。因此,在外周区域50内,电位以从内周侧朝向外周侧电位逐渐变化的方式而分布。如此,通过耗尽层向外周区域50内伸展,并且形成向外周区域50内缓慢变化的电位分布,从而抑制了外周区域50的电场集中。因此,半导体装置10耐压较高。
此外,第二底面区域56b与第一底面区域56a相比而向下侧突出。因此,在耗尽层正在向外周区域50扩展的状态下,在第二底面区域56b的周围,电场容易集中。但是,在半导体装置10中,第二底面区域56b的厚度Db较厚,由此第二底面区域56b的界面的曲线变得较为平缓。通过以这种方式使第二底面区域56b的界面的曲线变得平缓,从而抑制了第二底面区域56b附近的电场集中。由此,半导体装置10的耐压进一步提高。
接着,对半导体装置10的制造方法进行说明。在实施例1的制造方法中,首先,如图3所示,通过外延生长、离子注入等而在半导体基板12上形成源极区22、体区23以及表面区域51。
接着,如图4所示,在半导体基板12的表面上形成具有开口的掩模60(例如氧化膜),并通过各向异性蚀刻而对开口内的半导体基板12进行蚀刻。由此,形成第二外周沟槽54b。
接着,向第二外周沟槽54b的底面注入B(硼:权利要求的第二种第二导电型杂质的一个示例),之后,对半导体基板12进行退火(第一退火)。由此,使被注入的B活化并扩散。由此,如图5所示,形成第二底面区域56b。
接着,通过使绝缘体在第二外周沟槽54b内生长,从而在第二外周沟槽54b内形成绝缘层53。
接着,如图6所示,在半导体基板12的表面上形成具有开口的掩模62(例如氧化膜),并通过各向异性蚀刻而对开口内的半导体基板12进行蚀刻。由此,形成第一外周沟槽54a和栅极沟槽34。第一外周沟槽54a和栅极沟槽34被形成为与第二外周沟槽54b相比而较浅。此外,第一外周沟槽54a被形成在第二外周沟槽54b的相邻处,以使第一外周沟槽54a与第二外周沟槽54b被交替地配置。
接着,向第一外周沟槽54a的底面和栅极沟槽34的底面注入Al(铝:权利要求的第一种第二导电型杂质的一个示例),之后,对半导体基板12进行退火(第二退火)。另外,第二退火以与第一退火相比而较低的温度来实施。由此,使被注入的Al活化并扩散。由此,如图7所示,形成第一底面区域56a和p型浮置区32。
接着,使绝缘体在第一外周沟槽54a和栅极沟槽34的内部生长。由此,在第一外周沟槽54a内形成绝缘层53。接着,局部性地去除栅极沟槽34内的绝缘体,之后,在栅极沟槽34内形成栅绝缘膜34b和栅电极34c。
接着,通过在半导体基板12的上表面上形成绝缘层34d、绝缘层16以及表面电极14,从而完成半导体装置10的上表面侧的结构。接着,形成半导体基板12的下表面侧的结构(即,漏极区30以及背面电极18)。由此,完成了图1、2的半导体装置10。
在上述的半导体装置10的制造工序中,在沿着半导体基板12的上表面的方向(即,X方向以及Y方向)上,在第一外周沟槽54a与第二外周沟槽54b的相对位置上容易产生偏移。即,第一外周沟槽54a与第二外周沟槽54b的位置的X方向以及Y方向上的误差较大。尤其在上述的实施例中,由于通过不同的工序而形成第一外周沟槽54a和第二外周沟槽54b,因此该误差更大。第一底面区域56a的X方向以及Y方向上的位置因第一外周沟槽54a的位置而变化,第二底面区域56b的X方向以及Y方向上的位置因第二外周沟槽54b的位置而变化。因此,在X方向以及Y方向上,在第一底面区域56a与第二底面区域56b的相对位置上容易产生偏移。但是,在该半导体装置10中,在半导体基板12的厚度方向(即Z方向)上,第一底面区域56a与第二底面区域56b的位置有所不同。更详细而言,在第一底面区域56a与第二底面区域56b之间形成有间隔D1。因此,即使第一底面区域56a与第二底面区域56b的相对位置在X方向或Y方向上发生了较大偏移,第一底面区域56a与第二底面区域56b也不会连接在一起。例如,如图8所示,即使由于制造误差而使得第二底面区域56b位移至第一底面区域56a侧,第一底面区域56a也不会与第二底面区域56b连接。如此,根据半导体装置10的结构,能够防止由于制造误差而导致第一底面区域56a与第二底面区域56b连接的情况。
此外,第一底面区域56a的Z方向上的位置因第一外周沟槽54a的深度和针对第一底面区域56a的杂质的注入范围以及扩散范围而变化。此外,第二底面区域56b的Z方向上的位置因第二外周沟槽54b的深度和针对第二底面区域56b的杂质的注入范围以及扩散范围而变化。各个沟槽的深度和杂质的注入范围以及扩散范围能够准确地进行控制。因此,与X方向以及Y方向上的位置相比,第一底面区域56a以及第二底面区域56b的Z方向上的位置能够准确地进行控制。因此,根据上述的制造方法,能够准确地对第一底面区域56a与第二底面区域56b的Z方向上的间隔D1进行控制。因此,能够缩短间隔D1。因此,根据上述的制造方法,能够使外周区域50的耐压提高。
此外,在上述的制造方法中,作为第一底面区域56a的p型杂质而注入Al,作为第二底面区域56b的p型杂质而注入B。半导体基板12(即,SiC)之中的B的扩散系数与Al的扩散系数相比而较大。因此,能够将第二底面区域56b设为大于第一底面区域56a。
此外,在上述的制造方法中,以与第二退火相比而较高的温度来实施第一退火。因此,在第一退火中B的扩散距离变大。由此,也使得第二底面区域56b被形成为大于第一底面区域56a。
此外,在上述的制造方法中,与第一底面区域56a相比而优先形成第二底面区域56b。因此,第二底面区域56b不仅在第一退火中还在第二退火中被加热。在第二退火中,由于在第二底面区域56b中的B进一步扩散,因此第二底面区域56b扩大。由此也使得第二底面区域56b被形成为大于第一底面区域56a。
由于如上所述第二底面区域56b变得大于第一底面区域56a,因此第二底面区域56b的厚度Db也变得大于第一底面区域56a的厚度Da。其结果为,第二底面区域56b的界面的曲线与第一底面区域56a的界面的曲线相比而变得较为平缓。由于以这种方式而形成了第二底面区域56b,因此能够如上所述在MOSFET的断开时抑制第二底面区域56b的附近的电场集中。
此外,由于在第一底面区域56a的周围难以产生电场集中,因此即使第一底面区域56a的界面的曲率较大,也不会产生电场集中的问题。此外,通过以这种方式使第一底面区域56a小型化,从而能够使半导体装置10小型化。
此外,在上述的制造方法中,通过不同的工序而形成了第一外周沟槽54a与第二外周沟槽54b。若同时形成第一外周沟槽54a和第二外周沟槽54b,则在第一外周沟槽54a与第二外周沟槽54b之间的较薄的隔壁(半导体层)上容易产生裂纹。与此相对,如上述那样,若在形成第二外周沟槽54b之后,且在将绝缘层53埋入第二外周沟槽54b后形成第一外周沟槽54a,则由于不会形成较薄的隔壁从而能够抑制裂纹。另外,即使优先形成第一外周沟槽54a并在将绝缘层53埋入第一外周沟槽54a后形成第二外周沟槽54b,也能够消除隔壁的裂纹的问题。
(实施例2)
在实施例2的半导体装置中,第一底面区域56a中所包含的p型杂质与第二底面区域56b中所包含的p型杂质均为B。此外,第一底面区域56a中的C(碳)的浓度与第二底面区域56b中的C的浓度相比而较高。实施例2的半导体装置的其他结构与实施例1的半导体装置10相同。因此,实施例2的半导体装置也与实施例1的半导体装置10同样地进行动作。
对实施例2的半导体装置的制造方法进行说明。首先,以与实施例1相同的方式而形成图6所示的结构。接着,向第一外周沟槽54a的底面注入C。由此,第一外周沟槽54a的底面附近的C的浓度上升。接着,向第一外周沟槽54a的底面注入B。即,此处,将C和B混合在第一外周沟槽54a的底面中。接着,对半导体基板12进行退火(第二退火)。由此,使被注入到半导体基板12中的B活化并扩散。由此,如图7所示,形成第一底面区域56a。另外,在实施例2的制造方法中,也可以与第一底面区域56a同时形成p型浮置区32。之后,以与实施例1的方法相同的方式而完成实施例2的半导体装置。
当在半导体基板12(即SiC)中混合B和C时,半导体基板12中的B的扩散系数变小。即,B变得难以扩散。因此,根据实施例2的制造方法,能够形成较小的第一底面区域56a。此外,由于第二底面区域56b中只注入有B而未注入C,因此在实施例2的制造方法中也会与实施例1的制造方法同样地形成较大的第二底面区域56b。因此,如图2所示,在实施例2的制造方法中,也能够将第二底面区域56b设为大于第一底面区域56a。
另外,在实施例2的制造方法中,也可以以与实施例1的制造方法同样的方式将第二退火的温度设为高于第一退火的温度。
另外,在上述的实施例1、2中,最靠内周侧(与体区23较近的一侧)的外周沟槽54为第一外周沟槽54a。但是,如图9所示,最靠内周侧的外周沟槽54也可以为第二外周沟槽54b(较深的沟槽)。此外,在图2、9中,栅极沟槽34与最靠内周侧的外周沟槽54具有大致相同的深度。但是,最靠内周侧的外周沟槽54可以与栅极沟槽34相比而较深、也可以与栅极沟槽34相比而较浅。
此外,在上述的实施例中,第一外周沟槽54a与第二外周沟槽54b被交替地形成有多个。但是,在一部分的区域中,也可以并排地形成两个第一外周沟槽54a,还可以并排地形成两个第二外周沟槽54b。此外,也可以在外周区域50内各形成一个第一外周沟槽54a和第二外周沟槽54b。即,只需形成在外周区域50内于与第一外周沟槽54a相邻的位置处形成有第二外周沟槽54b的结构,就能够取得上述的实施例的效果。
此外,在上述的实施例中,第二底面区域56b与第一底面区域56a相比而较厚。但是,在第二底面区域56b附近的电场集中几乎不会成为问题的情况下,第二底面区域56b的厚度也可以为第一底面区域56a的厚度以下。
此外,在上述的实施例中,在对半导体基板12的上表面进行俯视观察时,第一底面区域56a与第二底面区域56b部分重叠。但是,如图10所示,它们也可以不重叠。即使采用这种结构,也能够防止由于X方向或Y方向上的位置的误差而使第一底面区域56a与第二底面区域56b连接的情况。此外,即使第一底面区域56a与第二底面区域56b不重叠,也能够使耗尽层从第一底面区域56a向第二底面区域56b(或者从第二底面区域56a向第一底面区域56b)伸展。
此外,在上述的实施例中,虽然半导体基板12由SiC构成,但也可以使用由Si等其他的材质构成的半导体基板。此外,也可以代替上述的实施例的p型浮置区32而形成与预定的电位相连接的p型区域。
虽然以上对本发明的具体例进行了详细说明,但这些只不过是示例,而并不是对权利要求书进行限定的内容。在权利要求书所记载的技术中,包括对上文所例示的具体例进行了各种变形、变更的内容。
在本说明书或附图中所说明的技术要素为单独或通过各种组合来发挥技术上的有用性的要素,其并不限定于申请时权利要求所记载的组合。此外,本说明书或附图所例示的技术为能够同时达成多个目的的技术,而实现其中一个目的本身也具有技术上的有用性。
Claims (13)
1.一种绝缘栅型半导体装置,具有半导体基板、被形成在所述半导体基板的表面上的表面电极、以及被形成在所述半导体基板的背面上的背面电极,并且对所述表面电极与所述背面电极之间进行开关,其中,
所述半导体基板具有:
第一导电型的第一区域,其与所述表面电极相接;
第二导电型的第二区域,其与所述表面电极相接,并与所述第一区域相接;
第一导电型的第三区域,其通过所述第二区域而与所述第一区域分离;
栅极沟槽,其为多个,并被形成在所述表面上,且贯穿所述第二区域而到达所述第三区域;
第二导电型的第四区域,其露出于所述栅极沟槽的底面上;
第一外周沟槽,其在所述第二区域的外侧的区域内被形成在所述表面上;
第二外周沟槽,其在所述第二区域的外侧的区域内被形成在所述表面上,并与第一外周沟槽相比而较深;
第二导电型的第五区域,其露出于所述第一外周沟槽的底面上;
第二导电型的第六区域,其露出于所述第二外周沟槽的底面上,并且,所述第二导电型的第六区域的所述表面侧的端部与第五区域的所述背面侧的端部相比而位于所述背面侧;
第一导电型的第七区域,其与所述第三区域连接,并使所述第五区域与所述第六区域分离。
2.如权利要求1所述的绝缘栅型半导体装置,其中,
在从所述表面侧对所述半导体基板进行俯视观察时,所述第五区域相对于所述第六区域而部分重叠。
3.如权利要求1或2所述的绝缘栅型半导体装置,其中,
所述第六区域的厚度与所述第五区域的厚度相比而较厚。
4.如权利要求3所述的绝缘栅型半导体装置,其中,
在所述第五区域内含有第一种第二导电型杂质,
在所述第六区域内含有第二种第二导电型杂质,所述第二种第二导电型杂质与所述第一种第二导电型杂质相比在所述半导体基板中的扩散系数较大。
5.如权利要求3所述的绝缘栅型半导体装置,其中,
所述半导体基板由SiC构成,
在所述第五区域和所述第六区域内含有碳和硼,
所述第五区域的碳的浓度与所述第六区域的碳的浓度相比而较高。
6.如权利要求1~5中任意一项所述的绝缘栅型半导体装置,其中,
在所述第二区域的外侧的区域内,所述第一外周沟槽与所述第二外周沟槽被交替地形成有多个。
7.一种方法,其为制造权利要求1~6中任意一项所述的绝缘栅型半导体装置的方法,包括:
形成所述第一外周沟槽的工序;
通过向所述第一外周沟槽的底面注入第二导电型杂质从而形成所述第五区域的工序;
形成所述第二外周沟槽的工序;
通过向所述第二外周沟槽的底面注入第二导电型杂质从而形成所述第六区域的工序。
8.如权利要求7所述的方法,其中,
优先形成所述第一外周沟槽与所述第二外周沟槽中的任意一方的沟槽,
在形成所述一方的沟槽后,形成所述第五区域与所述第六区域中的露出于所述一方的沟槽的底面上的区域,
在形成了露出于所述一方的沟槽的底面上的所述区域后,在所述一方的沟槽内形成绝缘层,
在形成了所述绝缘层后,形成所述第一外周沟槽与所述第二外周沟槽中的任意另一方的沟槽,
在形成了所述另一方的沟槽后,形成所述第五区域与所述第六区域中的露出于所述另一方的沟槽的底面上的区域,
在形成了露出于所述另一方的沟槽的底面上的所述区域后,在所述另一方的沟槽内形成绝缘层。
9.如权利要求7或8所述的方法,其中,
与形成所述第五区域的所述工序相比而优先实施形成所述第六区域的所述工序,
在形成所述第六区域的所述工序中,在向所述第二外周沟槽的底面注入了第二导电型杂质后对所述半导体基板进行退火,
在形成所述第五区域的所述工序中,在向所述第一外周沟槽的底面注入了第二导电型杂质后对所述半导体基板进行退火。
10.如权利要求9所述的方法,其中,
形成所述第六区域的所述工序中的退火的温度与形成所述第五区域的所述工序中的退火的温度相比而较高。
11.如权利要求7~10中任意一项所述的方法,其中,
在形成所述第五区域的所述工序中,向所述第一外周沟槽的底面注入第一种第二导电型杂质,
在形成所述第六区域的所述工序中,向所述第二外周沟槽的底面注入第二种第二导电型杂质,所述第二种第二导电型杂质与所述第一种第二导电型杂质相比在所述半导体基板中的扩散系数较大。
12.如权利要求7~11中任意一项所述的方法,其中,
所述半导体基板由SiC构成,
在形成所述第五区域的所述工序中,向所述第一外周沟槽的底面注入碳和硼,
在形成所述第六区域的所述工序中,向所述第二外周沟槽的底面注入硼。
13.如权利要求7~12中任意一项所述的方法,其中,
将所述栅极沟槽与所述第一外周沟槽同时形成。
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