CN106409911A - 具有内场板结构与p型栅结合的耐压漂移区的半导体器件 - Google Patents
具有内场板结构与p型栅结合的耐压漂移区的半导体器件 Download PDFInfo
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Abstract
具有内场板结构与P型栅相结合的耐压漂移区的半导体器件涉及半导体器件领域,解决了现有技术中半导体器件耐压低,工艺复杂和制作设备昂贵的问题,该半导体器件的耐压漂移区从下至上包括:高掺杂浓度的低阻衬底层N++,低掺杂浓度的高阻层N‑,和较高掺杂浓度的低阻层N;在低阻层N上进行硅刻蚀形成沟槽或孔,沟槽或深度为到达或接近低掺杂浓度的高阻层N‑,在沟槽或孔内制作P栅和绝缘层;在绝缘层内制作电极。本发明结构及工艺简单,制造成本低。在内场板结构的沟槽或孔的底形成P型栅,结合内场板结构,实现器件的高耐压,降低了通态电阻或压降。以600V的VDMOSFET器件为例,采用该耐压漂移区,在同等芯片面积下,通态电阻可以降低20%以上。
Description
技术领域
本发明涉及半导体器件领域,具体涉及一种具有内场板结构与P型栅相结合的耐压漂移区的半导体器件。
背景技术
半导体器件在作为开关器件,为了降低通态电阻或压降,突破“硅限”,尤其是高压功率半导体器件,目前开发出超级结(Super Junction)技术,为了降低工艺难度开发出比例超级结(Partial Super Junction)技术。超级结技术需要深沟槽刻蚀技术、外延技术、以及CMP技术,工艺难度大,相应的设备也比较昂贵。对于低压功率半导体器件,目前开发出内场板技术,这种技术目前名称比较多,如:Split-Gate(分栅)技术,Oxidt Bypassed(OB)侧氧结构技术等,这种技术效果与超级结技术效果接近,但工艺比较简单;不过由于内场板技术中,内场板顶端(或沟槽底部)处硅表面电场强度增加速度与内场板长度(或沟槽深度)强相关,所以该技术适合于耐压200V以下的器件。
发明内容
为了解决现有技术中存在的问题,本发明提供了一种具有内场板结构与P型栅相结合的耐压漂移区的半导体器件,解决了现有技术中半导体器件耐压低,工艺复杂和制作设备昂贵的问题。
本发明解决技术问题所采用的技术方案如下:
具有内场板结构与P型栅结合的耐压漂移区的半导体器件,该半导体器件的耐压漂移区从下至上包括:高掺杂浓度的低阻衬底层N++,低掺杂浓度的高阻层N-,和较高掺杂浓度的低阻层N;在低阻层N上进行硅刻蚀形成沟槽或孔,沟槽或孔深度为2μm-10μm;并到达或接近低掺杂浓度的高阻层N-,在沟槽或孔内制作绝缘层,在沟槽或孔底部制作P栅;在绝缘层内制作电极。
本发明的有益效果是:本发明结构及工艺简单,制造成本低。只是在内场板结构中的沟槽或孔的底部形成P型栅,结合内场板结构就可以实现器件的高耐压。实现了半导体器件的在耐压一定的情况下,降低了通态电阻或压降。以600V的VDMOSFET器件为例,采用该耐压漂移区,在同等芯片面积下,通态电阻可以降低20%以上。
附图说明
图1本发明内场板与P栅相结合的耐压漂移区结构。
图2本发明内场板与P栅相结合的耐压漂移区结构,内场板电极材料被绝缘层包裹。
图3本发明具有内场板与P栅相结合的耐压漂移区结构的平面栅结构的VDMOSFET,VDMOSFET的阱区在相邻内场板之间。
图4本发明具有内场板与P栅相结合的耐压漂移区结构的平面栅结构的VDMOSFET,VDMOSFET的阱区与内场板相邻。
图5本发明具有内场板与P栅相结合的耐压漂移区结构的沟槽栅结构的VDMOSFET,VDMOSFET的阱区与内场板相邻。
图6本发明具有内场板与P栅相结合的耐压漂移区结构的沟槽栅结构的VDMOSFET,VDMOSFET的与内场板共用沟槽结构。
图7本发明具有内场板与P栅相结合的耐压漂移区结构FER二极管结构。
图8本发明内场板与P栅相结合的耐压漂移区结构等效电路图。
图中:1、绝缘层,2、内场板电极,3、,4、栅极,5、源极,6、栅氧化层,7、N+源区,8、P阱区,9、漏极,10、阴极和11、阳极。
具体实施方式
下面结合附图和实施例对本发明做进一步详细说明。
一种内场板结构与P栅相结合耐压漂移区结构。场板是半导体器件改善器件终端耐压的一个部件,通过一个金属电极、绝缘层和半导体的结构实现的,位于器件终端表面位置;利用该结构,使其垂直与器件表面以原胞的形成分布在整个器件中,称为内场板。P型栅为以P型杂质形成的扩散岛或扩散条,在半导体内构成栅网。
以N型硅材料为例说明,如图1所示,材料片分为3层,最下层为高掺杂浓度的低阻衬底层N++,中间层为低掺杂浓度的高阻层N-,上层为较高掺杂浓度的低阻层N;在低阻层N上进行硅刻蚀,形成沟槽或孔,其深度为2μm-10μm,沟槽或孔的侧壁可以垂直或倾斜;深度接近高阻层N-或达到高阻层N-。在沟槽或孔的底部进行P栅3离子注入或通过光刻实现局部P栅3离子注入,然后在沟槽或孔内壁形成绝缘层1,其厚度0.15μm-1.0μm,退火或在形成绝缘层1等过程中将注入离子激活或推结,形成P栅3;在绝缘层1壁上制作内场板电极2,材料选择多晶硅等。此内场板电极2也可以被绝缘层1包裹,如图2所示。其中,N型区与由沟槽、绝缘层1、内场板电极2形成的内场板结构,内场板结构与内场板结构下方的P栅3及高阻层N-共同构成器件耐压漂移区。
具有该耐压漂移区的半导体器件,可以是VDSMOSFET器件,如图3-6所示,内场板电极2与源极5相连;在内场板的沟槽两侧低阻N型区表面,形成器件的栅极4、栅氧化层6、N+源区7、P阱区8,在N++型区形成漏极9,形成VDMOSFET结构;VDMOSFET可以是平面栅结构,也可以是沟槽栅结构。利用本发明的耐压漂移区结构构成的VDMOSFET,在图3中平面栅结构的VDMOSFET原胞,其P阱区8在相邻内场板之间的情况。图4中平面栅结构的VDMOSFET原胞,其P阱区8与内场板相邻;图5中沟槽栅结构的VDMOSFET,其P阱区8与内场板相邻;图6中P栅3结构的VDMOSFET原胞,其控制沟槽与内场板共用一个沟槽的结构。
具有该耐压漂移区的半导体器件,可以是FRD二极管,在内场板的沟槽两侧低阻N型区表面,形成器件的P型阴极区,在N++型区形成阳极,构成FRD二极管结构。
为了便于理解,以具有内场板技术与P栅相结合的耐压漂移区的二极管为例说明,在内场板的沟槽两侧低阻N型区表面,器件的P型区形成阴极10,在N++型区形成阳极11,构成FRD二极管结构。所有的N型区与P型区互换,互换后就可以形成相反导电类型的器件。如图7所示,其等效电路图如图8所示,二极管与一个JFET场效应三极管的漏极串联;一个电容一端与二极管的阴极相连,另一端与JFET场效应三极管的栅极相连;该耐压漂移区结构中,N层掺杂浓度较高,其电阻率小于N-层电阻率1/2以下;耐压由内场板结构和P栅3共同承担。器件加载偏压时,电压首先由内场板结构承担,随着偏压增加,P栅3上的偏压也随着增加,P栅3侧向的N型区耗尽而夹断,继续承载偏压,直至达到最高电压。
在耐压漂移内,本发明结构的耐压漂移区的电场分布可以看成近似梯形分布,而常规耐压漂移区的电场分布近似三角形分布,曲线包围的面积为漂移区的耐压,所以本发明结构的耐压漂移区对提高耐压更有利。
上面对本发明的内场板技术与P栅相结合耐压结构进行了介绍,利用该耐压漂移区结构可以制造各种各样的高压半导体器件。
本发明的耐压漂移区结构,有很多可供调整的参数,它们包括,内场板的长度(即场板的沟槽深度),以及内场板绝缘层的厚度;最上层N型区的杂质浓度及浓度分布,内场板的间距,以及P型栅的形状(点状或条状),以及高阻N区的杂质浓度和浓度分布,以及高阻N区的厚度。因此,在实际的工艺条件下,可以一定的内场板长度下得到合理电场分布,实现最高耐压。
Claims (6)
1.具有内场板结构与P型栅结合的耐压漂移区的半导体器件,其特征在于,该半导体器件的耐压漂移区从下至上包括:高掺杂浓度的低阻衬底层N++,低掺杂浓度的高阻层N-,和较高掺杂浓度的低阻层N;在低阻层N上进行硅刻蚀形成沟槽或孔,沟槽或孔深度为2μm-10μm;并到达低掺杂浓度的高阻层N-,在沟槽或孔内制作绝缘层,在沟槽或孔底部制作P栅;在绝缘层内制作电极。
2.根据权利要求1所述的具有内场板结构与P型栅结合的耐压漂移区的半导体器件,其特征在于,所述绝缘层的厚度为0.15μm-1.0μm。
3.根据权利要求1或2所述的具有内场板结构与P型栅相结合的耐压漂移区的半导体器件,其特征在于,所述制作P栅的工艺流程为离子注入或者推结。
4.根据权利要求1或2所述的具有内场板结构与P型栅结合的耐压漂移区的半导体器件,其特征在于,所述电极的材料为多晶硅。
5.根据权利要求1或2所述的具有内场板结构与P型栅结合的耐压漂移区的半导体器件,其特征在于,所述P栅的结构为点状、段状或者条状。
6.根据权利要求1或2所述的具有内场板结构与P型栅结合的耐压漂移区的半导体器件,其特征在于,所述硅刻蚀的沟槽或孔侧壁为垂直或者倾斜。
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CN103579345A (zh) * | 2012-07-30 | 2014-02-12 | 万国半导体股份有限公司 | 高压场平衡金属氧化物场效应晶体管 |
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CN115132587A (zh) * | 2022-07-05 | 2022-09-30 | 上海功成半导体科技有限公司 | 一种功率器件及其制备方法 |
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