CN106356366B - 倒装芯片接合合金 - Google Patents

倒装芯片接合合金 Download PDF

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Publication number
CN106356366B
CN106356366B CN201610557647.3A CN201610557647A CN106356366B CN 106356366 B CN106356366 B CN 106356366B CN 201610557647 A CN201610557647 A CN 201610557647A CN 106356366 B CN106356366 B CN 106356366B
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die
board
alloy
reflow
bond pads
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CN106356366A (zh
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M·J·塞登
F·J·卡尔尼
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Semiconductor Components Industries LLC
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Semiconductor Components Industries LLC
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Abstract

本公开涉及倒装芯片接合合金。一种用于将在管芯表面上具有第一及第二金属层的多个管芯接合至板件的方法，包括将第一管芯安置于包括具有可焊表面的陶瓷板或基材板或者金属引线框之一的板件之上，并且将第一管芯和板件安置于回流炉内。该方法包括在第一回流温度进行回流达第一时段，直到第一金属板层以及第一管芯的第一及第二金属管芯层中的至少一个形成合金，以将第一管芯粘附于板件。新形成的合金具有比第一回流温度更高的熔化温度。因此，如果使用同样的回流温度，则额外的管芯会被回流并被贴附于板件，而不导致第一管芯到板件的接合失败。

Description

倒装芯片接合合金
技术领域
本公开内容一般地涉及电路制造，并且更特别地涉及倒装芯片接合和布局技术。
背景技术
结合了倒装芯片设计的实施方式的多芯片模块越来越多地被用于各种各样的应用。在许多情况下，将既定的集成电路设计用于各种操作和/或功能是有利的。于是，可在制成的管芯中找得到的既定设计因此被结合于单个板件或多芯片模块上。但是，出于各种制造方面的考虑，各种集成电路器件，并且更具体地，倒装芯片器件，并非总是同时安装于多芯片模块内的。例如，不同的倒装芯片器件可能由不同的生产设备制造，并因此在不同的时间被添加到多芯片模块。目前有能够用来在不同的时间将管芯贴附于板件或模块的多种技术，包括丝线接合、管芯粘贴膜及焊接。这样的应用常常被使用，但并非总是适合于所有应用的。例如，在占用面积要求需要高效的集成电路(IC)基板面用法的情形中，丝线接合的解决方案可能并不适合。
焊料合金和浆料通常结合回流炉或箱来使用，以将管芯接合于板件。在一些情况下，使用任一种形式的焊料有益于将一个管芯接合于板件，例如，陶瓷板或基材板或者金属引线框，因为一旦焊料在被从回流炉或箱中移出之后冷却下来，可靠的接合就会形成。典型地，焊料合金或浆料在器件和板件被放入回流炉内时将会流动，并且然后将会冷却以将管芯接合于板件并(若需要)在器件与板件之间形成电连接。对于单管芯的情形，这种方法同样是有益的，因为如果有故障，则管芯可以通过随后在回流炉或箱内使管芯和板件回流来去除。但是，这种工艺典型地需要在管芯之间以及在管芯的接合焊盘之间有足够的空间，使得焊料在回流期间熔化时不会扩展而接触到正被回流的当前管芯或另一管芯的其他接合焊盘。
但是，使用焊料合金或浆料的另一个问题在于：在板件和另一个管芯被放入回流炉内以将新的管芯接合于板件时，焊料将会熔化并回流。因此，在焊料正于回流炉或箱内熔化以接合后续管芯时，粘接着原先已接合的管芯的键可能会失效。解决这个问题的一种方法已经是：给第一管芯使用不同的金属合金，使得接合管芯的金属合金具有比使焊料合金回流所需的温度高的回流温度。为此已经使用的两种金属包括铅和金，因为它们具有较高的熔化温度。但是，已知铅会造成健康问题，而且并非总是合意的。另一方面，金是昂贵的，会推高产品成本。在管芯或板件上形成将会随后被蚀刻掉并然后在回流期间被熔化的金层是对贵金属的浪费，除非这样的方法是必要的。因此，尽管焊料有其局限性，但通常也会被使用。
附图说明
通过参照根据各种实施例的附图，可以更好地理解本公开内容，并且本领域技术人员会很清楚本公开内容的众多特征和优点，在附图中：
图1是在第一倒装芯片接合于电路板之前电路板和第一倒装芯片的侧视图。
图2是在第一倒装芯片接合于电路板之前但在焊膏已经被回流成合金之后电路板和第一倒装芯片的侧视图。
图3是在第一倒装芯片接合于电路板之后且在焊膏已经被回流成合金之后的电路板和第一倒装芯片的侧视图。
图4是在第一倒装芯片接合于电路板之前电路板和第一倒装芯片的侧视图。
图5是在第一倒装芯片接合于电路板之前但在焊膏已经被回流成合金之后电路板和第一倒装芯片的侧视图。
图6是在第一倒装芯片接合于电路板之后并且在焊料合金已经与其他金属一起被回流成合金之后的电路板和第一倒装芯片的侧视图。
图7是示出了根据一种实施例的安装于板件或金属引线框上的第一倒装芯片的回流热分布的温度-时间曲线图。
图8是根据一种实施例的板件及安装于其上的多个倒装芯片的图示。
图9是根据一种实施例的板件及安装于其上的多个倒装芯片在后续回流以添加至少多一个倒装芯片或管芯之后的图示。
图10是根据一种实施例的板件及安装于其上的多个倒装芯片在后续回流以添加至少多一个倒装芯片或管芯之后的图示。
图11是示出根据一种实施例的用于接合倒装芯片的方法的流程图。
图12是示出根据一种实施例的用于接合多个倒装芯片的方法的流程图。
图13是示出根据一种实施例的用于接合多个倒装芯片的方法的流程图。
用于不同附图中的相同附图标记指示相似的或相同的项。除非另有说明，否则词语“耦合的(coupled)”及其关联的动词形式包括通过本技术领域已知的方式进行的直接连接和间接电连接，并且除非另有说明，否则任何关于直接连接的描述都同样隐含着使用间接电连接的合适形式的可替换实施例。
具体实施方式
图1是在第一倒装芯片接合于电路板之前电路板和第一倒装芯片的侧视图。图1示出了包含具有多个接合焊盘的硅管芯或倒装芯片10的***，每个接合焊盘都包含金属层12。包含锡和银的组合的焊膏14被沉积于包含金属层12的接合焊盘之上。板件16包含进一步含有金属层18和20的接合焊盘。管芯和板件的接合焊盘被形成为具有基本上相似的接合焊盘图形。板件16可以按照任何已知的方式来构造，并且可以包括例如陶瓷板或基材板。作为选择，金属引线框可以替代板件来使用。在下文中，在对板件、陶瓷板、基材板或金属引线框的任何引用被使用的任何时候，都应当理解，其他支撑结构元件中的任意一个(板件、陶瓷板、基材板或金属引线框)都能够可替换地使用。可选地，焊剂(flux)22可以被施加于倒装芯片或板件的接合焊盘的外金属层，用于防止氧化。在此，焊剂22仅被示于板件16的接合焊盘上。
板件16的金属层18和20包括至少一个可焊金属层，例如，银层、锡层或铜层。在所描述的实施例中，银层18和铜层20在按照基本上与倒装芯片10的接合焊盘图形类似的图形于板件16上创建接合焊盘之前使用。金属层18和20还可以包含多个金属或金属合金层，例如，铜(Cu)、镍(Ni)、锡(Sn)或银(Ag)或者由两种或更多种金属形成的合金。倒装芯片10可以包含两个或更多个层，尽管在不算上示于14处的焊膏凸块的情况下，在此仅示出一个层。虽然图1只示出了在倒装芯片10的接合焊盘上的一个层12以及在板件16的接合焊盘上的两个层18和20，但是实施例并没有受到限定并且管芯和板件可以包含另外的层。而且，另一个层可以是合金而不要求是单种元素或金属。层12的金属m1可以包括各种不同的金属或金属合金。在倒装芯片10上的金属层12在一种实施例中可以包括银、锡和镍的组合，尽管在所描述的实施例中使用了银金属层12。在一种可替换的实施例中，m1包括镍。
如图1所暗示的，倒装芯片10将被贴附于板件16(更具体地，贴附于板件16的接合焊盘的层18)。焊膏被用来与倒装芯片或板件的其他金属混合以在回流期间将倒装芯片接合于板件。但是，在此，在管芯和板件上的多个金属层的金属或金属合金被选择，使得它们在回流期间熔化或扩散以与焊膏14形成合金，从而具有比在初始金属层的回流以产生合金期间使用的温度高的后续回流温度。在所描述的实施例中，金属被选择，使得即使焊料或焊膏被使用，金属也将会熔化或扩散以与焊料混合，从而产生具有比对焊料进行回流所需的温度高的回流温度的合金。要对板件和一个或多个管芯进行“回流”，板件通常被放置于有规定的温度分布的回流炉或箱内达指定的时长。用于回流金属的其他技术同样可以用于可替换的过程中。在本文中，任何对箱或箱的引用都应当被理解为包括用于熔化或回流管芯和板件的金属层的可替换技术。
图2是在第一倒装芯片接合于电路板之前，但在一般示于图1的14处的焊膏已经被回流成合金之后电路板和第一倒装芯片的侧视图。图2示出了包含具有每个都包含金属层12的多个接合焊盘的硅管芯或倒装芯片10的***。之前沉积于金属层12的接合焊盘上的包含锡和银的组合的倒装芯片的焊膏14已经在低的回流温度进行回流以产生合金24。图2示出了用于对倒装芯片进行倒装芯片安装的方法，该方法典型地包括：在将倒装芯片安置于板件的接合焊盘之前，执行初始的低温回流以对锡/银焊膏进行回流，从而促使浆料硬化成合金24(在此，为基于焊膏的组成的银-锡合金)。在所描述的实施例中，该初始回流大约在230-235℃发生。在该温度，锡/银焊料将会熔化，但是银(以及倒装芯片10的其他金属层，若存在)不会熔化。如上所述，倒装芯片10包含含有至少一个金属层的接合焊盘。因此，焊膏14在第一回流之前被沉积于倒装芯片的接合焊盘上。在第一回流期间，所存在的任何焊剂及杂质被燃烧掉，并且第一合金24自金属浆料14形成而来。
图3是在第一倒装芯片接合于电路板之后且在焊膏已经被回流成具有其他金属的合金之后的电路板和第一倒装芯片的侧视图。如同前面所提到的，板件包含具有与倒装芯片的接合焊盘图形类似的接合焊盘图形的接合焊盘。在所描述的实施例中，板件的接合焊盘包含多个金属层。随后，在具有已经形成于其上的第一合金24的倒装芯片10被倒装芯片安装于板件上之后，板件和倒装芯片的第二回流随后在第二回流温度执行，以在倒装芯片的多个接合焊盘层(现在包含锡/银(Sn/Ag)金属层24)的每个层与板件的接合芯片的金属层之间形成第二合金26，如图3所示。
在所描述的实施例中，第二熔化温度为大约250℃。由第二回流形成的第二合金26具有比第二回流温度高的熔化温度(如，260℃)。在所描述的实施例中，第二合金26的熔化温度高于第二回流温度，并且可以比用来产生第二合金26的第二回流温度高至少10℃。例如，取决于被使用的金属和金属组合之比，合金26的熔化温度将会大于260℃并且可以为大约270℃。可以看出，第二合金26与倒装芯片10和板件16的层12、18和20的一些部分混合在一起。因为典型的回流温度为大约260℃，该温度比合金26的熔化温度低，所以合金26在后续的回流过程中不会完全熔化。对于本例，合金26具有来自层12、18和20的金属，但是这并不是必需的。最低程度下，合金26具有层12、18和20中的至少一种金属。
图4是在第一倒装芯片接合于电路板之前电路板和第一倒装芯片的侧视图。图4示出了包含具有包含多个金属层(即，金属层12、28和30)的多个接合焊盘的倒装芯片10的***。金属层12包含银。在所描述的实施例中，金属层28包含镍，而金属层30包含钛。包含锡和银的组合的焊膏14被沉积于倒装芯片10的接合焊盘的金属层12之上。
板件16包含还含有金属层18和20的接合焊盘。金属层18和20分别包含银和铜，像图1的实例那样。包含倒装芯片10的金属层12、28和30以及板件16的金属层18和20的接合焊盘图形基本上相似。板件16可以按照任何已知的方式来构造，并且可以包括例如陶瓷板或基材板。作为选择，金属引线框可以替代板件板件来使用。可选地，焊剂22可以被施加于倒装芯片或板件的接合焊盘的外金属层，用于防止氧化。在此，焊剂22仅被示于板件16的接合焊盘上。
板件16的金属层18和20包含至少一个可焊金属层，例如，银层、锡层或铜层。在所描述的实施例中，银层18和铜层20在蚀刻之前被使用，以按照基本上与倒装芯片10的接合焊盘图形类似的图形来创建接合焊盘。金属层18和20可以包含多个金属或金属合金层，例如，铜、镍、锡或银，或者由两种或更多种金属形成的合金。在倒装芯片上的金属层12、28和30在一种实施例中可以包含银、锡和镍的组合。在所描述的实施例中，金属层12、28和30分别包含银层、镍层和钛层。
虽然图4示出了在倒装芯片10上的三个金属层12、28和30以及在板件16上的两个层18和20，但是实施例并没有受到限定并且管芯和板件可以包含额外的层或数量更少的层。而且，任何一个层都可以是合金，并且不要求是单种元素或金属，如同本文关于图4所描述的。
如同在图4中所建议的，倒装芯片10应当贴附于板件16(更具体地，贴附于板件16的接合焊盘的层18)。焊膏被用来与倒装芯片或板件的其他金属混合，以将倒装芯片的接合焊盘接合于板件接合焊盘。但是，在此，在管芯和板件上的多个金属层的金属或金属合金被选择，使得它们在回流期间熔化或扩散以与焊膏14形成合金，该合金具有比在初始金属层的回流以产生合金24期间使用的温度高的后续熔化温度(如图5所示)。在所描述的实施例中，金属被选择，使得即使焊料或焊膏14被用来产生合金24，金属也将会熔化或扩散以与焊料合金24混合，从而产生具有比熔化焊料所需的温度高的熔化温度的合金。
图5是在第一倒装芯片接合于电路板之前但在焊膏已经被回流成合金之后电路板和第一倒装芯片的侧视图。图5示出了包含具有包含金属层12、28和30的多个接合焊盘的硅管芯或倒装芯片10的***。包含之前已经沉积于金属层12的接合焊盘上的锡和银的组合的焊膏14已经在低的回流温度进行回流以产生合金24，如图5所示。图5示出了用于对倒装芯片进行倒装芯片安装的方法，该方法典型地包括在将倒装芯片安置于板件的接合焊盘之前执行初始的低温回流以对锡/银焊膏进行回流，从而促使浆料硬化成合金24(在此，为基于焊膏的组成的银-锡合金)。
在所描述的实施例中，这种用于产生银/锡合金的初始回流大约在230-235℃发生。如上所述，倒装芯片10包含含有至少一个金属层的接合焊盘，尽管在此示出了三个金属层。因此，焊膏14在第一回流之前被沉积于倒装芯片的接合焊盘上。在第一回流期间，所存在的任何焊剂及杂质都被燃烧掉，并且第一合金24由金属浆料14形成，但是金属层12、28和30中没有一个会熔化，因为该第一回流温度在层12、28-30和18-20的回流温度以下。
图6是在第一倒装芯片接合于电路板之后并且在焊料合金已经与其他金属一起被回流成合金之后的电路板和第一倒装芯片的侧视图。同样还提到了，板件包含具有与倒装芯片10的接合焊盘图形相似的接合焊盘图形的连接点或接合焊盘。在所描述的实施例中，倒装芯片10和板件16的接合焊盘每个都包含多个金属层。随后，在具有已经形成于其上的第一合金24的倒装芯片10被倒装芯片安装于板件上之后，板件和倒装芯片的第二温度回流随后在第二回流温度执行，以在倒装芯片的接合焊盘层(现在包含Sn/Ag金属层24)的多个层中的至少一个层与板件16的接合焊盘的多个层之间形成第二合金32。
在所描述的实施例中，第二熔化温度为大约250℃。由第二回流形成的第二合金32具有比第二回流温度高的熔化温度。在所描述的实施例中，第二合金32的熔化温度比用来产生第二合金32的第二回流温度高至少10℃。例如，取决于被使用的金属和金属组合之比，合金32的熔化温度可以为大约270℃(该温度高出大约10-20℃)。
第二合金32包含来自倒装芯片和板件两者的金属。图6的实施例的一个方面在于，第二合金在第二回流期间产生，由于在之前的回流过程中形成的合金的更高的熔化温度，没有使先前已在之前的回流过程中接合的任何管芯的金属和合金层完全熔化或进行回流。
本发明的各种实施例的一个方面在于：用来将倒装芯片的接合焊盘接合于板件的接合焊盘的合金凸块被形成，具有比最初产生合金的回流温度高的后续熔化温度。另一个方面在于：合金的金属组成不仅基于用于倒装芯片和板件的接合焊盘的金属层，而且基于它们的相对厚度以及回流过程的持续时间。用于回流的温度分布定义了温度和时段两者。随着温度分布的时段增加，熔化和扩散的金属层的数量和量也增加，由此增加在合金32内的金属的数量或者改变在所产生的合金32内的金属之比。应当指出，因为金属之比可以根据初始的金属层厚度而逐渐改变，并且还基于用于产生合金的回流过程的总时长，所以所产生的合金可以不是均质的，这意味着可以产生金属间合金，而不是均质合金(整个合金的恒定比例)。因此，应当理解，术语“金属间”可以代替合金来使用更为合适，这取决于回流的结果。影响该结果的两种因素包括回流持续时间以及相对的层厚和构造。这里关于合金的所有讨论都应当被理解为对金属间合金的引用并且在适当的情况下包括金属间合金。
继续参照图6，如果回流进行最短的时间，则合金32可以由银和锡组成。随着回流时段根据回流分布而延长，额外的金属会熔化以变成合金32的一部分。例如，在增加的回流时段下，合金32可以包含镍以及银和锡。在增加到更大的回流时段下，合金32还可以包含钛(在所描述的实施例中来自倒装芯片，和/或来自板件的铜)。所产生的合金凸块的回流特性可以根据合金内的金属而改变。因此，回流温度分布以及(温度和持续时间)会影响到合金内有什么金属，并可能影响到在后续的回流期间的熔化温度。但是，在所有情况下，所产生的金属的熔化温度高于在为了熔化金属以产生合金的回流期间使用的温度。
在一种所描述的实施例中，用于倒装芯片的各种接合焊盘金属层的厚度如下：
钛：1.15kA(但是这能够被大幅度改变)。
镍：0.2kA(较厚的层可以用于较高温度的应用，或者如果厚的锡层被使用)。
银：4kA(能够在1kA-12kA间变动)
锡：2kA–36kA。
银-锡比可以基于应用来调整。例如，如果表面是粗糙或多孔的，则为了对于板件的额外浸润并帮助缩小空隙而增加锡合金。增加银会增大对镍的保护。但是，过多的银会限制待形成的NiSn金属间化合物的量，并且因此能够降低管芯的剪切强度以及倒装芯片的一致性。一般地，较高厚度的锡用于浸润的目的，但如果厚度过高，会出现制造问题。在一个具体的实施例中，锡层为22kA-26kA厚。
上述金属及相关的厚度的优点和好处在于：银和锡对空隙量最小的板件的可焊表面的浸润较好，快速地形成所产生的合金或金属间化合物，这会限制横过板件的银和锡的流动。此外，金属的熔化温度会快速上升到回流温度以上，用于防止未来在后续的回流期间熔化。因而，当其他器件被安装于板件并被回流时，倒装芯片将会在后续的回流期间留在原地。
取决于在回流期间使用的相对的金属层厚度和温度分布，来自板件的铜同样可以被熔化以变成在回流期间产生的合金的一部分。这会增强接合，以提供强的管芯粘接，并且会使所产生的合金中的镍和锡之比的量降低。还应当注意，在镍和锡之间的银会阻碍锡与镍之间的扩散，并限制镍/锡合金，这因此允许在倒装芯片和板件的接合焊盘之间产生更强的倒装芯片接合。
可得出类似结果的可替换的金属(纯金属和合金)层组合包括：
Ti/Ni/Cu/Ag/AgSn；
Ti/Ni/Cu/Sn；
Ti/Cu/Ag/AgSn；
Ti/Cu/Ag/Sn；
Ti/Cu/AgSn；以及
Ti/Cu/Sn。
各种实施例都会增加用于将倒装芯片或管芯接合焊盘接合于板件接合焊盘的焊料结或合金的熔化温度。一般地，该结构包含在包括钛、镍和银层的层状接合焊盘之上的银/锡的管芯或倒装芯片可焊表面。银/锡将倒装芯片接合于板件的可焊表面。在一种实施例中，板件的可焊表面包含银。作为选择，可焊表面包含铜。在又一种实施例中，可焊表面包含银和铜二者。
关于银/锡合金的使用，银/锡合金典型地具有≤6.5Wt％(重量百分比)的银的组成、在倒装芯片器件内的一个(至少一个)层，以浸润可焊表面，而没有使用额外的焊膏或预制件(preform)。一般地，该过程包括将银/锡焊膏或纯锡施加于可焊表面，例如，钛/镍/银，使得银/锡的最终组成为≤6.5Wt％的银。在这样的组成下，用于将浆料转化成合金的熔化温度为230-250℃。在一个具体的实施例中，在233-235℃的范围内的温度操作的回流炉或箱被用来熔化浆料以形成第一合金。
在大约250-260℃的后续回流期间，钛/镍/银/银-锡的可焊表面将会熔化以将管芯或倒装芯片接合于板件的可焊表面，并且产生在用来将额外的管芯贴附于板件的后续回流过程中将不会完全熔化的新合金。银/锡的金属间化合物由银-锡的顶层或者锡连同其他所描述的金属层一起形成，在后续的回流曲线下不会完全熔化。
图7是示出根据一种实施例的安装于板件或金属引线框上的第一倒装芯片的回流热分布的温度-时间曲线图。现在参照图7，该图示出了可识别出代表在根据一种实施例的过程中使用的各种热阶段的五个时间段p1-p5的回流热分布曲线图。可以看出，时段p1代表将回流炉进行预热到预热温度的加热升温。时段p2代表在典型的回流过程中使用的预热时段。时段p3代表到回流温度的加热升温。时段p4代表回流温度被保持的持续时间。时段p5反映了可允许合金硬化的冷却时段。
典型地，在现有技术的应用中，回流温度在给定传统的焊料元素的情况下并没有被维持达***著长的持续时间(这些焊料元素被用来使引线和器件相互接合或者将它们接合于印刷电路板)，因为它们在达到回流温度之前或当时会熔化。但是，在本申请，回流温度被保持至少直到达到时间t1。时间t1是熔化多种金属或使其扩散以形成合金并产生接合所需的时间量。该时间t1是关于什么金属正被熔化以及金属层的相对厚度的函数。而且，如同关于之前的附图所描述的，多个金属层可以被用于管芯或板件的至少一个上。
如果回流温度被保持超过时间t1至时间t2，则额外的合金可以由沉积于管芯或板件上的额外金属层形成。因此，在时间t2之后不久，代表冷却期的时段5开始。如同前面所描述的，由回流温度在时间t1和t2形成的合金具有比时段p4的回流温度高的后续的熔化温度。图7所代表的过程是用于第一管芯或者在同一回流中正被接合于板件的多个管芯或倒装芯片的回流过程。后续的回流可以使用相同的或相似的热分布，尽管特性会依据设计要求而改变。
图8是根据一种实施例的板件及安装于其上的多个倒装芯片的图示。可以包括基材板、陶瓷板或金属引线框的板件40包含多个接合焊盘器件图形42a-c。每个接合焊盘器件图形42a-c都具有与要于其上安装和接合的管芯或倒装芯片的接合焊盘图形基本上相似的接合焊盘图形。更具体地，接合焊盘器件图形42a和42b被调整大小并被配置用于接收更小的管芯或倒装芯片，如行44a、44b和44c所示，而接合焊盘器件图形42c被调整大小并被配置用于接收较大的管芯或倒装芯片，如行44d所示。
安装于板件40上的倒装芯片或管芯在根据一个或多个所描述的实施例来安装和接合时可以分离开很小的空间，大体如46处所示。相比之下，如果使用不会产生具有较高的熔化温度的合金的焊料，则如48处所示的相当大的分离是需要的，因为在回流和/或后续的回流期间，焊料将会熔化并且可以流动而在接近的接合焊盘或器件之间产生短路。因为本文所描述的过程不会像在标准焊料熔化温度的传统焊料那样流动，所以针对这些实施例描述过的过程和结构在将来可以用于很小尺寸的应用。
形成于集成电路内的晶体管的数量不断增加。同时，集成电路器件的尺寸正在显著缩小。芯片制造商一直依靠晶体管尺寸的持续缩小来实现晶体管数的指数增长，但是已知的用于接合管芯的技术会限制未来的缩小。例如，部分最新型的晶体管只有几个原子的厚度，并且因此，集成电路管芯的尺寸将会随着晶体管的缩小而缩小。虽然当前的器件现在小到了100微米(百万分之一米)，但是可以相信，未来的器件可以小到5-15皮米(pico-meters)宽。因此，在未来，人们会开发出小到人眼很难看见的整体集成电路。无论这样的规模是否可实际达到，应当肯定的是，当前缩小器件尺寸的趋势将会进行到当前用于接合器件的技术应当必须要修改的点。这样的集成电路或微管芯将必须被接合于主平台，例如，基板或陶瓷板或者具有连接点或接合焊盘的其他类型的封装。
该水平的集成将会由于构件的极小尺寸而难以实现。可能无法按照当前制造工艺所允许的方式单独对微电子的小构件图形化。虽然当前的集成电路能够具有几乎任意图形，但是这些微电子器件布局会受到物理处理局限的驱动。本实施例的一个方面在于：用于接合的焊料不会流动而在相邻的接合焊盘或连接点、引线或节点之间产生短路。因此，反过来参照图8，接合焊盘图形的布局允许具有最小空间(例如，如46处所示)的，而不是更多可观空间(例如，如48处所示)的个体管芯或倒装芯片的紧密布局，因为在接近的器件与接合焊盘之间产生短路的焊料流不是问题。此外，应当理解，图8的实施例可以代表今天正在制造的此类微电路以及倒装芯片器件。
图9是根据一种实施例的板件及安装于其上的多个倒装芯片在后续回流以添加至少多一个倒装芯片或管芯之后的图示。图9主要示出：即使在用于添加至少一个器件、倒装芯片或管芯的后续回流的情况下，所描述的实施例也允许器件被添加并进行回流以产生接合，而不破坏现有的接合或者在接近的接合焊盘和/或器件之间产生短路。可以看出，更小的管芯或倒装芯片被添加给示于44b处的器件行，并且较大的管芯或倒装芯片被添加给示于44d的器件行。应当指出，管芯可以被添加于板件的两侧。这里为了简单起见仅示出一侧。这适用于所有实施例。而且，本文所描述的实施例可以用于包含在两侧都有接合焊盘的堆叠式管芯的多芯片模块。
图10是根据一种实施例的板件及安装于其上的多个倒装芯片在后续回流以添加至少一个其他倒装芯片或管芯之后的图示。图10主要示出了：即使在用于添加至少一个器件、倒装芯片或管芯的后续回流(例如，第三回流)的情况下，所描述的实施例也允许器件被添加并进行回流以产生接合，而不破坏现有的接合或者在接近的接合焊盘和/或器件之间产生短路。可以看出，在两个后续的回流中，更小的倒装芯片被添加于44b和44c处所示的器件行，并且较大的倒装芯片被添加于44d处所示的器件行。在所有管芯或倒装芯片之间的空间46显著小于空间48，该空间48是如果在每次回流中都会熔化的常规焊锡被使用则会需要的空间。应当理解，由于所产生的具有较高熔化温度的合金的好处，因而在接合焊盘之间的空间也会减小。
图11是示出根据一种实施例的用于接合管芯的方法的流程图。图11的方法开始于在晶圆形式的管芯上形成至少一个金属层(102)。其后，该至少一个金属层被蚀刻以形成接合焊盘(104)。在接合焊盘形成于管芯上之后，管芯被倒装芯片安装于具有多个匹配的接合焊盘的板件上(106)。在所描述的实施例中，板件是可焊板件。可焊板件可以包括用于固定或连接电子器件的任何类型的已知板件，包括陶瓷板和基材板或金属引线框。在一种实施例中，被用来产生板件的接合焊盘的可焊板件的金属层是可焊金属层，例如，锡或铜。在所公开的实施例中，板件包含形成于一个表面上的两个金属层，而管芯包含至少一个可焊金属层。管芯被安置于板件上，使得板件和第一管芯的外金属层彼此接触。
其后，该方法包括在第一回流温度执行第一温度的回流，以燃烧掉焊剂和杂质中的至少一种，并且由金属浆料中形成第一合金，如果浆料被使用(108)。其后，该方法包括在板件和管芯的第二回流温度执行第二温度的回流，以在焊膏被使用时，在管芯和板件的接合焊盘的多个金属层中的每个金属层与在第一回流期间产生的第一合金之间形成第二合金(110)。
用于这些回流的温度分布可以包括到规定温度的温度上升和开始冷却时段，或者到期望温度的上升并然后在足以允许金属层进行回流的指定的时段或持续时间内维持该温度或温度范围，以产生至少一种合金。本文对温度分布的引用包括用来熔化管芯和板件金属层以产生期望的合金和/或金属间化合物的温度和时间的任意组合。该方法可选地包括在一种合金已经产生之后根据第二温度分布继续进行回流(例如，在第一回流温度分布进行达第二时段)，以继续对第一管芯以及管芯和板件的一个或多个金属层进行回流，从而形成第三合金(112)。
在第一回流过程结束并且任何所形成的合金已经冷却并硬化之后，该方法包括将第二管芯或倒装芯片(或者多个第二管芯或倒装芯片)安置于可焊板件上，并且将具有第一及第二管芯的板件放置于回流炉或烤炉内(112)。其后，第二管芯和板件金属层根据第三回流温度分布进行回流，而没有使在第一回流过程中产生的第一管芯和板件的任何合金金属完全发生回流。第二管芯和板件的金属层被回流以形成用于第二管芯和板件的第四合金(114)。最后，该方法可任选地包括根据第四温度分布继续对第二管芯和板件的金属层进行回流以形成用于第二管芯的第五合金(116)。应当理解，第一、第二、第三及第四温度分布可以是近似的也可以是不同的。同样地，所产生的第二、第三、第四及第五合金和/或金属间化合物基于温度分布和金属层组成，并因此可以是相似的或不同的。
图12是示出根据一种实施例的用于接合多个管芯的方法的流程图。该方法开始于在没有于管芯之间留下空间让熔化的金属流动的情况下将第一多个管芯倒装芯片安装于被蚀刻于板件或金属引线框上的多个接合焊盘上(120)。其后，该方法包括执行多次回流以产生含有来自管芯和板件两者的接合焊盘金属层的金属元素的多种合金(122)。随后，该方法包括将第二多个管芯倒装芯片安装于被蚀刻于板件或金属引线框上的第二多个接合焊盘上，而在管芯之间没有留下让熔化金属流动的空间(124)。最后，该方法结束于：执行多次回流以产生含有来自管芯和板件两者的接合焊盘金属层的金属元素的多种合金(126)。
图12所示的方法的一个方面在于：熔化并从其接合焊盘中流走的焊料不是关于根据各种实施例的管芯或倒装芯片安装和接合而执行的回流的问题。因此，个体管芯/倒装芯片可以被排列并被安置得非常接近。
图13是示出根据一种实施例的用于接合多个芯片的方法的流程图。该方法开始于：将第一管芯倒装芯片安装于板件接触焊盘上(102)并且将第一管芯和板件放置于回流炉或烤炉内(104)。其后，该方法包括根据第一回流温度分布对第一管芯以及可焊板件金属层进行回流，以形成第一合金(106)。该第一回流典型地用于燃烧掉杂质和焊剂，并且用于由焊膏形成出合金，如果焊膏正被用于该过程。
其后，该方法继续进行：根据第二回流温度分布进行回流，以继续对第一管芯进行回流，从而形成第二合金(108)。该第二合金包含来自管芯接合焊盘金属层和/或焊膏的至少一种金属以及来自可焊板件接合焊盘金属层的至少一种金属。其后，该方法包括继续对第一管芯和板件进行回流，以形成第三合金(110)。
在所描述的实施例中，至少三种金属被用于该过程中。在第二回流中，至少一种金属熔化以形成包含来自别的层的扩散金属的第二合金。通过继续对倒装芯片/管芯和板件进行回流，第三金属熔化并与第一及第二金属混合，以形成包含至少三种金属的第三合金。在该过程完成并且合金被允许冷却并硬化之后，该方法包括将第二管芯倒装芯片安装于具有多个金属层的板件接合焊盘上(112)，并且将第二管芯和具有已接合的第一管芯的板件两者放置于回流炉或烤炉内(114)，根据第四回流温度分布在没有使第一管芯完全回流的情况下对第二管芯进行回流以形成第四合金(116)。如同第一合金那样，如果在该过程中使用焊膏的话，则这里形成的第四合金来自焊膏。其后，该方法包括根据第五回流温度分布进行回流，以在没有使第一管芯回流的情况下对第二管芯进行回流，从而形成第五合金(118)，类似于第二合金。最后，该方法包括可选地继续进行回流，以形成第六合金(120)。
以上关于附图的讨论和描述涉及将管芯或倒装芯片的接合焊盘粘接于板件的接合焊盘。以上所公开的主题应当被认为是说明性的，而不是限制性的，并且所附的权利要求书意指覆盖属于本权利要求书的真实范围之内的所有此类修改、改进及其他实施例。
例如，根据所公开的装置和方法的一个方面，板件接合焊盘包含铜。
根据另一个方面，第一管芯的多个接合焊盘的至少两个金属层包括钛层。
根据又一个方面，合金包括锡、银和铜的合金或者锡和银的合金中的一种。
因而，在法律允许的最大范围内，本发明的范围应当由关于后面的权利要求书及其等同形式的最宽泛的可行解释来确定，并且不应受以上的详细描述所制约或限定。

Claims (10)

1.一种用于将至少一个管芯倒装芯片安装于板件上的方法，包括：
在具有至少一个金属层的第一管芯上形成多个可焊接合焊盘；
将可焊浆体或凸块中的一个沉积于所述第一管芯上的所述多个可焊接合焊盘中的至少一个可焊接合焊盘上或者沉积于所述板件上的多个匹配的接合焊盘上，所述板件的所述多个匹配的接合焊盘每个都具有至少两个金属层；
在第一回流温度执行第一回流以燃烧掉焊剂和杂质中的至少一种并且融化所述可焊浆体或凸块，从而形成第一合金；
将所述第一管芯倒装芯片安装于所述板件上；以及
在第二回流温度执行第二回流以融化所述第一合金的至少一部分，从而形成具有比所述第二回流温度高的熔化温度的第二合金，所述第二合金包含来自所述管芯和所述板件中的至少一个的接合焊盘的金属；以及
随后将第二管芯倒装芯片安装于板件，以及使第一管芯和第二管芯经历第一回流温度和第二回流温度，由此将第二管芯安装到板件上。
2.根据权利要求1所述的方法，其中所述第一管芯包含具有钛层、镍层和银层的接合焊盘。
3.根据权利要求1所述的方法，其中所述板件的接合焊盘包括铜层和银层。
4.根据权利要求1所述的方法，其中所述第二合金包含来自所述第一管芯和板件两者的金属层的金属。
5.根据权利要求1所述的方法，还包括：
在没有完全融化所述第一管芯和所述板件的任何金属层的情况下将第二管芯倒装芯片安装于所述板件上并且使所述第二管芯和所述板件经历回流温度分布；以及
在倒装芯片安装所述第二管芯之前将金属浆体沉积于所述第一管芯上的接合焊盘的顶层金属层之上。
6.一种电子装置，包括：
板件，所述板件进一步包含成板件接合焊盘图形的多个接合焊盘，每个接合焊盘都具有至少一个金属层；
第一管芯，所述第一管芯包括具有与所述板件接合焊盘图形匹配的管芯接合焊盘图形的多个接合焊盘，其中所述第一管芯被倒装芯片安装于所述板件上；
其中：
所述第一管芯的所述多个接合焊盘包含至少两个金属层；并且
所述板件的所述多个接合焊盘和所述第一管芯的匹配的所述多个接合焊盘以合金来接合，所述合金具有比用来在对应的第一回流操作和第二回流操作期间通过沉积在所述多个接合焊盘上的可焊浆体或凸块中的一个来接合所述板件接合焊盘以及所述第一管芯的匹配的所述多个接合焊盘的第一回流温度和第二回流温度高的熔化温度；以及
所述板件还包括用于在第一管芯被倒装芯片安装于板件之后安装第二管芯的接合焊盘器件图形。
7.根据权利要求6所述的电子装置，其中所述第一管芯的所述多个接合焊盘包含包括银和锡的至少三个金属层，并且所述板件的所述多个接合焊盘包含至少两个金属层。
8.根据权利要求7所述的电子装置，其中所述第一管芯的所述多个接合焊盘中的至少两个金属层包括银层和镍层。
9.根据权利要求7所述的电子装置，其中所述板件的所述至少两个金属层包括银层和铜层。
10.根据权利要求7所述的电子装置，还包含多个管芯，所述多个管芯被倒装芯片安装得非常接近，而没有任何金属或合金连接相邻管芯的接合焊盘。
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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10568213B2 (en) 2014-07-31 2020-02-18 Skyworks Solutions, Inc. Multilayered transient liquid phase bonding
US10965269B2 (en) 2016-12-02 2021-03-30 Skyworks Solutions, Inc. Electronic devices formed in a cavity between substrates and including a via
DE102017108422A1 (de) * 2017-04-20 2018-10-25 Osram Opto Semiconductors Gmbh Verfahren zum Befestigen eines Halbleiterchips auf einem Leiterrahmen und elektronisches Bauelement
US10600755B2 (en) * 2017-08-10 2020-03-24 Amkor Technology, Inc. Method of manufacturing an electronic device and electronic device manufactured thereby
US10347602B1 (en) * 2018-07-23 2019-07-09 Mikro Mesa Technology Co., Ltd. Micro-bonding structure
US10388627B1 (en) * 2018-07-23 2019-08-20 Mikro Mesa Technology Co., Ltd. Micro-bonding structure and method of forming the same
CN111373553B (zh) * 2019-12-30 2022-01-07 重庆康佳光电技术研究院有限公司 一种发光器件及其制备方法、显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070114662A1 (en) * 2005-11-17 2007-05-24 Johann Helneder Interconnecting element between semiconductor chip and circuit support and method
US20070205253A1 (en) * 2006-03-06 2007-09-06 Infineon Technologies Ag Method for diffusion soldering
CN103151092A (zh) * 2011-12-06 2013-06-12 富士通株式会社 导电接合材料、电子组件和电子装置
US20150001704A1 (en) * 2013-06-26 2015-01-01 Taiwan Semiconductor Manufacturing Co., Ltd Mechanisms for forming hybrid bonding structures with elongated bumps
CN104733424A (zh) * 2013-12-24 2015-06-24 瑞萨电子株式会社 半导体器件及其制造方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5186383A (en) * 1991-10-02 1993-02-16 Motorola, Inc. Method for forming solder bump interconnections to a solder-plated circuit trace
DE19531158A1 (de) 1995-08-24 1997-02-27 Daimler Benz Ag Verfahren zur Erzeugung einer temperaturstabilen Verbindung
JP4742844B2 (ja) * 2005-12-15 2011-08-10 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US7508012B2 (en) 2006-01-18 2009-03-24 Infineon Technologies Ag Electronic component and method for its assembly
DE102006013853B4 (de) 2006-03-23 2010-09-30 Infineon Technologies Ag Leistungshalbleiterbauelement mit großflächigen Außenkontakten sowie Verfahren zur Herstellung desselben
US20090160039A1 (en) * 2007-12-20 2009-06-25 National Semiconductor Corporation Method and leadframe for packaging integrated circuits
US8610270B2 (en) 2010-02-09 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and semiconductor assembly with lead-free solder
US8348139B2 (en) * 2010-03-09 2013-01-08 Indium Corporation Composite solder alloy preform
US9312240B2 (en) * 2011-01-30 2016-04-12 UTAC Headquarters Pte. Ltd. Semiconductor packages and methods of packaging semiconductor devices
US8431445B2 (en) 2011-06-01 2013-04-30 Toyota Motor Engineering & Manufacturing North America, Inc. Multi-component power structures and methods for forming the same
US9773744B2 (en) 2011-07-12 2017-09-26 Globalfoundries Inc. Solder bump cleaning before reflow
TW201320207A (zh) 2011-11-15 2013-05-16 Ableprint Technology Co Ltd 抑制濺錫之迴焊方法
US9219030B2 (en) * 2012-04-16 2015-12-22 Taiwan Semiconductor Manufacturing Co., Ltd. Package on package structures and methods for forming the same
US9516749B2 (en) * 2012-07-04 2016-12-06 Panasonic Intellectual Property Management Co., Ltd. Electronic component-mounted structure, IC card and COF package
WO2014023320A1 (de) 2012-08-10 2014-02-13 Gottfried Wilhelm Leibniz Universität Hannover Verfahren zum herstellen eines hermetisch abgeschlossenen gehäuses
US9111793B2 (en) * 2013-08-29 2015-08-18 International Business Machines Corporation Joining a chip to a substrate with solder alloys having different reflow temperatures
US9355980B2 (en) * 2013-09-03 2016-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional chip stack and method of forming the same
KR101430673B1 (ko) 2013-11-05 2014-08-19 주식회사 케이이씨 반도체 디바이스 및 이의 다이 본딩 구조
US9925612B2 (en) * 2014-07-29 2018-03-27 Panasonic Intellectual Property Management Co., Ltd. Semiconductor component, semiconductor-mounted product including the component, and method of producing the product

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070114662A1 (en) * 2005-11-17 2007-05-24 Johann Helneder Interconnecting element between semiconductor chip and circuit support and method
US20070205253A1 (en) * 2006-03-06 2007-09-06 Infineon Technologies Ag Method for diffusion soldering
CN103151092A (zh) * 2011-12-06 2013-06-12 富士通株式会社 导电接合材料、电子组件和电子装置
US20150001704A1 (en) * 2013-06-26 2015-01-01 Taiwan Semiconductor Manufacturing Co., Ltd Mechanisms for forming hybrid bonding structures with elongated bumps
CN104733424A (zh) * 2013-12-24 2015-06-24 瑞萨电子株式会社 半导体器件及其制造方法

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