CN106301369B - Position round-robin method that is a kind of while improving analog-digital converter SFDR and SNR - Google Patents
Position round-robin method that is a kind of while improving analog-digital converter SFDR and SNR Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1009—Calibration
- H03M1/1033—Calibration over the full range of the converter, e.g. for correcting differential non-linearity
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/462—Details of the control circuitry, e.g. of the successive approximation register
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Abstract
A kind of position round-robin method for improving analog-digital converter SFDR and SNR simultaneously of the disclosure of the invention, the technical field of application is the high-precision adc in Microelectronics and Solid State Electronics field.Position round-robin method proposed by the present invention is suitable for the gradually-appoximant analog-digital converter of any structure, its core concept is to split highest order (MSB) capacitor and time high-order (MSB-1) capacitor, capacitor array is divided into four groups, twice to the conversion of the same input voltage, transformation result is averaging to obtain corresponding digital output code twice, in conversion process, each position circulation all changes capacitor order, achievees the effect that capacitance error consecutive mean.Therefore, compared with tradition relies on the bearing calibration of correction DAC and correcting algorithm to improve the linearity, have the effect of that structure is simpler, chip occupying area is smaller, be easier to realize on piece.
Description
Technical field
The present invention relates to a kind of novel gradually-appoximant analog-digital converter (SAR ADC:Successive
Approximation Register Analog-to-Digital Converter) position round-robin method, direct applied technology
Field is the high-precision adc in Microelectronics and Solid State Electronics field.
Background technique
In system on chip, analog-digital converter (ADC:Analog-to-Digital Converter) is connection simulation system
System and the bridge of digital information processing system (DSP:Digital Signal Processor), most of signal in nature
It is all being macroscopically analog quantity, what our mankind can directly perceive is also all analog signal, such as light, sound, pressure and temperature
Degree etc., therefore effect of the data converter in SoC is most important, as shown in Figure 1, it converts analog signals into digital signal
It send to DSP and is handled, processing result is converted to analog signal using digital analog converter, and the performance of analog-digital converter is to system
Stability, reliability and persistence all have significant effect.
Requirement of the different applications to analog-digital converter characteristic is also different, and the design of high-performance analog-digital converter is always
It is one of the difficult point of design of integrated circuit.Although high speed, high-precision and low-power consumption are the important developments of analog-digital converter
Direction, but be not the performance indicator for measuring analog-digital converter, with the continuous improvement of system on chip degree, measure analog-to-digital conversion
The performance indicator of device also tends to diversification, and wherein dynamic indicator mainly includes signal-to-noise ratio (SNR:Signal-to-Noise
Ratio), signal noise distortion is than (SNDR:Signal-to-Noise-and-Distortion Ratio), total harmonic distortion
(THD:Total Harmonic Distortion), spurious-free dynamic range (SFDR:Spurious-Free Dynamic
) and effective accuracy (ENOB:Effective Number of Bits) etc. Range.The dynamic property and electricity of analog-digital converter
It is closely related to hold matching.
In order to adapt to the application requirement of different systems on chip, analog-digital converter also occurs more during its continuous development
Kind structure type, analog-digital converter mainly includes all-parallel A/D converter, production line analog-digital converter and over-sampling at present
Analog-digital converter, compared to the analog-digital converter of the several types such as assembly line, over-sampling and full parellel, Approach by inchmeal analog-to-digital conversion
Device has many advantages, such as that structure is simple, area is small, easy of integration, easy realize may be programmed, and has been widely used for touch screen, industry control
The systems such as system, biologic medical and wireless sensor network.
Traditional capacitive gradually-appoximant analog-digital converter of three level binaries as shown in Fig. 2, its working principle include sampling,
Keep and three processes of Charge scaling, the matching of capacitor be the key that determine gradually-appoximant analog-digital converter dynamic property because
Element, especially in high-precision applications, the matching problem of gradually-appoximant analog-digital converter capacitor is challenging always difficulty
Topic, this is because being limited by state-of-the-art, capacitor can only meet 10 matching precisions, it is not easy to realize high-precision, it is false
If it is C that specific capacitance C, which obeys mean value,0, standard deviation σcNormal distribution, i.e. C~N (C0,σc), then the m being connected in parallel
It is mC that a capacitor, which will obey mean value,0, standard deviation isNormal distribution, can indicate are as follows:Document [Y.-H.Chung, M.-H.Wu, and H.-S.Li, " A 12-bit 8.47-fJ/
Conversion-Step Capacitor-Swapping SAR ADC in 110-nm CMOS”,IEEE Trans.on
Circuits and Systems-I, vol.62, no.1, pp.10--18, Jan.2015.] it is mutual using high-low position capacitor array
The position round-robin method changed can effectively improve SFDR, but can not improve SNR, document [John G.Kauffman, Pascal
Witte,Matthias Lehmann,Joachim Becker,Yiannos Manoli and Maurits Ortmanns,“A
72dB DR,CTΔΣModulator Using Digitally Estimated,Auxiliary DAC Linearization
Achieving 88fJ/conv-step in a 25MHz BW”,IEEE J.Solid-State Circuits,vol.49,
No.2, pp.392--404, Feb.2014.] capacitance mismatch is corrected using foreground analog correction technology, it needs to interrupt mould
The normal work of number converter cannot improve SNR, document [W.Liu, P.Huang, and although SFDR can be significantly improved
Y.Chiu,“A 12-bit 50-MS/s 3.3-mW SAR ADC with background digital calibration”,
Proc.of IEEE CICC, pp.1--4, Sept.2012.] use " least mean-square error " (LMS:Least Mean
Square) algorithm corrective capacity mismatch, and based on the correcting scheme of LMS algorithm under conditions of given error modeling, precision
High and calibration effect is good, if but initial value choose improper, will lead to algorithm complexity increase, even result in algorithm and do not restrain etc. and ask
Topic is not easy on piece realization, cannot equally improve SNR.
Summary of the invention
Existing capacitance mismatch alignment technique can only improve SFDR, cannot improve SNR, the present invention is in view of the deficiencies of the prior art
Place Curve guide impeller is a kind of to improve SFDR and SNR simultaneously, do not need to introduce correction DAC, do not interrupt the normal work of analog-digital converter
Make, structure is simpler, chip occupying area is smaller, the gradually-appoximant analog-digital converter that can be improved that is easier to realize on piece moves
The position round-robin method of state property energy.Position round-robin method proposed by the present invention is suitable for the gradually-appoximant analog-digital converter of any structure,
Its core concept is fractionation highest order (MSB) capacitor and time high-order (MSB-1) capacitor, capacitor array is divided into four groups, to same
Twice, transformation result is averaging to obtain corresponding digital output code twice, in conversion process, every time for one input voltage conversion
Position circulation all changes capacitor order, achievees the effect that capacitance error consecutive mean.To round-robin method base in position proposed by the present invention
It is illustrated in 12 capacitive gradually-appoximant analog-digital converters of three level binaries of Fig. 2, as shown in Fig. 2, 12 three level
Binary capacitor type gradually-appoximant analog-digital converter is made of capacitor DAC, comparator and digital control circuit, compares sectional capacitance
Type structure, binary capacitor type structure is not due to having floating node, so the linearity is more preferable than segmentation capacitive structure.
The technical scheme is that a kind of position round-robin method for improving analog-digital converter SFDR and SNR simultaneously, this method
Include:
Step 1: all specific capacitances in binary capacitor type gradually-appoximant analog-digital converter are equally divided into 4 groups, first
When secondary conversion, first and second group of capacitor is as highest order, and third group capacitor is as a time high position, to first input voltage vin (1)
Position circulation is carried out after sampling, generates the output codons Dout (1) _ 1 for corresponding to first input voltage vin (1)；
Step 2: when second of conversion, resampling, does not still convert first input voltage vin (1), the
Two, three groups of capacitors are as highest order, and as a secondary high position, second of conversion is still generated to be inputted the 4th group of capacitor corresponding to first
The output codons Dout (1) _ 2 of voltage Vin (1)；Dout (1) _ 1 and Dout (1) _ 2 two code word are averaging, corresponded to
The code word Dout (1) of first input voltage vin (1)；
Step 3: when third time is converted, third and fourth group of capacitor is used as highest order, and first group of capacitor is as a time high position, to the
Position circulation is carried out after two input voltage vin (2) samplings, generates the output codons for corresponding to second input voltage vin (2)
Dout(2)_1；
Step 4: when the 4th conversion, resampling, does not still convert second input voltage vin (2), the
One, four groups of capacitors are as highest order, and for second group of capacitor as a time high position, the 4th conversion, which still generates, corresponds to second input
The output codons Dout (2) _ 2 of voltage Vin (2)；Dout (2) _ 1 and Dout (2) _ 2 two code word are averaging, corresponded to
The code word Dout (2) of second input voltage vin (2)；
Step 5: when the 5th conversion, third and fourth group of capacitor is as highest order, and first group of capacitor is as time high-order, to the
Position circulation is carried out after three input voltage vin (3) samplings, generates the output codons for corresponding to third input voltage vin (3)
Dout(3)_1；
Step 6: when the 6th conversion, resampling, does not still convert third input voltage vin (3), the
Two, three groups of capacitors correspond to third and input as highest order, the 4th group of capacitor as a time high position, the 6th conversion still generation
The output codons Dout (3) _ 2 of voltage Vin (3)；Dout (3) _ 1 and Dout (3) _ 2 two code word are averaging, corresponded to
The code word Dout (3) of third input voltage vin (3)；
During ADC subsequent output codons, the mode of the 7th conversion is identical as first time, the mode of the 8th conversion
It is identical as second, it circuits sequentially.
The present invention proposes a kind of position round-robin method that can improve gradually-appoximant analog-digital converter SFDR and SNR simultaneously, special
Point is: not needing to introduce any correcting algorithm, does not need to introduce correction DAC, and do not interrupt analog-digital converter normal work.
Position round-robin method proposed by the present invention can improve SFDR and SNR simultaneously, therefore, rely on correction DAC and correcting algorithm with tradition
It is compared to improve the bearing calibration of the linearity, with structure is simpler, chip occupying area is smaller, is easier to realize on piece
Effect.
Detailed description of the invention
Fig. 1 is the effect of data converter.
Fig. 2 is 12 capacitive gradually-appoximant analog-digital converters of three level binaries.
Fig. 3 is the position round-robin method proposed by the present invention for gradually-appoximant analog-digital converter capacitor array.
Fig. 4 is 12 gradually-appoximant analog-digital converters FFT simulation result proposed by the present invention.
Fig. 5 is traditional 12 gradually-appoximant analog-digital converter FFT simulation results.
Specific embodiment
The present invention proposes a kind of position round-robin method that can improve gradually-appoximant analog-digital converter SFDR and SNR simultaneously, such as Fig. 3
It is shown, (MSB) capacitor of highest order in Fig. 2 1024C is split into 256C, 128C ... C, C and 256C, 128C ... C, C two group capacitor,
A secondary high position (MSB-1) capacitor 512C splits into 256C, 128C ... 2048 specific capacitances in Fig. 2 are divided into four groups by C, C, this
Four groups of capacitors indicate that first group of capacitor C31~C40 is indicated with black in Fig. 3 with different colors, second group of capacitor C21~
C30 indicates that third group capacitor C11~C20 is indicated with red with purple, and the 4th group of capacitor C1~C10 indicates that every group equal with blue
Comprising 512 specific capacitances, i.e. 256C, 128C ... C, C, twice to the conversion of the same input voltage, transformation result asks flat twice
Corresponding digital output code is obtained, in conversion process, each position circulation uses different capacitor combinations, realizes capacitance error
Consecutive mean, to achieve the purpose that while improve SNR and SFDR.
It converts for the first time: to progress position circulation after first input voltage vin (1) sampling, highest order (MSB) capacitor
1024C is collectively constituted by first and second group of capacitor (C21~C40), and a secondary high position (MSB-1) capacitor 512C is by third group capacitor (C11
~C20) composition, C2~C10 is as bit capacitor, output codons Dout of the generation corresponding to first input voltage vin (1)
(1)_1；
Second of conversion: not resampling is still converted first input voltage vin (1), highest order (MSB)
Capacitor 1024C is collectively constituted by second and third group of capacitor (C11~C30), and a secondary high position (MSB-1) capacitor 512C is by the 4th group of capacitor
(C1~C10) composition, for C32~C40 as bit capacitor, second of conversion, which still generates, corresponds to first input voltage vin
(1) output codons Dout (1) _ 2；Dout (1) _ 1 and Dout (1) _ 2 two code word are averaging, obtain corresponding to first
The code word Dout (1) of input voltage vin (1)；
Third time is converted: to progress position circulation after second input voltage vin (2) sampling, highest order (MSB) capacitor
1024C is collectively constituted by third and fourth group of capacitor (C1~C20), a secondary high position (MSB-1) capacitor 512C by first group of capacitor (C31~
C40 it) forms, C22~C30 generates the output codons Dout for corresponding to second input voltage vin (2) as bit capacitor
(2)_1；
4th conversion: not resampling is still converted second input voltage vin (2), highest order (MSB)
Capacitor 1024C is collectively constituted by first, fourth group of capacitor (C1~C10, C31~C40), and a secondary high position (MSB-1) capacitor 512C is by
Two groups of capacitor (C21~C30) compositions, C12~C20 still generate defeated corresponding to second as bit capacitor, the 4th conversion
Enter the output codons Dout (2) _ 2 of voltage Vin (2)；Dout (2) _ 1 and Dout (2) _ 2 two code word are averaging, corresponded to
In the code word Dout (2) of second input voltage vin (2)；
5th conversion: to progress position circulation after third input voltage vin (3) sampling, highest order (MSB) capacitor
1024C is collectively constituted by third and fourth group of capacitor (C1~C20), a secondary high position (MSB-1) capacitor 512C by first group of capacitor (C31~
C40 it) forms, C22~C30 generates the output codons Dout for corresponding to third input voltage vin (3) as bit capacitor
(3)_1；；
6th conversion: not resampling still converts third input voltage vin (3), highest order (MSB)
Capacitor 1024C is collectively constituted by second and third group of capacitor (C11~C30), and a secondary high position (MSB-1) capacitor 512C is by the 4th group of capacitor
(C1~C10) composition, for C32~C40 as bit capacitor, the 6th conversion, which still generates, corresponds to third input voltage vin
(3) output codons Dout (3) _ 2；Dout (3) _ 1 and Dout (3) _ 2 two code word are averaging, obtain corresponding to third
The code word Dout (3) of input voltage vin (3)；
During ADC subsequent output codons, during ADC output codons, the mode of the 7th conversion and first time
Identical, the mode of the 8th conversion is identical as second, circuits sequentially.
12 gradually-appoximant analog-digital converter FFT simulation results proposed by the present invention are as shown in figure 4, specific capacitance value is
10f, specific capacitance mismatch errorIt is 0.04, and 12 gradually-appoximant analog-digital converter FFT simulation result such as Fig. 5 of tradition
It is shown.
Table 1 summarizes 12 gradually-appoximant analog-digital converters of tradition and 12 Approach by inchmeal analog-to-digital conversions proposed by the present invention
The performance comparison of the SFDR emulation of device.Table 1 shows: comparing the capacitive gradually-appoximant analog-digital converter of traditional resistor, the present invention will
SFDR improves 23dB, and SNR improves 5.2dB.
The present invention approaches analog-digital converter for conventional successive and proposes a kind of new position circulating technology, it is only necessary to by highest
Two capacitors are split, and all use different capacitor combinations in each position circulation, so that it may which the optimization for realizing dynamic property is compared
Conventionally employed correction DAC technique or correcting algorithm are come the method for improving dynamic property, and control logic of the present invention is simple, and hardware is opened
It sells small, power consumption and chip area can be saved.
Table 1: SFDR, SNR of tradition 12 SAR ADC and 12 SAR ADC proposed by the present invention is compared
| SFDR(dB) | SNR(dB) | |
| 12 SAR ADC of tradition | 62.8 | 65.3 |
| 12 SAR ADC proposed by the present invention | 85.8 | 70.5 |
Claims (1)
1. a kind of position round-robin method for improving analog-digital converter SFDR and SNR simultaneously, this method comprises:
Step 1: the highest order capacitor in binary capacitor type gradually-appoximant analog-digital converter is split as except highest order capacitor and
The identical two groups of capacitors of bit capacitor array except secondary high position capacitor, number is first group and second group of capacitor array；It will be secondary
High-order capacitor is split as except the identical capacitor array of bit capacitor array of the highest order capacitor in addition to time high-order capacitor, and number is
Third group capacitor；Remaining bit capacitor array is the 4th group of capacitor；
When converting for the first time, first and second group of capacitor is as highest order, and third group capacitor is as a time high position, to first input electricity
It presses Vin (1) sampling to carry out position circulation later, generates the output codons Dout (1) _ 1 for corresponding to first input voltage vin (1)；
Step 2: when second of conversion, resampling, does not still convert first input voltage vin (1), second and third
Group capacitor is as highest order, and for the 4th group of capacitor as a time high position, second of conversion, which still generates, corresponds to first input voltage
The output codons Dout (1) _ 2 of Vin (1)；Dout (1) _ 1 and Dout (1) _ 2 two code word are averaging, obtain corresponding to first
The code word Dout (1) of a input voltage vin (1)；
Step 3: when third time is converted, third and fourth group of capacitor is as highest order, and first group of capacitor is as a time high position, to second
Position circulation is carried out after input voltage vin (2) sampling, generates the output codons Dout for corresponding to second input voltage vin (2)
(2)_1；
Step 4: when the 4th conversion, resampling, is not still converted second input voltage vin (2), first, fourth
Group capacitor is as highest order, and for second group of capacitor as a time high position, the 4th conversion, which still generates, corresponds to second input voltage
The output codons Dout (2) _ 2 of Vin (2)；Dout (2) _ 1 and Dout (2) _ 2 two code word are averaging, obtain corresponding to second
The code word Dout (2) of a input voltage vin (2)；
Step 5: when the 5th conversion, third and fourth group of capacitor is as highest order, and first group of capacitor is as a time high position, to third
Position circulation is carried out after input voltage vin (3) sampling, generates the output codons Dout for corresponding to third input voltage vin (3)
(3)_1；
Step 6: when the 6th conversion, resampling, does not still convert third input voltage vin (3), second and third
Group capacitor is as highest order, and for the 4th group of capacitor as a time high position, the 6th conversion, which still generates, corresponds to third input voltage
The output codons Dout (3) _ 2 of Vin (3)；Dout (3) _ 1 and Dout (3) _ 2 two code word are averaging, obtain corresponding to third
The code word Dout (3) of a input voltage vin (3)；
During ADC subsequent output codons, the mode of the 7th conversion is identical with first time, the 8th mode converted and the
Secondary phase is same, circuits sequentially.
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