CN106301357B - All-digital phase-locked loop - Google Patents
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- H—ELECTRICITY
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- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
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- H—ELECTRICITY
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- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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Abstract
The invention discloses an all-digital phase-locked loop, which comprises a phase discrimination module, a digital filter, a digital control oscillator and a first frequency divider; the output end of the phase discrimination module is connected with the input end of the digital filter and is used for carrying out phase comparison on the reference clock received by the first input end of the phase discrimination module and the feedback clock received by the second input end of the phase discrimination module and outputting a digital signal which is in positive correlation with the phase difference of the reference clock and the feedback clock; the output end of the digital filter is connected with the input end of the digital control oscillator and used for outputting the digital signal to the digital control oscillator after filtering so as to control the digital control oscillator to adjust the frequency of the output clock according to the preset frequency change value, and the preset frequency change value is positively correlated with the numerical value of the digital signal. The invention greatly reduces the phase locking time of the phase-locked loop under the condition of not increasing the bandwidth of the phase-locked loop and an additional branch.
Description
Technical Field
The invention relates to the technical field of digital phase-locked loops, in particular to an all-digital phase-locked loop.
Background
A phase locked loop is a system that uses a reference clock to generate a reference clock to obtain other frequencies. The phase-locked loop is based on the principle that phase differences are compared to generate control signals, when the phase differences are not changed within a certain time range, an output clock of the phase-locked loop generates a feedback clock after passing through a frequency divider, the phase of the feedback clock is changed together with a reference clock, and at the moment, the phase-locked loop system realizes the locking of frequency through the locking of the phase.
As integrated circuit processes evolve, more and more analog circuits are being replaced by digital circuits. The digital circuit has the characteristics of high integration, strong portability, high reliability and the like, and the development cycle of the digital circuit is shortened and the cost is reduced due to the series of characteristics. Conventional analog phase-locked loops are also gradually being replaced by all-digital phase-locked loops.
A conventional adpll includes a switching phase detector, a digital filter, a digitally controlled oscillator, and a feedback loop formed by an inverter. The all-digital phase-locked loop generates a control signal by comparing the phase difference of a reference clock and a feedback clock, the control signal controls a digital control oscillator after passing through a digital filter, and the frequency generated by the digital control oscillator enables a loop to become a negative feedback system after passing through a frequency divider. When the phase difference between the reference clock and the feedback clock is maintained at 0 within a certain period, it means that the two frequencies do not cause phase difference change within a certain period, and it can be determined that the two frequency values are also equivalent. When the feedback clock is equal to the reference clock, the frequency of the output clock of the phase locked loop is the frequency of the reference clock multiplied by the frequency divider.
However, the switching phase detector only provides simple information of which the phase is close to the front or the back, and because the output digit of the switching phase detector is limited, a large amount of time is needed for phase locking of the phase-locked loop. In order to reduce the phase locking time of the phase-locked loop, the bandwidth of the single-loop phase-locked loop can be reduced, but the high bandwidth can reduce the noise resistance of the phase-locked loop, increase the frequency jitter of the output clock and reduce the stability of the whole system. Thus, the conventional method is to add a frequency detection branch to reduce the locking time, but the additional branch needs to increase the complexity of the system and consume a large amount of additional power consumption.
Disclosure of Invention
In view of the above, an objective of the present invention is to provide an adpll, so as to greatly reduce the phase locking time of the adpll without increasing the pll bandwidth and extra branches.
In order to achieve the purpose, the invention adopts the following technical scheme:
the embodiment of the invention provides an all-digital phase-locked loop, which comprises a phase discrimination module, a digital filter, a digital control oscillator and a first frequency divider;
the output end of the phase discrimination module is connected with the input end of the digital filter and is used for comparing the phase of a reference clock received by the first input end of the phase discrimination module with the phase of a feedback clock received by the second input end of the phase discrimination module and outputting a digital signal which is in positive correlation with the phase difference between the reference clock and the feedback clock, wherein the feedback clock is a clock of an output clock output by the digital control oscillator after passing through the first frequency divider;
the output end of the digital filter is connected with the input end of the digital control oscillator and is used for outputting the digital signal to the digital control oscillator after filtering, so as to control the digital control oscillator to adjust the frequency of an output clock by a preset frequency change value, and adjust the phase of a feedback clock to the phase of the reference clock, wherein the preset frequency change value is positively correlated with the numerical value of the digital signal;
the output end of the digital control oscillator is connected with the input end of the first frequency divider;
the output end of the first frequency divider is connected with the second input end of the phase discrimination module.
Further, the digital signals comprise a high-order digital signal with a first preset number of bits and a low-order digital signal with a second preset number of bits;
the output end of the digital filter comprises a high-order output end and a low-order output end;
the input end of the digital control oscillator comprises a high-order input end and a low-order input end;
and the high-order output end of the digital filter is connected with the high-order input end corresponding to the digital control oscillator, and the low-order output end of the digital filter is connected with the low-order input end corresponding to the digital control oscillator.
Further, the frequency divider further comprises a second frequency divider and a triangular integral modulator;
the second frequency divider is connected between the digital control oscillator and the first frequency divider, and the output end of the second frequency divider is connected with the trigger end of the delta-sigma modulator;
the delta-sigma modulator is connected between the low-order output end of the digital filter and the low-order input end of the digital control oscillator and used for integrating and averaging the numerical value of the low-order digital signal of the second preset digit.
Further, the phase detection module comprises a multi-output switch type phase detector or a time-to-digital converter.
Further, when the phase detection module comprises a multi-output switch type phase detector, the multi-output switch type phase detector comprises a phase detector, and the phase detector is used for comparing the phases of the reference clock and the feedback clock to obtain a time indication signal and transmitting the time indication signal to the time logic selection module;
the time logic selection module is connected with the phase discriminator and used for selecting a clock with a leading rising edge from the reference clock and the feedback clock according to the time indication signal and transmitting the clock to first input ends of the plurality of time delay modules, and selecting a clock with a trailing rising edge and transmitting the clock to second input ends of the plurality of time delay modules;
a plurality of time delay modules connected in parallel to the time logic selection module, for performing different time delays on the clock input from the first input terminal;
and the digital signal output modules are correspondingly connected with the time delay modules and used for outputting corresponding digital signals according to the arrival sequence of the rising edges of the reference clock and the feedback clock.
Further, the digital signal output module comprises a D flip-flop or a decider.
The invention has the beneficial effects that: the phase demodulation module adopted by the all-digital phase-locked loop can provide digital signals with enough digits for the digital filter, when the phase difference between the reference clock and the feedback signal is large, the high-order digital signals output by the phase demodulation module are recycled, the numerical value entering the digital filter is increased, the temporary increase of the bandwidth of a loop is equivalent, the phase difference between the reference clock and the feedback signal is rapidly reduced, and the phase locking time of the phase-locked loop is reduced.
Drawings
The above and other features and advantages of the present invention will become more apparent to those of ordinary skill in the art by describing in detail exemplary embodiments thereof with reference to the attached drawings, in which:
fig. 1 is a schematic structural diagram of an adpll according to an embodiment of the present invention;
fig. 2a is a schematic diagram of a relationship between a time input and a digital output of a switching phase detector according to an embodiment of the present invention;
FIG. 2b is a schematic diagram illustrating a relationship between a time input and a digital output of the time-to-digital converter according to an embodiment of the present invention;
fig. 2c is a schematic diagram of a relationship between a time input and a digital output of the multi-output switching phase detector according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of an adpll according to a second embodiment of the present invention;
fig. 4 is a schematic structural diagram of a multi-output switching phase detector according to a second embodiment of the present invention;
fig. 5a is a circuit diagram of a decision unit in a decision device according to a second embodiment of the present invention;
fig. 5b is a circuit diagram of a latch unit in the arbiter according to the second embodiment of the present invention;
fig. 6 is an input/output waveform diagram of the decision device according to the second embodiment of the present invention.
Detailed Description
The technical scheme of the invention is further explained by the specific implementation mode in combination with the attached drawings. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Example one
Fig. 1 is a schematic structural diagram of an adpll according to an embodiment of the present invention. As shown in fig. 1, the adpll may include a phase detection module 1, a digital filter 2, a digitally controlled oscillator 3, and a first frequency divider 4.
The output end of the phase discrimination module 1 is connected with the input end of the digital filter 2, and is used for comparing the phase of the reference clock received by the first input end of the phase discrimination module 1 with the phase of the feedback clock received by the second input end of the phase discrimination module 1, and outputting a digital signal which is in positive correlation with the phase difference between the reference clock and the feedback clock, wherein the feedback clock is the clock of the output clock output by the digital control oscillator 3 after passing through the first frequency divider;
the output end of the digital filter 2 is connected with the input end of the digital control oscillator 3, and is used for outputting the digital signal to the digital control oscillator 3 after filtering, so as to control the digital control oscillator 3 to adjust the frequency of the output clock by a preset frequency change value, so that the phase of the feedback clock is adjusted to the phase of the reference clock, wherein the preset frequency change value is positively correlated with the numerical value of the digital signal;
the output end of the digital control oscillator 3 is connected with the input end of the first frequency divider 4;
the output end of the first frequency divider 4 is connected with the second input end of the phase discrimination module 1.
In a conventional phase-locked loop, a phase detection module is generally a switch-type phase detector, but the switch-type phase detector only provides simple information with a phase close to the front or the back (see fig. 2a), and since the output bit number of the switch-type phase detector is limited, a large amount of time is required for phase locking of the phase-locked loop. In this embodiment, the phase detection module 1 may include a multi-output switch type phase detector or a time-to-digital converter. After the phases of the reference clock and the feedback clock are compared by the multi-output switch type phase discriminator, outputting a digital signal which has a nonlinear positive correlation with the phase difference (see fig. 2 c); after the phases of the reference clock and the feedback clock are compared by the time-to-digital converter, a digital signal having a linear positive correlation with the phase difference is output (see fig. 2 b).
In the above scheme, because the time-to-digital converter is complex in design, a large amount of silicon chip area and a large amount of power consumption are consumed, which is not beneficial to reducing the cost of the chip; the multi-output switch type phase discriminator integrates the characteristics of the switch type phase discriminator and the time-to-digital converter, adopts the nonlinear relation of positive correlation to carry out phase identification, can effectively reduce the design difficulty, reduce the chip cost, and can provide digital signals with enough digits for the digital filter 2, therefore, the multi-output switch type phase discriminator is preferably selected by the phase discrimination module 1 of the embodiment.
For example, taking the multi-output switching type phase detector as an example, when the phase-locked loop starts to work, the frequency of the feedback clock is different from that of the reference clock, the different frequencies may cause the phase to change in each period, there is a phase difference between two different phases, and after the multi-output switching type phase detector identifies the phase difference, the phase difference is converted into a non-linear positive correlation digital signal. In the present embodiment, the high-order multiplexing technique is used to increase the number of bits of the digital signal, the processed digital signal is input to the digital filter 2 and then filtered, and then the output clock frequency of the digitally controlled oscillator 3 is directly controlled. The output clock is fed back to the second input end of the multi-output switch type phase discriminator after passing through the first frequency divider 4, thereby forming a complete negative feedback system. In this embodiment, when the phase difference between the reference clock and the feedback clock is larger, the numerical value of the digital signal output by the multi-output switching type phase detector is larger, and the frequency change (frequency change value) of the digitally controlled oscillator 3 is also larger, so that the phase of the feedback clock approaches the phase of the reference clock at a faster speed. When the phase difference is smaller and smaller, the numerical value of the digital signal output by the multi-output switch type phase discriminator is smaller, the frequency change of the digital control oscillator 3 is smaller, the phase of the feedback clock slowly approaches to the phase of the reference clock at a lower speed, when the phase difference is zero, the numerical value of the output digital information is also zero, the digital filter 2 is maintained at a stable numerical value, the phase of the phase-locked loop is locked, and the frequency of the output clock reaches the target frequency.
It should be noted that the numerical value of the digital information output by the multi-output switching phase detector and the phase difference may also be in a nonlinear negative correlation, but the subsequent digital filter 2 is usually provided, or the gain positive and negative coefficients of the numerically controlled oscillator 3 are usually provided, so that the whole loop is ensured to be a negative feedback system, and the working characteristics of the system are not affected no matter whether the numerical value of the digital information output by the multi-output switching phase detector and the phase difference are in a positive correlation or a negative correlation.
Further, the digital signal may include a high-order digital signal with a first predetermined number of bits and a low-order digital signal with a second predetermined number of bits, where the first predetermined number of bits and the second predetermined number of bits may be set by a user, for example, the first predetermined number of bits may be 6 bits, and the second predetermined number of bits may be 4 bits; the output end of the digital filter 2 comprises a high-order output end and a low-order output end; the input end of the digital control oscillator 3 comprises a high-order input end and a low-order input end; the high-order output end of the digital filter 2 is connected with the corresponding high-order input end of the digital control oscillator 3, and the low-order output end of the digital filter 2 is connected with the corresponding low-order input end of the digital control oscillator 3.
In the all-digital phase-locked loop provided by the first embodiment of the present invention, the phase demodulation module can provide digital signals with sufficient bits for the digital filter, and when the phase difference between the reference clock and the feedback signal is large, the high-bit digital signals output by the phase demodulation module are recycled, so that the value entering the digital filter is increased, which is equivalent to temporarily increasing the bandwidth of a loop, thereby quickly reducing the phase difference between the reference clock and the feedback signal, and reducing the phase locking time of the phase-locked loop.
Example two
Fig. 3 is a schematic structural diagram of an adpll according to a second embodiment of the present invention. As shown in fig. 3, unlike the first embodiment, the adpll of the present embodiment further includes a second frequency divider 5 and a delta-sigma modulator 6.
The second frequency divider 5 is connected between the numerically controlled oscillator 3 and the first frequency divider 4, and the output end of the second frequency divider 5 is connected with the trigger end of the delta-sigma modulator 6;
the delta-sigma modulator 6 is connected between the low-order output end of the digital filter 2 and the low-order input end of the digital control oscillator 3, and is used for integrating and averaging the numerical value of the low-order digital signal with the second preset number of bits so as to effectively reduce the burr phenomenon caused by the rapid change of the low-order digital signal.
In this embodiment, when the phase detection module 1 includes a multi-output switch-type phase detector, as shown in fig. 4, the multi-output switch-type phase detector includes a phase detector 11, which is configured to compare phases of a reference clock and a feedback clock to obtain a time indication signal, and transmit the time indication signal to the time logic selection module;
a time logic selection module 12 connected to the phase detector 11, configured to select, according to the time indication signal, a clock whose rising edge comes first from the reference clock and the feedback clock and transmit the clock to first input ends of the multiple time delay modules 13, and select a clock whose rising edge comes later and transmit the clock to second input ends of the multiple time delay modules 13;
a plurality of time delay modules 13 connected in parallel to the time logic selection module 12, for performing different time delays on the clock input from the first input terminal;
and a plurality of digital signal output modules 14 correspondingly connected to the plurality of time delay modules 13, configured to output corresponding digital signals according to the arrival sequence of the rising edges of the reference clock and the feedback clock.
Illustratively, when the reference clock and the feedback clock are compared and determined by the phase detector 11, the clock with the first arriving rising edge is defined as F by the time logic selection module 12EThe clock arriving after the rising edge is defined as FL. The two clock signals will be delayed by different time through the time delay modules 13, and the time difference adopted in this embodiment is 0, 20ΔT，21ΔT，22ΔT，…，212Δ T, the two clock signals are delayed and then compared by the digital signal output modules 14, when F isEAfter the delayed signals enter the digital signal output modules 14, the outputs of the digital signal output modules 14 are 1, otherwise, the outputs of the digital signal output modules 14 are 0. For example, when the time difference between two clock signals is 55.5 Δ T, after different time delay processing, the time differences are 55.5 Δ T, 54.5 Δ T, 53.5 Δ T, 51.5 Δ T, …, -4040.5 Δ T before entering the digital signal output modules 14, since the digital signal output modules 14 can determine the clock signal that the rising edge arrives first, the corresponding output signals are 11111110000000000 in sequence from low to high, the corresponding numbers are 127 after decimal conversion, and the frequency of the digital oscillation controller is controlled by the values.
Further, the digital signal output module 14 may include a D flip-flop or a determiner. To improve the accuracy of the rising edge arrival time precedence determination, the digital signal output module 14 preferably includes a determiner.
The determiner of the present embodiment may include a determining unit (shown in fig. 5 a) and a latch unit (shown in fig. 5 b) for latching the value outputted from the determining unitAnd (6) locking. Wherein the decision unit comprises two input terminals R1And R2Two output terminals A1And A2The latch unit comprises two input ends respectively connected with two output ends A of the judging unit1And A2Two output terminals C1And C2。
Illustratively, as shown in FIG. 6, R is the initial state of the arbiter1And R2At low level, the outputs N of the two NAND gates of the corresponding decision units1And N2All are high level, at this time, the following N-type and P-type field effect transistors are equivalent to two phase inverters, and the corresponding output A1And A2Are all low. When R is2After the rising edge of the NAND gate enters the discriminator, the two inputs of the NAND gate at the lower end are both high level, N2Changing from high to low. If then R1Still low, with both inputs of the upper NAND gate low, N1High, the output A of the decision device1Is at a low level, A2Is high. If then R1Also becomes high level, the two input levels of the NAND gate at the upper end are low level and high level in sequence, and the output N of the NAND gate at the upper end at the moment1Is still high, N2Still low, the output A of the decision device1Is at a low level, A2Is high. When R is2After the falling edge comes, the NAND gate input at the lower end is low level and high level, and the corresponding output N2High level, the NAND gate inputs at the upper end are all high level, and the corresponding output N1Is low, at this time A2Will be reset to low level, A1Is high. When R is1After the falling edge comes, the input of the NAND gate at the upper end is low level and high level, and the corresponding output N is1High level, low level and high level at the input of NAND gate at the lower end, and corresponding output N2High, both A1 and A2 are low. The same principle can be analyzed when R is1When entering the decider first, the waveform diagrams of the input and the output are obtained.
When R is1And R2When all are low, A1And A2Are both low. When R is1Or R2When the falling edge of (A) occurs, A1Or A2Will generate a pulse signal with a width R1And R2Time difference of falling edge. When A is1From low to high, A2When the level is changed from high level to low level, A in two inputs of upper NOR gate in latch unit1At a high level, corresponding to an output B1Is low level, at this time, both inputs of the nor gate at the lower end are low level, and the corresponding output B2Is high. The same principle can be analyzed that when A2From low to high, A1A of two inputs of the NOR gate at the lower end when the high level is changed into the low level2At a high level, corresponding to an output B2Is low level, at the moment, two inputs of the upper NOR gate are both low level, and the corresponding output B1Is high. However, in the embodiment of the present invention, the order of the rising edges needs to be determined, and the method for determining the order of the rising edges is as follows.
At R1And R2Are all in a low state waiting for a rising edge, A1And A2Is low, at this time B1And B2Will always latch the last state. When A is2Changing from low level to high level, one high level in two inputs of NOR gate at lower end, and corresponding output B2Is low level, at the moment, two inputs of the upper NOR gate are both low level, and the corresponding output B1Is high. When A is1Changing from low level to high level, one high level in two inputs of upper NOR gate, and corresponding output B1Is low level, at this time, both inputs of the nor gate at the lower end are low level, and the corresponding output B2Is high.
In summary, corresponding to pair A in FIG. 61And A2Can correspondingly judge B1And B2High and low level of (B)1And B2Is then inverted to obtain C as shown in FIG. 61And C2A waveform diagram of (a).
The all-digital phase-locked loop provided by the embodiment integrates and averages the numerical value of the low-bit digital signal of the second preset bit output by the digital filter through the delta-sigma modulator, thereby effectively reducing the burr phenomenon caused by the rapid change of the low-bit digital signal.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (3)
1. An all-digital phase-locked loop is characterized by comprising a phase discrimination module, a digital filter, a digital control oscillator and a first frequency divider;
the output end of the phase discrimination module is connected with the input end of the digital filter and is used for comparing the phase of a reference clock received by the first input end of the phase discrimination module with the phase of a feedback clock received by the second input end of the phase discrimination module and outputting a digital signal which is in positive correlation with the phase difference between the reference clock and the feedback clock, wherein the feedback clock is a clock of an output clock output by the digital control oscillator after passing through the first frequency divider;
the output end of the digital filter is connected with the input end of the digital control oscillator and is used for outputting the digital signal to the digital control oscillator after filtering, so as to control the digital control oscillator to adjust the frequency of an output clock by a preset frequency change value, and adjust the phase of a feedback clock to the phase of the reference clock, wherein the preset frequency change value is positively correlated with the numerical value of the digital signal;
the output end of the digital control oscillator is connected with the input end of the first frequency divider;
the output end of the first frequency divider is connected with the second input end of the phase discrimination module;
the digital signals comprise a high-order digital signal with a first preset digit and a low-order digital signal with a second preset digit;
the output end of the digital filter comprises a high-order output end and a low-order output end;
the input end of the digital control oscillator comprises a high-order input end and a low-order input end;
the high-order output end of the digital filter is connected with the high-order input end corresponding to the digital control oscillator, and the low-order output end of the digital filter is connected with the low-order input end corresponding to the digital control oscillator;
when the phase discrimination module comprises a multi-output switch type phase discriminator, the multi-output switch type phase discriminator comprises a phase discriminator which is used for comparing the phases of the reference clock and the feedback clock to obtain a time indication signal and transmitting the time indication signal to a time logic selection module;
the time logic selection module is connected with the phase discriminator and used for selecting a clock with a leading rising edge from the reference clock and the feedback clock according to the time indication signal and transmitting the clock to first input ends of the plurality of time delay modules, and selecting a clock with a trailing rising edge and transmitting the clock to second input ends of the plurality of time delay modules;
a plurality of time delay modules connected in parallel to the time logic selection module, for performing different time delays on the clock input from the first input terminal;
and the digital signal output modules are correspondingly connected with the time delay modules and used for outputting corresponding digital signals according to the arrival sequence of the rising edges of the reference clock and the feedback clock.
2. The adpll of claim 1, further comprising a second frequency divider and a delta-sigma modulator;
the second frequency divider is connected between the digital control oscillator and the first frequency divider, and the output end of the second frequency divider is connected with the trigger end of the delta-sigma modulator;
the delta-sigma modulator is connected between the low-order output end of the digital filter and the low-order input end of the digital control oscillator and used for integrating and averaging the numerical value of the low-order digital signal of the second preset digit.
3. The all-digital phase-locked loop of claim 1, wherein the digital signal output module comprises a D flip-flop or a decider.
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| CN108923769B (en) * | 2018-08-08 | 2024-03-19 | 宗仁科技(平潭)股份有限公司 | Digital filter circuit and filtering method thereof |
| CN109379076A (en) * | 2018-10-24 | 2019-02-22 | 佛山市秀声电子科技有限公司 | A kind of low-frequency phase-locking ring that modulus combines |
| CN110061737B (en) * | 2019-04-26 | 2023-05-16 | 海光信息技术股份有限公司 | Phase lock detection output circuit and all-digital phase-locked loop system |
| CN113054998B (en) * | 2019-12-26 | 2023-04-18 | 澜至电子科技（成都）有限公司 | Linear calibration system and method of time-to-digital converter and digital phase-locked loop |
| CN111641410B (en) * | 2020-06-22 | 2023-11-17 | 上海兆芯集成电路股份有限公司 | Digital phase-locked loop |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101420226A (en) * | 2008-12-16 | 2009-04-29 | 凌阳科技股份有限公司 | Full digital phase locking loop |
| CN103684436A (en) * | 2012-09-10 | 2014-03-26 | 国际商业机器公司 | Phase locked loop circuit and method of generating clock signals using the phase locked loop |
| CN104901686A (en) * | 2015-06-09 | 2015-09-09 | 中山大学 | Phase-locked loop with low phase noise |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7482885B2 (en) * | 2005-12-29 | 2009-01-27 | Orca Systems, Inc. | Method of frequency synthesis for fast switching |
-
2016
- 2016-07-25 CN CN201610593908.7A patent/CN106301357B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101420226A (en) * | 2008-12-16 | 2009-04-29 | 凌阳科技股份有限公司 | Full digital phase locking loop |
| CN103684436A (en) * | 2012-09-10 | 2014-03-26 | 国际商业机器公司 | Phase locked loop circuit and method of generating clock signals using the phase locked loop |
| CN104901686A (en) * | 2015-06-09 | 2015-09-09 | 中山大学 | Phase-locked loop with low phase noise |
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