CN215186700U

CN215186700U - Clock signal selection circuit, delay chain circuit and delay phase-locked loop

Info

Publication number: CN215186700U
Application number: CN202121239714.XU
Authority: CN
Inventors: 狄鑫娟; 肖文勇
Original assignee: Hangzhou Xiongmai Integrated Circuit Technology Co Ltd
Current assignee: Zhejiang Xinmai Microelectronics Co ltd
Priority date: 2021-06-03
Filing date: 2021-06-03
Publication date: 2021-12-14
Anticipated expiration: 2031-06-03

Abstract

The utility model discloses a clock signal selection circuit, including the delay chain circuit and the delay phase-locked loop of this clock selection signal, above-mentioned clock signal selection circuit includes negative edge D flip-flop, first low level latch and selecting unit, and the selecting unit is used for receiving first clock signal and second clock signal, and the second clock signal is the delay signal of first clock signal; the signal input end of the negative edge D trigger is connected with an external control circuit, the clock control end is used for receiving an externally input trigger signal, and the signal output end is connected with the signal input end of the first low-level latch; the clock control end of the first low-level latch is used for receiving a second clock signal, and the signal output end is connected with the selection unit so as to control the selection unit to output the first clock signal or the second clock signal. The control signal is processed by the negative edge D trigger and the first low-level latch to control the selection unit to work, and the selection unit is prevented from outputting the second clock signal when the second clock signal is high level, so that the generation of burrs is avoided.

Description

Clock signal selection circuit, delay chain circuit and delay phase-locked loop

Technical Field

The utility model relates to a phase-locked loop field especially relates to a DLL time delay phase-locked loop.

Background

In the design of USB2.0 data recovery, a DLL (delay locked loop) is adopted to generate five or eight clocks for oversampling data. Taking five-item clock DLL delay phase-locked loop as an example, the principle is as follows:

the delay of each clock is controlled by a five-stage delay chain circuit, the phase relation between the last stage clock (the clock signal output by the tail delay chain circuit) and the input clock (the initial clock signal) is locked by a phase detection circuit, and the output signal of the phase detection circuit is input into a control circuit to control the delay parameter of each clock.

However, in the prior art, the clock signal output by each delay chain circuit has glitches, which causes errors in data recovery.

SUMMERY OF THE UTILITY MODEL

The utility model discloses there is the burr shortcoming to the clock signal that delay chain circuit among the prior art exported, provides a clock signal selection circuit (hereinafter be referred to as selection circuit for short), still provides an adopt this selection circuit's delay chain circuit and time delay phase-locked loop.

In order to solve the technical problem, the utility model discloses a following technical scheme can solve:

a clock signal selection circuit comprises a negative edge D trigger, a first low-level latch and a selection unit, wherein the selection unit is used for receiving a first clock signal and a second clock signal, and the second clock signal is a delay signal of the first clock signal;

the signal input end of the negative edge D trigger is connected with an external control circuit, the clock control end is used for receiving an externally input trigger signal, and the signal output end is connected with the signal input end of the first low-level latch;

and the clock control end of the first low-level latch is used for receiving the second clock signal, and the signal output end of the first low-level latch is connected with the selection unit so as to control the selection unit to output the first clock signal or the second clock signal.

As an implementable manner, the selection unit includes:

the logic circuit comprises an inverter, a second low-level latch and a logic branch circuit;

the signal output end of the first low-level latch is connected with the input end of the logic branch circuit;

the input end of the phase inverter is connected with the signal output end of the negative edge D trigger, and the output end of the phase inverter is connected with the signal input end of the second low-level latch;

the clock control end of the second low-level latch is used for receiving the first clock signal, and the signal output end of the second low-level latch is connected with the input end of the logic branch circuit;

the input end of the logic branch is also used for receiving a first clock signal and a second clock signal, and the output end of the logic branch is used for outputting the first clock signal or the second clock signal.

As an implementable embodiment, the logical leg comprises:

a first and gate, a first input end of which is connected to the signal output end of the first low-level latch, and a second input end of which is used for receiving the second clock signal;

a first input end of the second AND gate is connected with a signal output end of the second low-level latch, and a second input end of the second AND gate is used for receiving the first clock signal;

and the first input end of the OR gate is connected with the output end of the first AND gate, the second input end of the OR gate is connected with the output end of the second AND gate, and the output end of the OR gate is used for outputting a first clock signal or a second clock signal.

The utility model also provides a delay chain circuit, which comprises a plurality of selection circuits connected in series and delay chains corresponding to the selection circuits one by one;

the selection circuit is the clock signal selection circuit of any one of the above items;

the input end and the output end of the delay chain are both connected with the corresponding selection circuit, the input end of the delay chain is used for receiving a first clock signal, and the output end of the delay chain is used for outputting a second clock signal.

As an implementable embodiment:

the number of the delay chains is n;

the delay chain corresponding to the kth selection circuit comprises 2^n-kAnd k is less than or equal to n and is a positive integer.

As an implementable embodiment:

taking the delay chain corresponding to the 1 st selection circuit as a first delay chain; the input of the first delay chain is the input clock signal of the corresponding delay chain circuit, and the output is the input clock signal passing through 2^n-1The delay signal is output after the delay unit.

The output end of the first delay chain is respectively connected with the clock control end of the negative edge D trigger in each selection circuit, namely, the delay signal output by the first delay chain is used as the trigger signal of each negative edge D trigger.

As an implementable embodiment:

the number of delay chains is 6.

The utility model relates to a time delay phase-locked loop, which comprises a control circuit, a delay circuit and a phase demodulation circuit, wherein the control circuit is respectively connected with the delay circuit and the phase demodulation circuit;

the delay circuit comprises a plurality of delay chain circuits which are sequentially connected in series;

the delay chain circuit is any one of the delay chain circuits.

As an implementable embodiment:

the delay chain circuit comprises a head delay chain circuit, a tail delay chain circuit and a plurality of middle delay chain circuits;

the input of the first delay chain circuit is the input of the delay circuit, namely the input of the initial clock signal, and the output of the tail delay chain circuit is the output of the delay circuit.

The tail delay chain circuit and any one of the middle delay chain circuits are connected with the phase discrimination circuit.

As one possible implementation, the phase detection circuit includes:

a first signal input for receiving an initial clock signal;

the second signal input end is connected with the output end of the tail delay chain circuit;

a third signal input end connected with the output end of a middle delay chain circuit;

the first phase detection unit is respectively connected with the first signal input end, the second signal input end and the control circuit and is used for outputting a locking signal to the control circuit;

the second phase discrimination unit is respectively connected with the first signal input end, the second signal input end and the control circuit and is used for outputting corresponding first feedback signals to the control circuit;

and the third phase discrimination unit is respectively connected with the first signal input end, the third signal input end and the control circuit and is used for outputting corresponding second feedback signals to the control circuit.

The utility model discloses owing to adopted above technical scheme, have apparent technological effect:

in the utility model, through the design of the negative edge D trigger and the first low level latch, the control signal input by the control circuit is processed, and then the selection signal with a fixed phase relation with the corresponding second clock signal is output, namely, the edge change of the selection signal must occur in the period that the second clock signal is at low level; and enabling the selection unit to perform clock switching based on the selection signal so as to avoid outputting the second clock signal when the second clock signal is at a high level in the selection unit, thereby avoiding the generation of burrs and effectively reducing the problem of duty ratio distortion.

The utility model designs the number of the delay units in each delay chain, so that the minimum adjusting unit is one delay unit, which is convenient for adjustment;

the utility model discloses to the design of phase discrimination circuit, make its phase relation that not only can appraise the clock signal that initial clock signal and tail delay chain circuit exported, judge whether the phase-locked loop of place locks, can also judge whether to be harmonic locking (it is error condition) through appraising the phase relation between the clock signal that initial clock signal and the middle delay chain circuit of prescribing in advance exported, ensure that the lock state that the phase-locked loop reaches is normal lock state.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic diagram of a module connection of a clock signal selection circuit according to the present invention;

FIG. 2 is a schematic block diagram of the selection unit 130 of FIG. 1;

fig. 3 is a schematic diagram of module connection of a delay chain circuit 1 according to the present invention;

fig. 4 is a schematic circuit connection diagram of a delay chain circuit 1 according to the present invention;

FIG. 5 is a schematic diagram of prior art output signal glitching;

FIG. 6 is a schematic diagram of the anti-glitch circuit 1 of FIG. 4;

fig. 7 is a schematic circuit diagram of a delay locked loop according to the present invention;

fig. 8 is a circuit schematic diagram of the phase detection circuit 3 of fig. 7;

FIG. 9 is a state transition diagram of the control circuit 2 of FIG. 7;

fig. 10 is a schematic diagram of the operation of the control circuit 2 in fig. 7.

Detailed Description

The present invention will be described in further detail with reference to the following examples, which are illustrative of the present invention and are not intended to limit the present invention.

Embodiment 1, a clock signal selection circuit, as shown in fig. 1, includes a negative edge D flip-flop 110, a first low-level latch 120, and a selection unit 130, where the selection unit 130 is configured to receive a first clock signal and a second clock signal, and the second clock signal is a delayed signal of the first clock signal;

the negative edge D flip-flop 110 (also called a falling edge D flip-flop) has a signal input end connected to the external control circuit 2 and receives a control signal sent by the external control circuit 2, a clock control end for receiving an externally input trigger signal, and a signal output end connected to the signal input end of the first low-level latch 120;

referring to fig. 4, DFFNRQ in fig. 4 represents the negative edge D flip-flop 110, the D terminal is the signal input terminal of the negative edge D flip-flop 110, the clk terminal is the clock control terminal of the negative edge D flip-flop 110, and the Q terminal is the signal output terminal of the negative edge D flip-flop 110.

The clock control terminal of the first low-level latch 120 is configured to receive the second clock signal, and the signal output terminal is connected to the selection unit 130 to control the selection unit 130 to output the first clock signal or the second clock signal.

Referring to fig. 4, LANRQ in fig. 4 represents a low level latch, a terminal D is a signal input terminal of the low level latch, a terminal clk is a clock control terminal of the low level latch, a terminal Q is a signal output terminal of the low level latch, and in fig. 4, a low level latch signal-connected to a signal output terminal of the negative edge D flip-flop 110 is a first low level latch 120.

Note that in the art, high and low levels have specific meanings, and in a digital logic circuit, low level indicates 0 and high level indicates 1.

In the prior art, a clock selection circuit is often composed of a flip-flop and a switch, two different clock signals (an initial clock signal and a delay signal, or two delay signals with different delays) are input to the switch, the flip-flop samples a control signal when detecting a rising edge of the initial clock signal, and controls the switch according to a sampling result, so that the switch outputs one of the clock signals, and when the switch switches the clock signal, the output signal is often glitched.

In this embodiment, the negative edge D flip-flop 110 samples the control signal when detecting the falling edge of the trigger signal, and outputs a pulse signal when the sampling result is a high level (i.e., "1"), and takes the pulse signal as a processing signal; the first low-level latch 120 processes the pulse signal according to the phase of the second clock signal, and outputs a selection signal; the edge change of the selection signal must occur during the period when the second clock signal is at a low level, so as to avoid the selection unit 130 outputting the clock signal when the second clock signal is at a high level, thereby avoiding the generation of glitch and reducing the problem of duty ratio distortion.

The selection unit 130 may adopt a switch to output the first clock signal or the second clock signal based on the selection signal output by the first low-level latch 120, for example, when the level of the selection signal is switched, the switch is activated to switch the output clock signal.

The selecting unit 130 may also be implemented by using a logic circuit, and referring to fig. 2, in this embodiment, the selecting unit 130 includes:

an inverter 131, a second low-level latch 132 and a logic branch 133;

the signal output terminal of the first low level latch 120 is connected to the input terminal of the logic branch 133;

the input end of the inverter 131 is connected to the signal output end of the negative edge D flip-flop 110, and the output end is connected to the signal input end of the second low-level latch 132;

the clock control terminal of the second low-level latch 132 is configured to receive the first clock signal, and the signal output terminal is connected to the input terminal of the logic branch 133;

the low level latch connected to the signal at the output of the inverter 131 in fig. 4 is a second low level latch 132.

The input terminal of the logic branch 133 is further configured to receive a first clock signal and a second clock signal, and the output terminal thereof is configured to output the first clock signal or the second clock signal.

The logical branch 133 comprises:

a first and gate having a first input terminal connected to the signal output terminal of the first low level latch 120 and a second input terminal for receiving the second clock signal;

a second and gate having a first input connected to the signal output of the second low-level latch 132 and a second input for receiving the first clock signal;

Embodiment 2, a delay chain circuit 1, as shown in fig. 3, includes a plurality of selection circuits 10 connected in series, and further includes delay chains 11 corresponding to the selection circuits 10 one to one;

the selection circuit 10 is the clock signal selection circuit according to any one of embodiments 1;

the input end and the output end of the delay chain 11 are connected to the corresponding selection circuit 10, the input end is used for receiving a first clock signal, and the output end is used for outputting a second clock signal.

Each selection circuit 10 selects whether the corresponding delay chain 11 is connected to the delay chain circuit 1 or not according to an externally input control signal so as to control the delay value of the delay chain circuit 1;

further:

the number of the delay chains 11 is n;

the delay chain 11 corresponding to the kth selection circuit 10 comprises 2^n-kAnd k is less than or equal to n and is a positive integer.

Those skilled in the art can select the delay units disclosed in the prior art to form the delay chain 11 according to actual needs, and in this embodiment, the delay chain is designed according to a 22nm process, where n is 6, and at this time, the delay chain circuit 1 has 6 delay chains 11, and the number of the delay units in each delay chain 11 is a power of 2, and is 63 delay units in total, and this design can achieve that the minimum adjustment unit of the delay units is 1, that is, the delay value of the delay chain circuit 1 can be adjusted based on the delay value of a single delay unit.

Further:

a delay chain 11 corresponding to the 1 st selection circuit 10 is used as a first delay chain 11;

the output end of the first delay chain 11 is connected to the clock control end of the negative edge D flip-flop 110 in each selection circuit 10.

As can be seen from the above, the clock control terminal of the negative edge D flip-flop 110 is used for receiving a trigger signal, in the prior art, the trigger signal usually adopts the input clock signal of the delay chain circuit 1, and in the actual use process, a person skilled in the art can automatically designate a clock signal as the trigger signal according to actual needs;

in this embodiment, by designing the delay chains 11, the delay values of the delay chains 11 in the delay chain circuit 1 are arranged in a descending order, the input of the first delay chain 11 is the input clock signal of the delay chain circuit 1, and the delay unit is the largest, so that the phase of the delay signal passing through the delay chain circuit 1 is the latest, and the delay signal is used as the trigger signal to further reduce the generation of the glitch.

The working principle of the delay chain circuit 1 provided in fig. 4 for glitch resistance and duty cycle distortion reduction will be described in detail below;

the delay chain circuit 1 comprises 6 delay chain modules and 11 delay chain modules, wherein each delay chain 11 module comprises a delay chain 11 and a selection circuit 10 which are connected;

in fig. 4, the first clock signal corresponding to the first delay chain 11 block is an input clock signal i _ clkin, and the second clock signal is clkout31, that is, the input clock signal i _ clkin is a delay signal obtained by a delay chain 11 having 32 delay cells, and the clock signal output by the first delay chain 11 block is mx clkout 31;

in fig. 4, the first clock signal corresponding to the second delay chain 11 block is mx clkout31, and the second clock signal is clkout47, that is, the input clock signal mx clkout31 is the delay signal output by the delay chain 11 with 16 delay cells, and the clock signal output by the second delay chain 11 block is mx clkout 47;

in the prior art, with the input clock signal i _ clkin of the delay chain circuit 1 as a trigger signal, when a rising edge of the input clock signal i _ clkin is detected, the control signal i _ delay _ ctrl [ 0: 5, sampling, and switching signals according to sampling results;

as shown in fig. 5, the first delay chain 11 block outputs mx _ clkout31 after performing signal selection based on the control signal i _ delay _ ctrl [5], and in the next delay stage, a glitch occurs in the output mx clkout47 after performing signal selection based on the control signal i _ delay _ ctrl [4] in the second delay chain 11 block.

In this embodiment, clkout31 is used as a trigger signal, and the negative edge D flip-flop 110(DFFNRQ) is used to compare the output voltage of the control signal i _ delay _ ctrl [ 0: sampling, outputting a processing signal ndff _ sel _ f _ d according to a sampling result, inputting the processing signal ndff _ sel _ f _ d and a corresponding second clock signal into a low-level latch LANRQ, and taking a signal output by the low-level latch LANRQ as a final selection signal;

as can be seen from fig. 6, in this embodiment, the control signal i _ delay _ ctrl [ 0: 5] sampling is carried out;

the control signal corresponding to the first delay chain 11 block is i _ delay _ ctrl [5], the processing signal is ndff _ sel5_ f _ d, the selection signal is clk2_ sel5_ f _ d, the processing signal and the selection signal have the same waveform, the first clock signal is i _ clkin, the second clock signal is clkout31, and the finally output clock signal is mx _ clkout31, as shown in fig. 6, the clock signal switching is performed when the levels of clk2_ sel5_ f _ d are changed, the second period T2 of mx _ clkout31 is lengthened, and the second period T3 is shortened;

the control signal corresponding to the second delay chain 11 is i _ delay _ ctrl [4], the processing signal is ndff _ sel4_ f _ d, the selection signal is clk2_ sel4_ f _ d, the first clock signal is mx _ clkout31, the second clock signal is clkout47, and the finally output clock signal is mx _ clkout47, as shown in fig. 6, switching of the clock signals is performed when the level of ndff _ sel4_ f _ d changes, which cannot compensate for the second period T3 and still easily causes glitch, and clock selection is performed based on clk2_ sel4_ f _ d, since the edge change of 2_ sel4_ f _ d occurs during the period when the level of clkout47 is low, the glitch generation can be avoided, and the problem of distortion of the duty cycle T3 can be reduced.

After the remaining 4 delay chain 11 modules sequentially perform delay and clock selection, the 3 rd period T3 will continue to be lengthened, so as to ensure that the problem that the T3 period is shortened to nothing does not occur.

Embodiment 3 discloses a delay locked loop, which includes a control circuit 2, a delay circuit, and a phase detection circuit 3 as shown in fig. 7, where the control circuit 2 is connected to the delay circuit and the phase detection circuit 3, respectively, and the delay circuit is connected to the phase detection circuit 3;

the control circuit 2 may be, for example, a control circuit 2 provided in an existing delay locked loop, which will not be described in detail in this embodiment.

The delay circuit comprises a plurality of delay chain circuits 1 which are sequentially connected in series;

the delay chain circuit 1 is the delay chain circuit 1 according to any one of embodiments 2.

The selection of the number of the delay chain circuits 1 is related to the required clock output, the delay value required by a single delay chain circuit 1 and the number of the selection circuits 10 in the delay chain circuit 1, when m delay chain circuits 1 are serially cascaded, m clock outputs are provided, and each delay chain circuit 1 realizes the delay of T/m; the larger the delay value required in each delay chain circuit 1 is, the more the selection circuits 10 are required, and the smaller the delay value is, the fewer the selection circuits 10 are required, so that a person skilled in the art can set the number of the delay chain circuits 1 and the number of the selection circuits 10 in each delay chain circuit 1 by himself or herself according to actual needs, which is not limited in this embodiment.

The number of delay chain circuits 1 in this embodiment is 5.

Further:

when the number of the delay chain circuits 1 is more than or equal to 3, the delay chain circuit 1 comprises a head delay chain circuit 1, a tail delay chain circuit 1 and a plurality of middle delay chain circuits 1;

the tail delay chain circuit 1 and any one of the middle delay chain circuits 1 are connected with the phase discrimination circuit 3.

In the prior art, the phase discrimination circuit 3 only compares the phases according to the initial clock signal and the clock signal output by the tail delay chain circuit 1, sends the comparison result to the control circuit 2, and controls the delay value of each delay chain circuit 1 according to the comparison result by the control circuit 2 until locking;

in this embodiment, a clock signal output by a certain intermediate delay chain circuit 1 is additionally sent to the phase demodulation circuit 3, so that the phase demodulation circuit 3 can perform phase comparison between the clock signal output by the intermediate delay chain circuit 1 and the clock signal output by the tail delay chain circuit 1, so that the control circuit 2 can identify whether harmonic locking occurs, and continuously adjust the delay values of the delay chain circuits 1 during the harmonic locking, thereby achieving real locking.

Further, the phase detection circuit 3 includes:

a first signal input for receiving an initial clock signal;

the second signal input end is connected with the output end of the tail delay chain circuit 1;

a third signal input end connected with the output end of an intermediate delay chain circuit 1;

a first phase-identifying unit 31, which is respectively connected to the first signal input terminal, the second signal input terminal and the control circuit 2, and is configured to output a locking signal to the control circuit 2;

the second phase discrimination unit 32 is respectively connected to the first signal input terminal, the second signal input terminal and the control circuit 2, and is configured to output a corresponding first feedback signal to the control circuit 2;

the third phase discrimination unit 33 is connected to the first signal input terminal, the third signal input terminal and the control circuit 2, and configured to output a corresponding second feedback signal to the control circuit 2;

the control circuit 2 is configured to receive the locking signal, the first feedback signal, and the second feedback signal, and further configured to output a corresponding control signal to each delay chain circuit 1.

Aiming at the problems that the existing delay-locked loop cannot identify harmonic locking and the conditions that the clock jitter is unlocked or the locking and unlocking are repeated are difficult to achieve locking, the phase demodulation circuit 3 is designed in the embodiment;

a circuit schematic diagram of the phase detection circuit 3 in this embodiment is shown in fig. 8, and includes a first phase detection unit 31, a second phase detection unit 32, and a second phase detection unit 32, where the first phase detection unit 31 is an existing phase detector and is configured to perform locking judgment based on an initial clock signal and a clock signal output by the tail delay chain circuit 1;

the second phase detection unit 32 and the third phase detection unit 33 both use positive edge D flip-flops, the clock control terminals of the second phase detection unit 32 and the third phase detection unit 33 both receive an initial clock signal, the signal input terminal of the second phase detection unit 32 receives a clock signal output by the tail delay chain circuit 1, and the signal input terminal of the third phase detection unit 33 receives a clock signal output by a pre-designated middle delay chain circuit 1 (in this embodiment, the third delay chain circuit 1 is designated);

the second phase detection unit 32 is configured to identify a situation that locking cannot be performed due to clock jitter, and if the output of the first phase detection unit 31 is kept at 0 and the output of the second phase detection unit 32 is alternately set to 0 and 1, it indicates that the DLL is already close to a locked state, so that the DLL can be directly determined to be in the locked state, that is, the state machine of the control circuit 2 reaches the locked state.

The third phase discrimination unit 33 is configured to identify whether a harmonic occurs, when the result output by the first phase discrimination unit 31 is locking, the control circuit 2 determines whether harmonic locking occurs according to the output of the third phase discrimination unit 33, reconfigures an adjustment starting point according to a preset rule after the harmonic locking occurs, and locks the delay value of each delay chain circuit 1 again until the phase-locked loop where the delay chain circuit is located is locked stably.

Referring to fig. 9, the control circuit 2 enters an initial state CNT _ IDLE after being activated, enters an adjustment state CNT _ UPDATE after being reset and released, and starts automatic adjustment based on a phase discrimination result; if the delay chain circuit is LOCKED, entering a LOCKED state LOCKED, otherwise, continuously and automatically adjusting the delay of each delay chain circuit 1; after entering a locking state LOCKED, if the locking is continuously and stably performed, the locking state is always in the locking state, and once the locking is lost, the locking state WAIT _ LOCKED is entered into a waiting locking state;

when the control circuit 2 WAITs for the lock state, if the lock state is unlocked again after a few short periods due to clock jitter, the control circuit enters the lock state LOCKED again, as shown by a signal i _ LOCKED _ stable _ reg in fig. 7, a person skilled in the art can set how many clock periods to WAIT according to actual conditions, and when the control circuit enters the lock state WAIT for the lock state WAIT _ LOCKED, the control circuit WAITs for a preset number of clock periods and then judges whether the lock state is unlocked, if the lock state is still in the lock state, the control circuit enters the adjustment state CNT _ UPDATE to continue adjusting, otherwise, the control circuit resumes the lock state LOCKED.

When the jitter is always present, the value of o _ clk _ locked output by the first phase detection unit 31 is always 0, and the value of o _ clk _ fs output by the second phase detection unit 32 is 0 and 1 alternately, which indicates that the DLL is actually in the locked edge, so that the control circuit 2 automatically asserts its lock according to the outputs of o _ clk _ locked and o _ clk _ fs in this embodiment, and stops the adjustment.

If o _ clk _ locked is 0, indicating that the phase relationship between i _ clkin5 and i _ clkin0 is out of the range of 6 delay units, considering unlocking, and continuing to adjust according to the phase relationship, once adjusting, i.e. increasing or decreasing the delay value of 5 delay units (because of the 5-stage delay chain circuit 1), theoretically locking by once adjusting, but if the clock is jittered at this time, the phase difference between i _ clkin0 and i _ clkin5 is increased (greater than the delay value of 6 delay units), the first phase identifying unit 31 still considers unlocking, but actually reaches the locked state at this time; because the first phase identifying unit 31 considers that the DLL is unlocked and continues to adjust, but if the clock in the next cycle is normal, the phase relationship between the two will be enlarged again (for example, the delay is increased), and if the clock in the next cycle is normal, the delay needs to be decreased in the next cycle, so that the value of o _ clk _ fs is 0 and 1 alternately, and o _ clk _ locked is always 0, which reflects the situation that the current DLL is repeatedly increased, decreased delay and unable to lock, for this situation, the control circuit 2 automatically determines that the DLL is locked and stops adjusting.

Referring to fig. 10, the following describes the operation flow of the delay locked loop provided in this embodiment in detail:

STEP 1: after the power is on, starting the automatic DLL adjusting function, and entering STEP2 after the starting;

the start-up method configures i _ dll _ int _ start _ en to a high level.

Controlling each delay chain circuit 1 to sequentially increase or decrease the accessed delay units one by one;

that is, if it needs to be increased, the five-stage delay chain circuits 1 are sequentially increased by 1, that is, each time a clock cycle passes, a certain delay chain circuit 1 is increased by 1; if the delay needs to be reduced, the five-stage delay chain circuit 1 is sequentially reduced by 1 through five clock cycles, so that only one delay chain circuit 1 is used for adjusting delay in one clock cycle, and clock glitch is avoided.

STEP 2: judging whether to lock;

whether the lock is performed is determined according to the o _ clk _ locked output by the first phase detection unit 31, the o _ clk _ fs output by the second phase detection unit 32, and the o _ clk2_ fs output by the third phase detection unit 33;

in this case, o _ clk _ locked is 1, which means locking, and goes to STEP5, otherwise, goes to STEP 3.

STEP 3: judging whether the lock is lost;

namely, judging whether the DLL is unlocked after being locked;

when o _ clk _ locked output by the first phase identifying unit 31 is 0, the state of the control circuit 2 is in the locked state, it is determined that the lock is lost, and the state of the control circuit 2 is changed to the lock waiting state, and then STEP4 is entered;

when the o _ clk _ locked output by the first phase identifying unit 31 is equal to 0, and the state of the control circuit 2 is in the adjustment state, it indicates that the DLL is not locked all the time, at this time, it is determined whether the DLL cannot be locked due to clock jitter according to the o _ clk _ fs, if the o _ clk _ fs is alternately 0 and 1, it is determined that the DLL is locked, the state of the control circuit 2 is changed to the locked state, and the control circuit enters the STEP8, otherwise, the control circuit continues to enter the STEP2 after the delay unit is increased/decreased.

STEP 4: waiting based on a pre-configured waiting period;

presetting a waiting period i _ locked _ stable _ reg equal to aT (n is 0-255), wherein T is a period, the period represents that whether the lock is lost is judged after waiting a clock periods after the lock is lost, whether the delay value of the delay chain circuit 1 is adjusted to realize locking is judged according to the judgment result, namely, the STEP2 is carried out after waiting a clock periods.

STEP 5: judging whether the harmonic locking is performed;

if o _ clk _ locked is 1, the STEP is entered after the lock is determined, if o _ clk2_ fs is 1, the STEP is entered for harmonic lock, and the STEP6 is entered, otherwise, the STEP8 is entered.

STEP 6: reconfiguring the automatic adjustment starting point;

in the harmonic locking state, it is necessary to configure a starting point of the automatic adjustment, reduce the number of delay units connected in each delay chain circuit 1, and the reconfigured value is 1/2 of the initial value, that is, the value of i _ delay _ ctrl _ reg, and at the same time, i _ delay _ ctrl _ up _ en is configured to be 1, and the value of i _ delay _ ctrl _ reg can be updated to the inside of the control circuit 2, and then the STEP7 is entered.

STEP 7: starting the automatic regulation again;

i _ delay _ ctrl _ up _ en is turned off (i _ delay _ ctrl _ up _ en ═ 0), and STEP2 is entered to continue to determine the wait for lock.

STEP 8: the DLL is in a stable locked state.

The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.

It should be noted that:

reference in the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrase "one embodiment" or "an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment.

While the preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the appended claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the invention.

In addition, it should be noted that the specific embodiments described in the present specification may differ in the shape of the components, the names of the components, and the like. All equivalent or simple changes made according to the structure, characteristics and principle of the utility model are included in the protection scope of the utility model. Various modifications, additions and substitutions may be made by those skilled in the art without departing from the scope of the invention as defined in the accompanying claims.

Claims

1. The clock signal selection circuit is characterized by comprising a negative edge D flip-flop, a first low-level latch and a selection unit, wherein the selection unit is used for receiving a first clock signal and a second clock signal, and the second clock signal is a delay signal of the first clock signal;

2. The clock signal selection circuit of claim 1, wherein the selection unit comprises:

3. The clock signal selection circuit of claim 2, wherein the logic branch comprises:

4. The delay chain circuit is characterized by comprising a plurality of selection circuits connected in series and delay chains in one-to-one correspondence with the selection circuits;

the selection circuit is the clock signal selection circuit of any one of claims 1 to 3;

5. The delay chain circuit of claim 4, wherein:

the number of the delay chains is n;

6. The delay chain circuit of claim 5, wherein:

taking the delay chain corresponding to the 1 st selection circuit as a first delay chain;

and the output end of the first delay chain is respectively connected with the clock control end of the negative edge D trigger in each selection circuit.

7. The delay chain circuit of claim 5 or 6, wherein:

the number of delay chains is 6.

8. A time delay phase-locked loop comprises a control circuit, a time delay circuit and a phase discrimination circuit, wherein the control circuit is respectively connected with the time delay circuit and the phase discrimination circuit;

the method is characterized in that:

the delay chain circuit is as claimed in any one of claims 4 to 7.

9. The delay locked loop of claim 8, wherein:

10. The delay locked loop of claim 9, wherein the phase detection circuit comprises:

a first signal input for receiving an initial clock signal;