CN106301343B - A kind of customized multi-protocols digital audio and video signals generating system of level and method - Google Patents
A kind of customized multi-protocols digital audio and video signals generating system of level and method Download PDFInfo
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- CN106301343B CN106301343B CN201610696718.8A CN201610696718A CN106301343B CN 106301343 B CN106301343 B CN 106301343B CN 201610696718 A CN201610696718 A CN 201610696718A CN 106301343 B CN106301343 B CN 106301343B
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- 238000006243 chemical reaction Methods 0.000 claims description 3
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- 238000004458 analytical method Methods 0.000 abstract description 3
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
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Abstract
The invention discloses a kind of customized multi-protocols digital audio and video signals generating systems of level, including host computer, FPGA, digital analog converter, the host computer to connect with FPGA, and the FPGA is connect with digital analog converter；FPGA includes state code memory, waveform generating module, amplitude adjusting module, data coding module, clock frequency division module and agreement output module.The beneficial effects of the invention are as follows having built the hardware circuit that a variety of digital audio protocol standards may be implemented, and output logic level can be carried out customized, the quantitative test analysis to the compatible performance of logic level is devices under may be implemented.
Description
Technical field
The present invention relates to audio analysis field, especially a kind of customized multi-protocols digital audio and video signals generating system of level
And method.
Background technique
Currently, digital audio field possesses a variety of different types of digital audio interfaces, the interface standard of mainstream includes disappearing
Take the interconnection of class digital audio interface S/PDIF digital audio and profession class digital audio interface AES/EBU digital audio interface two
Standard.The digital audio of current audio analyzer occurs and analytic function is mainly for S/PDIF interface and AES/EBU interface
The signal of two standards occurs and analysis.Audio analyzer, which generates, during the test meets corresponding digital audio protocol standard
Digital signal is input in digital audio receiving device, to detect digital audio receiving device decoding performance.Audio analyzer is defeated
The digital signal of Different Logic level tests digital audio receiving device to the compatibility of level out.
General audio analyzer generates digital audio and video signals, general sound using dedicated digital audio protocol coding chip
The functional block diagram of frequency division analyzer is as shown in Figure 1, working principle is as follows：CPU is by digital audio protocol parameter and digital audio-frequency data
It is written in the corresponding register of pro digital audio encoding chip, enabling signal output function.The digital sound of coding chip output
The fixed level that logic level generation circuit generates is applied in digital signal by frequency signal through level selection circuit, is realized not
Coding with logic level different digital audio protocols exports.
Resolution circuitry complexity occurs for universal audio analyzer digital audio and video signals, needs to design special logic level and generates
Circuit；Digital audio standards are single, and every kind of digital audio standards are both needed to special coding chip and realize that digital audio and video signals generate；
Flexibility is poor, can only export several typical logic level such as+5V ,+3.3V ,+2.5V ,+1.8V and+1.2V, receives in test
It is only capable of providing the qualitative index of typical logic level when apparatus logic level compatibility, it is simultaneous that specific logic level can not be provided
The quantizating index of capacitive.
Summary of the invention
The purpose of the present invention is to overcome above-mentioned the deficiencies in the prior art, provide a kind of customized multi-protocols number sound of level
Frequency signal generating system and method.
To achieve the above object, the present invention adopts the following technical solutions：
A kind of customized multi-protocols digital audio and video signals generating system of level, including host computer, FPGA, digital analog converter,
The host computer is connect with FPGA, and the FPGA is connect with digital analog converter；
The FPGA includes state code memory, waveform generating module, amplitude adjusting module, data coding module, clock
Frequency division module and agreement output module；
The state code memory is inputted with host computer and is connected, for storing the status code in digital audio encoding；
The waveform generating module, for generating Wave data；
The data coding module, status code and waveform generating module for storing state code memory generate waveform
Data carry out protocol code；
The clock frequency division module, for bit clock needed for generating agreement output module；
The amplitude adjusting module, the data for generating to data coding module carry out amplitude adjustment, are stored in interim
It is stored in RAM memory；
The agreement output module successively adjusts amplitude under the driving for the bit clock that clock frequency division module provides
Data afterwards are transmitted to digital analog converter.
Preferably, the signal conditioning circuit includes gain adjustment circuit and single-ended difference switching circuit；
The gain adjustment circuit, the signal level for the output of logarithm mode converter carry out gain adjustment, make output electricity
The flat range for meeting 0~5V；
The single-ended difference switching circuit meets different audio protocols for switching the transmission mode of output audio signal
The requirement of standard.
Preferably, the digital analog converter uses high precision digital-to-analog converter.
Based on the method for the customized multi-protocols digital audio and video signals generating system of level, include the following steps：
Step 1 selects the consensus standard of digital audio and video signals in upper computer software set interface, and host computer is according to choosing
Corresponding digital audio protocol encoded program code is passed through FPGA dynamically load interface circuit by fixed consensus standard；
Step 2, upper computer software set interface to each channel status code of each frame in digital audio consensus standard into
Row configuration, and configuration information is sent in the state code memory of FPGA and is stored, wherein frame is with channel status code sum number
The data flow of word audio waveform data, digital audio protocol standard define the number and structure of frame in a data flow, each
The length and format of channel status code position in each frame and digital audio-frequency data.
Step 3, the inside FPGA carry out digital audio protocol encoding setting, are successively read from state code memory each
The channel status code of frame, and the Wave data generated with waveform generating module is combined coding, obtains digital audio encoding number
According to stream；
Step 4, the logic level that FPGA is set according to host computer carry out amplitude adjustment to digital audio encoded data stream
And be stored in interim RAM memory, under the bit clock driving of clock division circuits output, output to digital analog converter
In；
Step 5, digital analog converter receives amplitude digital audio data stream adjusted, and carries out digital-to-analogue conversion, defeated
Single-ended out or differential digital audio signal waveform, and export to signal conditioning circuit；
Step 6, signal conditioning circuit receive single-ended perhaps differential digital audio signal waveform and to single-ended or difference
Digital audio and video signals waveform carries out shaping filter, and output meets the digital audio and video signals of digital audio and video signals consensus standard.
Preferably, in the step 2, the configuration information includes each status code in each channel of each frame.
Preferably, in the step 2, the consensus standard of the digital audio and video signals includes AES/EBU or S/PDIF general
The digital audio protocol of digital audio protocol and other standards.
Preferably, in the step 4, FPGA carries out amplitude adjustment to digital audio data stream using amplitude calibration algorithm.
The beneficial effects of the invention are as follows：
1. the present invention uses high precision digital-to-analog converter chip, output voltage linearly spends, and precision is high, it may be implemented 0~+
Any logic level between 5V voltage；
2. the continuous output of 0~+5V voltage may be implemented in the present invention, therefore can provide and be devices under to logic level
Compatibility, the maximum value and minimum of the maximum value for obtaining logic high and minimum value and logic low can be tested
The quantizating index of the parameters such as value, may be implemented quantitative analysis.
Detailed description of the invention
Fig. 1 is universal audio analyzer digital audio and video signals occurring principle block diagram；
Fig. 2 is the customized multi-protocols digital audio and video signals generating system functional block diagram of level；
Fig. 3 is FPGA internal circuit block diagram.
Specific embodiment
Present invention will be further explained below with reference to the attached drawings and examples.
As shown in Fig. 2, a kind of customized multi-protocols digital audio and video signals generating system of level, including host computer, FPGA, number
Mode converter, the host computer are connect with FPGA, and the FPGA is connect with digital analog converter；
As shown in figure 3, the FPGA includes state code memory, waveform generating module, amplitude adjusting module, data encoding
Module, clock frequency division module and agreement output module；
The state code memory is inputted with host computer and is connected, for storing the status code in digital audio encoding；
The waveform generating module, for generating Wave data；
The data coding module, status code and waveform generating module for storing state code memory generate waveform
Data carry out protocol code；
The clock frequency division module, for bit clock needed for generating agreement output module；
The amplitude adjusting module, the data for generating to data coding module carry out amplitude adjustment, are stored in interim
It is stored in RAM memory；
The agreement output module successively adjusts amplitude under the driving for the bit clock that clock frequency division module provides
Data afterwards are transmitted to digital analog converter.
Preferably, the signal conditioning circuit includes gain adjustment circuit and single-ended difference switching circuit；
The gain adjustment circuit, the signal level for the output of logarithm mode converter carry out gain adjustment, make output electricity
The flat range for meeting 0~5V；
The single-ended difference switching circuit meets different audio protocols for switching the transmission mode of output audio signal
The requirement of standard.
Preferably, the digital analog converter uses high precision digital-to-analog converter.
Based on the method for the customized multi-protocols digital audio and video signals generating system of level, include the following steps：
Step 1 selects the consensus standard of digital audio and video signals in upper computer software set interface, and host computer is according to choosing
Corresponding digital audio protocol encoded program code is passed through FPGA dynamically load interface circuit by fixed consensus standard；
Configuration information is arranged to digital audio consensus standard in step 2, upper computer software set interface, and by configuration information
It is sent in the state code memory of FPGA and stores；
Step 3, the inside FPGA carry out digital audio protocol encoding setting, are successively read from state code memory each
The channel status code of frame, and the Wave data generated with waveform generating module is combined coding, obtains digital audio encoding number
According to stream；
Step 4, the logic level that FPGA is set according to host computer carry out amplitude adjustment to digital audio encoded data stream
And be stored in interim RAM memory, under the bit clock driving of clock division circuits output, output to digital analog converter
In；
Step 5, digital analog converter receives amplitude digital audio data stream adjusted, and carries out digital-to-analogue conversion, defeated
Single-ended out or differential digital audio signal waveform, and export to signal conditioning circuit；
Step 6, signal conditioning circuit receive single-ended perhaps differential digital audio signal waveform and to single-ended or difference
Digital audio and video signals waveform carries out shaping filter, and output meets the digital audio and video signals of digital audio and video signals consensus standard.
Preferably, in the step 2, the configuration information includes each status code in each channel of each frame.
Preferably, in the step 2, the consensus standard of the digital audio and video signals includes AES/EBU or S/PDIF general
The digital audio protocol of digital audio protocol and other standards.
Preferably, in the step 4, FPGA carries out amplitude adjustment to digital audio data stream using amplitude calibration algorithm.
The amplitude calibration algorithm is specially：First according to the output logic level and gain adjustment circuit of setting to output
Signal carries out segmentation calibration, then compares the difference between setting voltage and the actual output voltage of multimeter measurement, calculates
Amplitude regulation coefficient and bias store it in onboard EEPROM；It need to be patrolled according to the output of setting when carry out amplitude adjustment
It collects level and calls the regulation coefficient stored in EEPROM and amount of bias, i.e., exportable accurate logic level.
The present invention uses high precision digital-to-analog converter chip, and output voltage is linearly spent, and precision is high, and 0~+5V may be implemented
Any logic level between voltage.
Scheme occurs for universal audio analyzer digital audio only with several typical logic level such as+5V ,+3.3V ,+2.5V
Output signal.During the test, user only can judge to be devices under whether be compatible under these types of logic level, can
It identifies the logic level, is then judged as compatible, be otherwise judged as incompatible, it only can be with qualitative analysis.
The continuous output of 0~+5V voltage may be implemented in the present invention, therefore can provide and be devices under to logic level
Compatibility can test the maximum value and minimum value of the maximum value for obtaining logic high and minimum value and logic low
Etc. parameters quantizating index, quantitative analysis may be implemented.
Above-mentioned, although the foregoing specific embodiments of the present invention is described with reference to the accompanying drawings, not protects model to the present invention
The limitation enclosed, those skilled in the art should understand that, based on the technical solutions of the present invention, those skilled in the art are not
Need to make the creative labor the various modifications or changes that can be made still within protection scope of the present invention.
Claims (6)
1. a kind of customized multi-protocols digital audio and video signals generating system of level, characterized in that including host computer, FPGA, number
Analog converter, the host computer are connect with FPGA, and the FPGA is connect with digital analog converter；
The FPGA includes state code memory, waveform generating module, amplitude adjusting module, data coding module, clock division
Module and agreement output module；
The state code memory is inputted with host computer and is connected, for storing the status code in digital audio encoding；
The waveform generating module, for generating Wave data；
The data coding module, status code and waveform generating module for storing state code memory generate Wave data
Carry out protocol code；
The clock frequency division module, for bit clock needed for generating agreement output module；
The amplitude adjusting module, the data for generating to data coding module carry out amplitude adjustment, are stored in interim RAM and deposit
It is stored in reservoir；
The agreement output module, it is successively that amplitude is adjusted under the driving for the bit clock that clock frequency division module provides
Data are transmitted to digital analog converter；
A kind of customized multi-protocols digital audio and video signals generating system of level further includes signal conditioning circuit；The signal condition electricity
Road includes gain adjustment circuit and single-ended difference switching circuit；
The gain adjustment circuit, the signal level for exporting to the digital analog converter carry out gain adjustment；
The single-ended difference switching circuit, for switching the transmission mode of output audio signal.
2. the customized multi-protocols digital audio and video signals generating system of level as described in claim 1, characterized in that the number
Analog converter uses high-precision digital-to-analog converter.
3. the customized multi-protocols digital audio and video signals method for generation of level based on any system of claim 1 to 2, special
Sign is to include the following steps：
Step 1, in upper computer software set interface select digital audio and video signals consensus standard, host computer according to select
Corresponding digital audio protocol encoded program code is passed through FPGA dynamically load interface circuit by consensus standard；
Step 2, configuration information is arranged to digital audio consensus standard in upper computer software set interface, and configuration information is sent
It is stored into the state code memory of FPGA；
Step 3, the inside FPGA carry out digital audio protocol encoding setting, each frame are successively read from state code memory
Channel status code, and the Wave data generated with waveform generating module is combined coding, obtains encoded digital audio data stream；
Step 4, the logic level that FPGA is set according to host computer carry out amplitude adjustment to digital audio encoded data stream and deposit
Storage under the bit clock driving of clock division circuits output, is exported into digital analog converter in interim RAM memory；
Step 5, digital analog converter receives amplitude digital audio data stream adjusted, and carries out digital-to-analogue conversion, and output is single
End or differential digital audio signal waveform, and export to signal conditioning circuit；
Step 6, signal conditioning circuit receive single-ended perhaps differential digital audio signal waveform and to single-ended or differential digitals
Audio signal waveform carries out shaping filter, and output meets the digital audio and video signals of digital audio and video signals consensus standard.
4. the customized multi-protocols digital audio and video signals method for generation of level as claimed in claim 3, characterized in that the step
In two, the configuration information includes each status code in each channel of each frame.
5. the customized multi-protocols digital audio and video signals method for generation of level as claimed in claim 3, characterized in that the step
In two, the consensus standard of the digital audio and video signals includes AES/EBU or S/PDIF general digital audio protocols.
6. the customized multi-protocols digital audio and video signals method for generation of level as claimed in claim 3, characterized in that the step
In four, FPGA carries out amplitude adjustment to digital audio data stream using amplitude calibration algorithm.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101592707A (en) * | 2009-07-08 | 2009-12-02 | 天津渤海易安泰电子半导体测试有限公司 | Analog and digital mixed signal chip test card |
| CN105116183A (en) * | 2015-08-24 | 2015-12-02 | 中国科学院微电子研究所 | Multichannel waveform signal generator |
| CN105259442A (en) * | 2015-10-30 | 2016-01-20 | 江苏省电力公司电力科学研究院 | UPFC control protection system testing device and method with isochronous transmission function on the basis of multiple protocols |
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| JP2005127765A (en) * | 2003-10-22 | 2005-05-19 | Toshiba Corp | Semiconductor test module and test method of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101592707A (en) * | 2009-07-08 | 2009-12-02 | 天津渤海易安泰电子半导体测试有限公司 | Analog and digital mixed signal chip test card |
| CN105116183A (en) * | 2015-08-24 | 2015-12-02 | 中国科学院微电子研究所 | Multichannel waveform signal generator |
| CN105259442A (en) * | 2015-10-30 | 2016-01-20 | 江苏省电力公司电力科学研究院 | UPFC control protection system testing device and method with isochronous transmission function on the basis of multiple protocols |
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