CN204131478U - Based on the DDS signal generator of FPGA - Google Patents

Abstract

Based on the DDS signal generator of FPGA, relate to DDS signal generator, at present output waveform is there is based on the signal generator of DDS chip and fixes in the utility model in order to solve, lack the problem of Long-distance Control and very flexible, the utility model comprises remote input, bluetooth module, 32 bit accumulators, ROM, D/A converting circuit, electric current turns potential circuit, second order active low pass filter and amplitude regulating circuit, remote input and bluetooth module radio communication, bluetooth module is communicated with 32 bit accumulators, 32 bit accumulators are communicated with ROM, the output of ROM is communicated with D/A converting circuit, D/A converting circuit and electric current turn potential circuit and are communicated with, the output that electric current turns potential circuit is communicated with second order active low pass filter, the output of second order active low pass filter is communicated with amplitude regulating circuit, the output of amplitude regulating circuit is the output of DDS signal generator.The utility model is applicable to DDS signal generator.

Description

Based on the DDS signal generator of FPGA

Technical field

The utility model relates to DDS signal generator.

Background technology

Signal generator is widely used in teaching, scientific research as the basic electronic equipment of one.Along with the development of programmable logic device (FPGA), the maturation further of Direct frequency synthesizer (DDS) technology application, makes the signal generator based on DDS chip be able to extensive use.

But there is the problem that output waveform is fixed, lacked Long-distance Control and very flexible in the current signal generator based on DDS chip.

Utility model content

The purpose of this utility model at present there is based on the signal generator of DDS chip the problem that output waveform fixes, lacks Long-distance Control and very flexible to solve, and provides a kind of DDS signal generator based on FPGA.

Based on the DDS signal generator of FPGA, it comprises remote input, bluetooth module, 32 bit accumulators, ROM, D/A converting circuit, electric current turns potential circuit, second order active low pass filter and amplitude regulating circuit, remote input and bluetooth module pass through communicating wireless signals, the signal output part of bluetooth module is communicated with the signal input part of 32 bit accumulators, the signal output part of 32 bit accumulators is communicated with the signal input part of ROM, the signal output part of ROM is communicated with the signal input part of D/A converting circuit, the signal input part that signal output part and the electric current of D/A converting circuit turn potential circuit is communicated with, the signal output part that electric current turns potential circuit is communicated with the signal input part of second order active low pass filter, the signal output part of second order active low pass filter is communicated with the signal input part of amplitude regulating circuit, the signal output part of amplitude regulating circuit is the output of DDS signal generator.

The utility model utilizes DDS principle in FPGA platform, achieve the generation of multiple waveforms signal, and by remote input frequency control word M, achieving can the generation of online updating waveform signal as requested, there is the feature of Long-distance Control, different frequency, the sine wave of amplitude, triangular wave, square-wave signal can be produced, meet many wave form output of desired indicator, emulation and measured result all confirm its flexibility and reliability.

Accompanying drawing explanation

Fig. 1 is system configuration schematic diagram of the present utility model, Fig. 2 is the circuit diagram of embodiment two D/A converting circuit, Fig. 3 is the circuit diagram that the electric current of embodiment three turns potential circuit, Fig. 4 is the circuit diagram of the second order active low pass filter of embodiment four, Fig. 5 is the circuit diagram of the amplitude regulating circuit of embodiment five, Fig. 6 is the DDS program flow diagram of embodiment six, Fig. 7 is the sine wave output time stimulatiom oscillogram of embodiment six, Fig. 8 is the oscillogram of the sine wave output of embodiment six, Fig. 9 is the oscillogram of the output triangular wave of embodiment six, Figure 10 is the oscillogram of the output square wave of embodiment six.

Embodiment

Embodiment one: composition graphs 1 illustrates present embodiment, based on the DDS signal generator of FPGA described in present embodiment, it comprises remote input 1, bluetooth module 2, 32 bit accumulators 3, ROM4, D/A converting circuit 5, electric current turns potential circuit 6, second order active low pass filter 7 and amplitude regulating circuit 8, remote input 1 and bluetooth module 2 pass through communicating wireless signals, the signal output part of bluetooth module 2 is communicated with the signal input part of 32 bit accumulators 3, the signal output part of 32 bit accumulators 3 is communicated with the signal input part of ROM4, the signal output part of ROM4 is communicated with the signal input part of D/A converting circuit 5, the signal input part that signal output part and the electric current of D/A converting circuit 5 turn potential circuit 6 is communicated with, the signal output part that electric current turns potential circuit 6 is communicated with the signal input part of second order active low pass filter 7, the signal output part of second order active low pass filter 7 is communicated with the signal input part of amplitude regulating circuit 8, the signal output part of amplitude regulating circuit 8 is the output of DDS signal generator.

The utility model utilizes bluetooth module 2, the frequency control word M of remote input 1 is input to 32 bit accumulators 3 and carries out accumulating operation, intercept the 24 to the 30 address as ROM (read-only memory) 4 of 32 bit accumulators 3, in read only memory ROM 4, store the digital waveform data of 8; ROM4 is under the control of accumulator, export the digital waveform data of 8, analog quantity is converted to through D/A converting circuit 5, because what D/A converting circuit 5 exported is the form of electric current, so be converted to the analog waveform of voltage form by Voltage-current conversion circuit 6, but wherein also containing a large amount of radio-frequency components, in order to the signal waveform that output frequency is pure, again by the active low-pass filter 7 of a second order, finally in order to the peak-to-peak value of regulation output signal, introduce an amplitude regulating circuit 8 again, achieve and meet desired indicator, reliable many wave form output.

According to direct digital synthesis technique theory, the frequency resolution of system and output frequency are written as:

$\begin{array}{cc}{f}_{\min }=\frac{f_{\mathrm{clk}}}{2^N}& f_{\mathrm{out}}=\frac{f_{\mathrm{clk}}}{2^N}\×M\end{array}---\left(1\right)$

Wherein f _clkbe system clock and bit wide with N, M is frequency control word, utilizes signal phase and time linear characteristic, directly samples to desired signal, quantizes and map, the signal waveform that output frequency is adjustable.In each clock cycle, determine that the size of phase increment is to control output frequency by frequency control word M.F can be found out by formula _clkalso be related to the frequency of D/A conversion with N, bit wide N is larger, clock f _clklower, resolution is higher, but system clock step-down, also can reduce maximum output frequency, and the output number of the sample magnitude of one-period waveform.

Embodiment two: composition graphs 2 illustrates present embodiment, present embodiment be to described in embodiment one based on the further restriction of the DDS signal generator of FPGA, D/A converting circuit 5 adopts DAC0832.

D/A converting circuit 5 adopts DAC0832, and DAC0832 is the inverted T resistor network type D/A converter of 8 bit resolutions.According to the data latches of DAC0832 and the different control modes of DAC register, DAC0832 has three kinds of working methods: direct-passing mode, single buffer mode and double buffering mode; The utility model uses straight-through working method.The input of DAC0832 logic meets Transistor-Transistor Logic level, can directly be connected with TTL circuit or microcomputer circuit.

Embodiment three: composition graphs 3 illustrates present embodiment, present embodiment be to described in embodiment one based on the further restriction of the DDS signal generator of FPGA, electric current turns potential circuit 6 and adopts NE5532.

Because the transformation result of DAC0832 exports as an electrical current.In order to obtain analog voltage signal, need the linear operational amplifier by a high input impedance.The feedback resistance of amplifier quotes intrinsic resistance in sheet by RFB end, also can be external.In order to the analog current value be converted to by DAC0832 is converted to the magnitude of voltage of simulation, the electric current be made up of amplifier NE5532 in the output termination of ADC0832 turns potential circuit, as shown in Figure 3.

NE5532 is high-performance low-noise dual operational amplifier (double operational) integrated circuit.Similar to a lot of standard amplifier, but it has better noiseproof feature, excellent output driving force and quite high small signal bandwidth, the features such as supply voltage scope is large.Therefore be well suited for being applied in high-quality and Specialty Hi-Fi equipment, instrument, control circuit and telephone channel amplifier.

The switching current of DAC0832 exports and is:

$I_{\mathrm{OUT}1}=\frac{V_{\mathrm{REF}}}{15\mathrm{k\Ω}}\×\frac{\mathrm{Digital}\_\mathrm{Input}}{256}---\left(2\right)$

$I_{\mathrm{OUT}2}=\frac{V_{\mathrm{REF}}}{15\mathrm{k\Ω}}\×\frac{255-\mathrm{Digital}\_\mathrm{Input}}{256}---\left(3\right)$

Electric current turns voltage output:

Vout＝-(I _OUT1×R ₁₉) (4)。

Embodiment four: composition graphs 4 illustrates present embodiment, present embodiment be to described in embodiment one based on the further restriction of the DDS signal generator of FPGA, second order active low pass filter 7 adopts NE5532.

Second order active low pass filter also adopts amplifier NE5532, its cut-off frequency is designed to 6KHz, the output highest frequency of function signal generator is 20KHz, situation according to occurring in reality debugging: when the cut-off frequency of low pass filter is designed to 6KHz, the waveform frequency exported is pure, if improve the cut-off frequency of low pass filter, output waveform just has radio-frequency component, if reduce the highest frequency that cut-off frequency will reduce output waveform.Second order active low pass filter as shown in Figure 4.

Its characteristic frequency is:

$f_0=\frac{1}{2\mathrm{\πRC}}---\left(5\right)$

Bring R=1K Ω, C=10nF into formula 5 and calculate f ₀=16KHz.The cut-off frequecy of passband of second-order low-pass filter is: f _p=0.37f ₀, by f ₀=16KHz brings into and calculates cut-off frequency f _p=5.92KHz, passband multiplication factor is 1.

Embodiment five: composition graphs 5 illustrates present embodiment, present embodiment be to described in embodiment one based on the further restriction of the DDS signal generator of FPGA, amplitude regulating circuit 8 adopts NE5532.

In order to the amplitude realizing output waveform is adjustable, connect a voltage follower at the output of function signal generator, and by the waveform peak of a slide rheostat regulation output.Amplitude transfer circuit 8 is made up of amplifier NE5532, as shown in Figure 5.

Embodiment six: composition graphs 6 to Figure 10 illustrates present embodiment, present embodiment be to described in embodiment one based on the further restriction of the DDS signal generator of FPGA, amplitude regulating circuit 8 also comprises LCD display, and the signal input part of LCD display is communicated with the signal output part of amplitude regulating circuit (8).

LCD display is used for the type of instant playback waveform signal, frequency and amplitude.

Composition graphs 6 illustrates embody rule process of the present utility model:

DDS program flow diagram as shown in Figure 6,32 bit accumulators constantly add up to the frequency control word exported, get 32 bit accumulators the 24 to the 30 address as ROM, according to the 32nd of 32 bit accumulators and the value of the 31st, data are exported to ROM address and ROM and do following process:

1) the 32nd equal 0 and the 31st equal 0, then to export data constant for ROM address and ROM;

2) the 32nd equal 0 and the 31st equal 1, then to export data constant for the negate of ROM address but ROM;

3) the 32nd equal 1 and the 31st equal 0, then constant the but ROM in ROM address exports data-conversion;

4) the 32nd equal 0 and the 31st equal 0, then the negate of ROM address and ROM export data also negate.

The time stimulatiom waveform of DDS sine wave output as shown in Figure 7.First signal is 100MHz system clock clk, and second signal is reset signal rst_n, and the 3rd signal is accumulator add, and the 4th signal is most-significant byte and the ROM address of accumulator, and the 6th signal is ROM output and Wave data.

Composition graphs 8 to Figure 10 illustrates hardware debug:

This signal generator can export amplitude, the sine wave of frequency-adjustable, square wave, the triangular signal of certain power.The frequency resolution of this signal generator output waveform is 1Hz, reference frequency output: 1Hz-20kHz, output voltage range: 50mV-1V.

Because the electric capacity of low pass filter is on the discharge and recharge impact exporting triangular wave and square wave, export triangular wave and square wave frequency higher, affect more serious, causes the wave distortion of output.Through measuring, the distortionless frequency of output of triangular wave is about 5KHz, and exporting the distortionless frequency of square wave is about 2KHz.Because DDS adopts digital structure, inevitably introduce loose assorted.Its source mainly contains three: it is loose assorted that phase accumulator phase place rounding error causes; It is loose assorted that the loose assorted and DAC non-ideal characteristic that amplitude quantization error causes causes.

Function signal generator output frequency be the sine wave of 1.3KHz as shown in Figure 8, function signal generator output frequency be the triangular wave of 1.2KHz as shown in Figure 9, function signal generator output frequency be the square wave of 1.2KHz as shown in Figure 10.Result shows that output waveform reaches the requirement of design objective, can use as stable signal source.

Claims (6)

1. based on the DDS signal generator of FPGA, it is characterized in that, it comprises remote input (1), bluetooth module (2), 32 bit accumulators (3), ROM (4), D/A converting circuit (5), electric current turns potential circuit (6), second order active low pass filter (7) and amplitude regulating circuit (8), remote input (1) and bluetooth module (2) pass through communicating wireless signals, the signal output part of bluetooth module (2) is communicated with the signal input part of 32 bit accumulators (3), the signal output part of 32 bit accumulators (3) is communicated with the signal input part of ROM (4), the signal output part of ROM (4) is communicated with the signal input part of D/A converting circuit (5), the signal input part that signal output part and the electric current of D/A converting circuit (5) turn potential circuit (6) is communicated with, the signal output part that electric current turns potential circuit (6) is communicated with the signal input part of second order active low pass filter (7), the signal output part of second order active low pass filter (7) is communicated with the signal input part of amplitude regulating circuit (8), the signal output part of amplitude regulating circuit (8) is the output of DDS signal generator.

2. according to claim 1 based on the DDS signal generator of FPGA, it is characterized in that, D/A converting circuit (5) adopts DAC0832.

3. according to claim 1 based on the DDS signal generator of FPGA, it is characterized in that, electric current turns potential circuit (6) and adopts NE5532.

4. according to claim 1 based on the DDS signal generator of FPGA, it is characterized in that, second order active low pass filter (7) adopts NE5532.

5. according to claim 1 based on the DDS signal generator of FPGA, it is characterized in that, amplitude regulating circuit (8) adopts NE5532.

6. according to claim 1 based on the DDS signal generator of FPGA, it is characterized in that, amplitude regulating circuit (8) also comprises LCD display, and the signal input part of LCD display is communicated with the signal output part of amplitude regulating circuit (8).