CN106839963A - A kind of bus deformeters of AXIe 0 and strain testing method - Google Patents
A kind of bus deformeters of AXIe 0 and strain testing method Download PDFInfo
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- CN106839963A CN106839963A CN201611241555.0A CN201611241555A CN106839963A CN 106839963 A CN106839963 A CN 106839963A CN 201611241555 A CN201611241555 A CN 201611241555A CN 106839963 A CN106839963 A CN 106839963A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
- G01B7/00—Measuring arrangements characterised by the use of electric or magnetic techniques
- G01B7/16—Measuring arrangements characterised by the use of electric or magnetic techniques for measuring the deformation in a solid, e.g. by resistance strain gauge
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Abstract
The invention discloses a kind of bus deformeters of AXIe 0 and strain testing method, the deformeter includes：AXIe interfaces, arm processor, synchronous trigger module, fpga logic and front end processing block；Front end processing block includes N number of signal sampling channel, for under the control of corresponding logic, N number of foil gauge is set to export the first data signal and analog voltage signal respectively when strain is produced, and channel recognition is carried out to N number of first data signal obtain channel recognition result, N number of analog voltage signal nurse one's health and obtains N number of second data signal, and channel recognition result and N number of second data signal are sent to fpga logic.The bus deformeters of AXIe 0 that the present invention is provided can realize the strain signal measurement of multiple passages, with bus synchronous and Trigger Function, it is ensured that each module in AXIe cabinets can work asynchronously.
Description
Technical field
The present invention relates to Auto-Test System and surveying instrument field, more particularly to a kind of AXIe-0 buses deformeter
And strain testing method.
Background technology
AXIe-0 instruments are a kind of card insert type instruments, with ATCA connectors.AXIe-0 instruments need insertion when working
AXIe cabinets, its ATCA connector is connected with AXIe case back plates, and LAN communication buses, Trigger Bus, same are provided by AXIe cabinets
Step clock and power supply, when setting up Auto-Test System, the AXIe-0 instruments of AXIe controllers and polylith identical function are together inserted
AXIe cabinets, by LAN mouthfuls of AXIe controllers by AXIe system access networks, set up main control computer with AXIe-0 instruments
Ethernet communication, realizes the extension of AXIe-0 instruments multiple passage.AXIe-0 instruments are suitably applied centralization test measurement system
System.
The content of the invention
It is total the invention provides a kind of AXIe-0 the need in order to meet large scale structure multichannel stress test application scenario
Line strain instrument and strain testing method.
The AXIe-0 bus deformeters that the present invention is provided, including：AXIe interfaces, arm processor, synchronous trigger module,
Fpga logic and front end processing block；
The arm processor, for by the AXIe interfaces command signal, being parsed to the command signal
Obtain director data and send to the fpga logic；
The synchronous trigger module, for by the AXIe interfaces clock signal and trigger signal, to it is described when
Clock signal and the trigger signal synchronize treatment, obtain synchronizing clock signals and synchronous triggering signal, and send to described
Fpga logic；
The fpga logic, for receiving director data and the synchronous trigger module hair that the arm processor sends
The synchronizing clock signals and synchronous triggering signal for sending, trigger corresponding logic, to realize the control to the front-end circuit；
The front end processing block, including N number of signal sampling channel, under the control of the corresponding logic, making N
Individual bridge sensor exports the first data signal and analog voltage signal respectively when strain is produced；And to N number of described first
Data signal carries out channel recognition and obtains channel recognition result, N number of analog voltage signal nurse one's health obtains N number of second
Data signal, and the channel recognition result and N number of second data signal are sent to the fpga logic；Wherein N is
Positive integer；
The fpga logic, is additionally operable to, according to the channel recognition result and N number of second digital voltage signal, obtain
The fpga logic is write after digital voltage signal with channel recognition numbering；
The arm processor, is additionally operable to read the digital voltage with channel recognition numbering of the fpga logic
Signal, and send extraneous by AXIe interfaces.
Present invention also offers a kind of strain testing method of AXIe-0 buses deformeter, the AXIe-0 buses deformeter
In insertion AXIe cabinets, comprise the following steps：
Command signal is received, the command signal is parsed, director data is obtained；
Clock signal and trigger signal are received, treatment is synchronized to the clock signal and the trigger signal, obtained
Synchronizing clock signals and synchronous triggering signal；
Based on the synchronizing clock signals and synchronous triggering signal, according to the director data, corresponding logic is triggered；
Under the control of the corresponding logic, N number of bridge sensor is set to export the first numeral respectively when strain is produced
Signal and analog voltage signal；
Channel recognition is carried out to N number of first data signal and obtains channel recognition result, N number of analog voltage is believed
Number nurse one's health and obtain N number of second data signal；
According to the channel recognition result and N number of second digital voltage signal, obtain with channel recognition numbering
Digital voltage signal, and send to the external world.
The present invention has the beneficial effect that：
AXIe-0 buses deformeter provided in an embodiment of the present invention, is capable of achieving the strain signal measurement of multiple passage, should
Becoming instrument has bus synchronous and Trigger Function, it is ensured that each module in AXIe cabinets can work asynchronously, while can will be many
Individual AXIe-0 buses deformeter is integrated into AXIe cabinets to realize further expanding for strain measurement passage.
Brief description of the drawings
Fig. 1 is the structural representation of the AXIe-0 bus deformeters of apparatus of the present invention embodiment；
Fig. 2 is the structural representation of the AXIe-0 bus deformeters of apparatus of the present invention examples Example 1；
Fig. 3 is the flow chart of the strain testing method of the AXIe-0 bus deformeters of the inventive method embodiment.
Specific embodiment
The exemplary embodiment of the disclosure is more fully described below with reference to accompanying drawings.Although showing the disclosure in accompanying drawing
Exemplary embodiment, it being understood, however, that may be realized in various forms the disclosure without should be by embodiments set forth here
Limited.Conversely, there is provided these embodiments are able to be best understood from the disclosure, and can be by the scope of the present disclosure
Complete conveys to those skilled in the art.
It is total the invention provides a kind of AXIe-0 the need in order to meet large scale structure multichannel stress test application scenario
Line strain instrument and strain testing method, below in conjunction with accompanying drawing and embodiment, the present invention will be described in further detail.Should
Understand, the specific embodiments described herein are merely illustrative of the present invention, do not limit the present invention.
A kind of apparatus according to the invention embodiment, there is provided AXIe-0 buses deformeter, Fig. 1 is that apparatus of the present invention are implemented
The structural representation of the AXIe-0 bus deformeters of example, as shown in figure 1, the AXIe-0 buses according to apparatus of the present invention embodiment should
Becoming instrument includes：AXIe interfaces 10, arm processor 14, synchronous trigger module 12, fpga logic 16 and front end processing block 18, with
Under the modules of the embodiment of the present invention are described in detail.
Specifically, the connection of the AXIe interfaces 10 AXIe case back plates, including 48V power supply signals, LAN communication buses letter
Number, 3 parts such as synchronous Trigger Bus signal.48V power supply signals by power conversion unit, output+3.3V ,+5V ,+12V ,-
The multiple power sources such as 12V voltage is used for instrument internal circuit；LAN communication buses signal is by network filter, LAN PHY cores
Piece, is then attached to arm processor, sets up the LAN communication links of arm processor and main control computer；Synchronous Trigger Bus letter
Number it is connected to " synchronous triggering " element circuit.
The arm processor 14, for receiving command signal by the AXIe interfaces 10, is carried out to the command signal
Parsing obtains director data and sends to the fpga logic.
Specifically, the arm processor 14 is the control administrative center of whole instrument, run in processor embedded
(SuSE) Linux OS, performs ICP/IP protocol stack and realizes network communication, and the main instruction for being responsible for reception main control computer is (i.e.
The command signal that AXIe cabinets send), and parse, then the result according to instruction parsing performs corresponding service, for example initially
Change instrument, driving source is set, sensor connected mode, control signal modulate circuit is set, is started strain signal collection etc..Need
It should be noted that arm processor controls each conditioning and Acquisition Circuit by fpga logic, arm processor is sent out to FPGA by all means
Instruction (writing register) or read data register, all of control sequential are realized in FPGA.
The synchronous trigger module 12, for by the AXIe interfaces clock signal and trigger signal, to described
Clock signal and the trigger signal synchronize treatment, obtain synchronizing clock signals and synchronous triggering signal, and send to institute
State fpga logic.Wherein, the synchronizing clock signals and the synchronous triggering signal are used for as RAM processors 14, described
Fpga logic 16 and the front end processing block 18 provide synchronised clock and synchronous triggering.
Specifically, synchronous triggering：It is main to increase the clock signal in AXIe buses, trigger signal specific buffering core
Piece.Clock signal is linked into FPGA logic cell by clock buffer chip, and so FPGA in each AXIe deformeter is used
With the clock of frequency same-phase, the consistent purpose of different AXIe deformeters sequential is reached.Trigger signal is linked into by buffer
FPGA logic cell, can receive the triggering input of AXIe backboards, it is also possible to the trigger signal output for exporting this instrument FPGA
To AXIe backboards, different AXIe deformeters triggering collection simultaneously is realized.So, because the clock of different AXIe deformeters is same with frequency
Phase, and again can be with synchronization triggering collection, such that it is able to realize the collection synchronization between different AXIe deformeters.It is " same
Step triggering " unit, by arm processor control, can be also exported trigger signal to the interrupt pin of ARM, to notify arm processor
An existing trigger event is produced.
The fpga logic 16, director data and the synchronous trigger mode for receiving the transmission of the arm processor 14
Synchronizing clock signals and synchronous triggering signal that block 12 sends, trigger corresponding logic, to realize to the front end processing block
18 control.
Specifically, the fpga logic is a kind of PLD, it is made up of some gate circuits, user can pass through
Programming realization is adapted to the logic circuit or state machine of oneself, such as register, MUX, decoder, control sequential.AXIe
FPGA in deformeter mainly connects arm processor, synchronous triggering, and A/D, D/A, 1-wire device are (in sensor identification chip
Storage information read) etc..The director data of fpga logic primary recipient arm processor (is specified from arm processor in FPGA
Register writes director data), corresponding logic is then triggered, realize the control to specified circuit.
The front end processing block 18, including N number of signal sampling channel, under the control of the corresponding logic,
N number of bridge sensor is set to export the first data signal and analog voltage signal respectively when strain is produced；And to N number of described
One data signal carries out channel recognition and obtains channel recognition result, N number of analog voltage signal nurse one's health obtains N number of
Two digital signal, and the channel recognition result and N number of second data signal are sent to the fpga logic；Wherein N
It is positive integer.
Fig. 2 is the structural representation of the AXIe-0 bus deformeters of apparatus of the present invention examples Example 1, institute as shown in Figure 2
Front end processing block 18 is stated including a multichannel synchronousing collection module and N number of single channel acquisition module (in fig. 2 including 20
Single channel acquisition module)；Wherein, a single channel acquisition module includes front end signal conditioning unit, driving source, one
Individual sensor recognition unit and an electric bridge.
The driving source, under the control of the corresponding logic for an electric bridge provides supply voltage so that institute
State bridge sensor and export the first data signal and analog voltage signal when strain is produced；Wherein, wrapped in the first data signal
Channel information is included, module voltage signal includes strain measurement object information.
Specifically, foil gauge is passive device, it is necessary to outside apply supply voltage.AXIe deformeters can be strained for each
Measurement channel exports the program-controlled voltage sources of -5~+5V, and driving current can reach 50mA.Foil gauge is by exportable after excitation
One voltage signal.
The front end signal conditioning unit, for nursing one's health the analog voltage signal, and by the simulation after conditioning
Voltage signal is sent to the multichannel synchronousing collection module.
Specifically, the front end signal conditioning unit includes that electric bridge switching circuit, zero compensation circuit, signal amplify electricity
Road, filter circuit and single-ended transfer difference circuit；
The electric bridge switching circuit, for the selection of full-bridge, half-bridge, 1/4 bridge in the electric bridge；
The zero compensation circuit, the zero point for adjusting each single channel acquisition module；
The signal amplification circuit, for the analog voltage signal to be amplified；
The filter circuit, for the analog voltage signal after amplification to be filtered；
The single-ended transfer difference circuit, for filtered single-ended signal to be converted into differential signal.Single-ended signal is turned
Be conducive to improving channel ratio after being changed to differential signal.
That is front end signal conditioning, 20 road strain signals have respective signal conditioning circuit, main to include input protection electricity
Road (prevent maloperation, input signal is excessive and damage instrument internal circuit), electric bridge switching circuit (full-bridge, half-bridge, the choosing of 1/4 bridge
Select), zero compensation (adjusting the zero point of each analog acquisition passage), signal amplification circuit (gather, can carry again after low level signal amplification
Height collection precision), filter circuit (filtering interference signals, such as 50Hz Hz noises), single-ended transfer difference circuit (A/D turn
The input of parallel operation is Differential Input) etc..
Further, passage alignment unit is also included in the front-end circuit；The passage alignment unit, for described
Front end signal conditioning unit is calibrated and is sent to the fpga logic result after calibration.
Specifically, the passage calibration includes Shunt calibrations, passage self calibration." Shunt calibrations " by electric bridge certain
Big resistance known to one in parallel on individual bridge arm, with the known strained value for producing an original arm resistance value of ratio smaller, quite
In a process for strain variation is simulated, the method is mainly used in eliminating the mistake of the sensitivity of strain gauge reduction that line stopband comes
Difference, mainly by simulating predetermined strain value, the gain coefficient of sensitivity of strain gauge or instrument is adjusted until instrument at instrument end
Device end shows predetermined strain value." passage self calibration " nurses one's health the temperature drift of passage in order to eliminate, and each Measurement channel has one
Individual calibration source, there is provided zero point and the automatic calibration function of gain are compensated with the measured value to subsequent acquisition.
As shown in Fig. 2 the present invention devises a kind of AXIe-0 buses deformeter, there are individual module 20 strain measurements to lead to
Road, supports 1/4 bridge, 1/2 bridge and full bridge measurement, supports channel recognition, supports synchronous triggering.Answered by by polylith AXIe-0 buses
Become during instrument is installed to AXIe cabinets and realize that the strain signal of multichannel is measured.For example, inserting 5 pieces of AXIe- in 5 groove AXIe cabinets
0 bus deformeter, you can to set up into the strain gauge of 100 passages.The strain measurement system built using which is had
The advantages of high channel track density, remote control, it is particularly suitable for the application scenario of the multichannel stress test of large scale structure, Er Qiezhi
Hold the identification of TEDS sensors, CID channel recognitions, it is possible to resolve the problem of passage is difficult to because connection cables are long.
The multichannel synchronousing collection module, for receiving the simulation after the conditioning that N number of front end signal conditioning module sends
Voltage signal, second digital voltage signal is converted to by the analog voltage signal after the conditioning.
Specifically, multichannel synchronousing collection：It is main to include 20 A/D conversions (analog-to-digital conversion) of passage, provided by FPGA
The logic control signals such as clock, collection sequential, are responsible for being converted into the analog voltage signal that " front end signal conditioning " unit is exported
Data signal." synchronous acquisition " by FPGA SECO, when the control sequential complete that FPGA is exported to 20 A/D conversion chips
During cause, the digital voltage of A/D conversion chips output is simultaneously.
The sensor recognition unit, for being carried out according to first data signal under the control of the fpga logic
Measurement channel is recognized, and channel recognition result is sent to the fpga logic.
Specifically, the sensor recognition unit is CID sensors recognizing or the identification of TEDS sensors.
CID circuits are designed in strain signal transfer wire, facilitates strain measurement channel recognition；Set in modulate circuit part
Meter TEDS circuits, the convenient sensor with TEDS functions (sensor electronic tables of data window) is recognized.
The identification of CID sensors needs a CID circuit of being connected in connection cables of the foil gauge with deformeter, and its core is
One 1-wire memory device, the inside is previously written channel information (such as positional information of strain gauge adhesion, passage code name),
To that should have a 1-wire control chip, arm processor can read the information stored in CID by the chip at deformeter end,
So as to recognize passage.This mode does not need extra cable expense (the core number of cable is constant), in strain measurement number of channels
Greatly, and when foil gauge and deformeter are distant it is applicable very much.
The identification of TEDS sensors is to increased a 1-wire EEPROM memory cell in sensor internal, can be write in advance
Enter content, 2 cores of extra increase on the basis of original cable are needed when sensor is connected with deformeter, for the biography of TEDS signals
Defeated, at deformeter end to that should have a 1-wire control chip, arm processor can read TEDS electrical forms by the chip
The information of middle storage, so as to recognize passage.This mode needs extra cable expense (the core number of cable increases by 2), is adapted to
In most of sensor (being not limited to strain transducer).
The further fpga logic 16, is additionally operable to export trigger signal；The synchronous trigger module 12, be additionally operable to by
The trigger signal of the fpga logic output is exported to the external world by the AXIe interfaces, can so specify deformeter to specify logical
The synchronous acquisition between differently strained instrument is realized as trigger source in road.
The invention discloses a kind of AXIe-0 buses deformeter, high density stress-strain measurement occasion is applied to.Instrument is hard
Part is connect by sensor identification circuit, driving source, front end modulate circuit, calibration circuit, synchronous acquisition circuit, triggers circuit, AXIe
The parts such as mouth circuit constitute, and AXIe cabinets are installed on when using, by main control computer by LAN controls.Channel recognition circuit reality
The identification of existing TEDS sensors, CID channel recognitions；Driving source externally provides program-controlled constant pressure source, for electric bridge provides supply voltage；
Front end modulate circuit is nursed one's health 1/4 bridge, half-bridge, full bridge signal, including protection, amplification, filtering；Calibration circuit provides internal
Calibration voltage and measuring resistance, for calibrating conditioning acquisition channel；Synchronous acquisition circuit realizes the high-precise synchronization of all passages
Collection, the sequential of A/D converter is realized by PLD；Triggers circuit is realized touching software triggering, backboard LVDS firmly
Hair, the management of the triggerings of IEEE 1588；AXIe interface circuits with arm processor as core, using LXI protocol realization AXIe interfaces
Communication, supports that IEEE 1588 is synchronous, and supports the identification of TEDS sensors, CID channel recognitions, it is possible to resolve due to connection cables
Problem that is long and being difficult to passage.
A kind of the method according to the invention embodiment, there is provided strain testing method of AXIe-0 buses deformeter, Fig. 3 is
The flow chart of the strain testing method of the AXIe-0 bus deformeters of the inventive method embodiment, as shown in figure 3, according to the present invention
The strain testing method of the AXIe-0 bus deformeters of embodiment of the method includes following treatment：
Step 301, receives command signal, parses the command signal, obtains director data；
Step 302, receives clock signal and trigger signal, and place is synchronized to the clock signal and the trigger signal
Reason, obtains synchronizing clock signals and synchronous triggering signal；
Step 303, based on the synchronizing clock signals and synchronous triggering signal, according to the director data, triggering correspondence
Logic；
Step 304, under the control of the corresponding logic, makes N number of bridge sensor be exported respectively when strain is produced
First data signal and analog voltage signal；
Step 305, carries out channel recognition and obtains channel recognition result, to N number of mould to N number of first data signal
Plan voltage signal nurse one's health and obtains N number of second data signal；
Step 306, according to the channel recognition result and N number of second digital voltage signal, obtains knowing with passage
The digital voltage signal do not numbered, and send to the external world.
Specifically, it is described N number of analog voltage signal nurse one's health obtain N number of second data signal including following step
Suddenly：
N number of analog voltage signal is nursed one's health, the analog voltage signal after N number of conditioning is obtained；
Analog voltage signal after N number of conditioning is converted into N number of second digital voltage signal.
The strain testing method of the AXIe-0 bus deformeters of the inventive method embodiment is further comprising the steps of：
Output trigger signal；
By the trigger signal by output to the external world.
The inventive method embodiment provide AXIe-0 bus deformeters strain testing method support 1/4 bridge, 1/2 bridge and
Full bridge measurement, individual module realizes the strain signal measurement of multiple passages, and multiple modules can be realized in being integrated into AXIe cabinets
The extension of strain measurement passage, and with bus synchronous and Trigger Function, it is ensured that each module in AXIe cabinets
Can work asynchronously.
Embodiments of the invention are the foregoing is only, is not intended to limit the invention, for those skilled in the art
For member, the present invention can have various modifications and variations.All any modifications within the spirit and principles in the present invention, made,
Equivalent, improvement etc., should be included within scope of the presently claimed invention.
Claims (9)
1. a kind of AXIe-0 buses deformeter, it is characterised in that including：AXIe interfaces, arm processor, synchronous trigger module,
Fpga logic and front end processing block；
The arm processor, for by the AXIe interfaces command signal, being parsed to the command signal
Director data is simultaneously sent to the fpga logic；
The synchronous trigger module, for by the AXIe interfaces clock signal and trigger signal, believing the clock
Number and the trigger signal synchronize treatment, obtain synchronizing clock signals and synchronous triggering signal, and transmission is to the FPGA
Logic；
The fpga logic, what director data and the synchronous trigger module for receiving the arm processor transmission sent
Synchronizing clock signals and synchronous triggering signal, trigger corresponding logic, to realize the control to the front end processing block；
The front end processing block, including N number of signal sampling channel, under the control of the corresponding logic, making N number of electricity
Bridge sensor exports the first data signal and analog voltage signal respectively when strain is produced；And to N number of first numeral
Signal carries out channel recognition and obtains channel recognition result, N number of analog voltage signal nurse one's health obtain it is N number of second numeral
Signal, and the channel recognition result and N number of second data signal are sent to the fpga logic；Wherein N is just whole
Number；
The fpga logic, is additionally operable to, according to the channel recognition result and N number of second digital voltage signal, to be had
The fpga logic is write after the digital voltage signal of channel recognition numbering；
The arm processor, is additionally operable to read the digital voltage signal with channel recognition numbering of the fpga logic,
And send extraneous by AXIe interfaces.
2. AXIe-0 buses deformeter as claimed in claim 1, it is characterised in that the front end processing block is included more than
Channel Synchronous acquisition module and N number of single channel acquisition module；Wherein, a single channel acquisition module includes that a front end signal is adjusted
Reason unit, driving source, a sensor recognition unit and an electric bridge；
The driving source, under the control of the corresponding logic for an electric bridge provides supply voltage so that the electricity
Bridge sensor exports the first data signal and analog voltage signal when strain is produced；Wherein, the first data signal includes logical
Road information, module voltage signal includes strain measurement object information；
The front end signal conditioning unit, for nursing one's health the analog voltage signal, and by the analog voltage after conditioning
Signal is sent to the multichannel synchronousing collection module；
The multichannel synchronousing collection module, for receiving the analog voltage after the conditioning that N number of front end signal conditioning module sends
Signal, second digital voltage signal is converted to by the analog voltage signal after the conditioning；
The sensor recognition unit, for being measured according to first data signal under the control of the fpga logic
Channel recognition, and channel recognition result is sent to the fpga logic.
3. AXIe-0 buses deformeter as claimed in claim 2, it is characterised in that the front end signal conditioning unit includes electricity
Bridge switching circuit, zero compensation circuit, signal amplification circuit, filter circuit and single-ended transfer difference circuit；
The electric bridge switching circuit, for the selection of full-bridge, half-bridge, 1/4 bridge in the electric bridge；
The zero compensation circuit, the zero point for adjusting each single channel acquisition module；
The signal amplification circuit, for the analog voltage signal to be amplified；
The filter circuit, for the analog voltage signal after amplification to be filtered；
The single-ended transfer difference circuit, for filtered single-ended signal to be converted into differential signal.
4. AXIe-0 buses deformeter as claimed in claim 3, it is characterised in that also include in the front end processing block logical
Road alignment unit；
The passage alignment unit, for carrying out school to the front end signal conditioning unit under the control of the fpga logic
Standard, and the result after calibration is sent to the fpga logic.
5. AXIe-0 buses deformeter as claimed in claim 1, it is characterised in that
The fpga logic, is additionally operable to export trigger signal；
The synchronous trigger module, be additionally operable to by the fpga logic export trigger signal by the AXIe interfaces export to
It is extraneous.
6. AXIe-0 buses deformeter as claimed in claim 1, it is characterised in that the sensor recognition unit uses CID
Sensor is recognized or the identification of TEDS sensors.
7. a kind of strain testing method of AXIe-0 buses deformeter is it is characterised in that it includes following steps：
Command signal is received, the command signal is parsed, director data is obtained；
Clock signal and trigger signal are received, treatment is synchronized to the clock signal and the trigger signal, obtain synchronization
Clock signal and synchronous triggering signal；
Based on the synchronizing clock signals and synchronous triggering signal, according to the director data, corresponding logic is triggered；
Under the control of the corresponding logic, N number of bridge sensor is set to export the first data signal respectively when strain is produced
And analog voltage signal；
Channel recognition is carried out to N number of first data signal and obtains channel recognition result, N number of analog voltage signal is entered
Row conditioning obtains N number of second data signal；
According to the channel recognition result and N number of second digital voltage signal, the numeral with channel recognition numbering is obtained
Voltage signal, and send to the external world.
8. the strain testing method of AXIe-0 buses deformeter as claimed in claim 7, it is characterised in that described to N number of institute
State analog voltage signal and nurse one's health and obtain N number of second data signal and comprise the following steps：
N number of analog voltage signal is nursed one's health, the analog voltage signal after N number of conditioning is obtained；
Analog voltage signal after N number of conditioning is converted into N number of second digital voltage signal.
9. the strain testing method of AXIe-0 buses deformeter as claimed in claim 7, it is characterised in that also including following step
Suddenly：
Output trigger signal；
By the trigger signal by output to the external world.
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Cited By (5)
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| CN108444376A (en) * | 2018-02-10 | 2018-08-24 | 西安前观测控技术有限公司 | Ultra-large real-time distributed strain measurement system |
| CN111189553A (en) * | 2020-01-10 | 2020-05-22 | 北京航天测控技术有限公司 | Thermocouple and synchronous acquisition device for multi-order differential signals thereof |
| CN112711296A (en) * | 2020-12-25 | 2021-04-27 | 北京航天测控技术有限公司 | Calibration system |
| CN113128144A (en) * | 2021-05-07 | 2021-07-16 | 芯华章科技股份有限公司 | Prototype verification system and simulation platform for verifying logic system design |
| CN116148568A (en) * | 2022-12-30 | 2023-05-23 | 北京航天测控技术有限公司 | Analog signal comprehensive measurement device based on FPGA |
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| CN113128144A (en) * | 2021-05-07 | 2021-07-16 | 芯华章科技股份有限公司 | Prototype verification system and simulation platform for verifying logic system design |
| CN116148568A (en) * | 2022-12-30 | 2023-05-23 | 北京航天测控技术有限公司 | Analog signal comprehensive measurement device based on FPGA |
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