CN106298926A - A kind of vertical DMOS transistor and preparation method thereof - Google Patents
A kind of vertical DMOS transistor and preparation method thereof Download PDFInfo
- Publication number
- CN106298926A CN106298926A CN201510303482.2A CN201510303482A CN106298926A CN 106298926 A CN106298926 A CN 106298926A CN 201510303482 A CN201510303482 A CN 201510303482A CN 106298926 A CN106298926 A CN 106298926A
- Authority
- CN
- China
- Prior art keywords
- conduction type
- buried regions
- ion
- injection
- body region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002360 preparation method Methods 0.000 title abstract description 5
- 210000000746 body region Anatomy 0.000 claims abstract description 40
- 239000004065 semiconductor Substances 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 23
- 229920005591 polysilicon Polymers 0.000 claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 claims abstract description 9
- 238000002347 injection Methods 0.000 claims description 55
- 239000007924 injection Substances 0.000 claims description 55
- 238000000034 method Methods 0.000 claims description 18
- 229920002120 photoresistant polymer Polymers 0.000 claims description 17
- 230000008569 process Effects 0.000 claims description 9
- 230000004913 activation Effects 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- 230000005611 electricity Effects 0.000 abstract description 4
- 229940090044 injection Drugs 0.000 description 42
- 238000000407 epitaxy Methods 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 5
- 230000008859 change Effects 0.000 description 5
- 230000035755 proliferation Effects 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 108091006146 Channels Proteins 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005764 inhibitory process Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 241001597008 Nomeidae Species 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000033228 biological regulation Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 150000002926 oxygen Chemical class 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2229/00—Indexing scheme for semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, for details of semiconductor bodies or of electrodes thereof, or for multistep manufacturing processes therefor
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention relates to field of semiconductor fabrication, particularly relate to a kind of vertical DMOS transistor and preparation method thereof, including: the first conductive type semiconductor substrate；It is positioned at the first conductive type epitaxial layer of described first conductive type semiconductor substrate；It is positioned at the gate oxide on described first conductive type epitaxial layer；And, it is positioned at the polysilicon gate on described gate oxide；The first conduction type source region, the second conductivity type body region and the second conduction type buried regions it is provided with among described first conductive type epitaxial layer.The present invention solves the VDMOS problem that source and drain is leaked electricity due to punch through.
Description
Technical field
The present invention relates to field of semiconductor fabrication, particularly relate to a kind of vertical DMOS
Transistor and preparation method thereof.
Background technology
Along with the development of super large-scale integration, create various New Type Power Devices, wherein, most generation
The device of table is exactly vertical DMOS transistor (VDMOSFET, below letter
Claim VDMOS).VDMOS has input impedance height, heat stability is high, switching speed is fast, drive electric current
The advantage such as little, dynamic loss is little, distortion is little, is widely used to various field, such as: electronic speed regulation, inverse
Become device, Switching Power Supply, electrical switch, high-fidelity music center and electric ballast etc..
Traditional plane VDMOS, owing to P/N knot is lightly doped the short of width in district, to such an extent as to snowslide is hit
Wear and not yet occur, and two depletion regions (depletion region that the P/N knot of source-body is formed and extension-body district
P/N tie the depletion region that formed) come in contact in the case of far below breakdown voltage, thus produce source
Leakage electric leakage, i.e. produces punch through (Punch Through), makes device prior to the generation that punctures and loses resistance
Disconnected ability.
Summary of the invention
The present invention solves the VDMOS problem that source and drain is leaked electricity due to punch through, it is provided that a kind of vertical double
LDMOS transistor and preparation method thereof.
The present invention includes:
A kind of vertical DMOS transistor, including:
First conductive type semiconductor substrate；
It is positioned at the first conductive type epitaxial layer of described first conductive type semiconductor substrate；
It is positioned at the gate oxide on described first conductive type epitaxial layer；And,
It is positioned at the polysilicon gate on described gate oxide；
The first conduction type source region, the second conduction type it is provided with among described first conductive type epitaxial layer
Body district and the second conduction type buried regions；
Described second conduction type buried regions is positioned at described first conduction type source region and hangs down in described Semiconductor substrate
Nogata upwards and is positioned at below described second conductivity type body region, described second conduction type buried regions and described the
Two conductivity type body region contact, and described second conduction type buried regions is along described Semiconductor substrate horizontal direction
Length less than described second conductivity type body region along the length of described Semiconductor substrate horizontal direction.
The ion doping concentration of described second conduction type buried regions less than described second conductivity type body region from
Sub-doping content.
Described second conduction type buried regions is more than described first along the length of described Semiconductor substrate horizontal direction
Conduction type source region is along the length of described Semiconductor substrate horizontal direction.
Described second conduction type buried regions thickness is 2～4 μm, and the width of cross section is 2～4 μm.
The thickness of described gate oxide is
A kind of manufacture method of vertical DMOS transistor, including:
The first conductive type epitaxial layer, gate oxide is sequentially formed in the first conductive type semiconductor substrate
And polysilicon gate；
First injection of the ion carrying out the second conduction type forms the second conductivity type body region；
Second injection of the ion carrying out the second conduction type forms the second conduction type buried regions；
Carry out ion to drive in, form raceway groove；
Carry out the ion implanting of the first conduction type, in described second conductivity type body region, form the first conduction
Type source region；
Described second conduction type buried regions is positioned at described first conduction type source region and hangs down in described Semiconductor substrate
Nogata upwards and is positioned at below described second conductivity type body region, described second conduction type buried regions and described the
Two conductivity type body region contact, and described second conduction type buried regions prolongs described Semiconductor substrate horizontal direction
Length prolong the length of described Semiconductor substrate horizontal direction less than described second conductivity type body region.
First injection of the ion carrying out the second conduction type forms the second conductivity type body region；Carry out second to lead
Second injection of the ion of electricity type forms the second conduction type buried regions, specifically includes:
First injection of the ion carrying out described second conduction type forms described second conductivity type body region；
Photoresist is utilized to define the injection zone of described second conduction type buried regions；
Carry out the second injection of the ion of described second conduction type, under described second conductivity type body region
The described second conduction type buried regions of square one-tenth；
Remove described photoresist.
First injection of the ion carrying out the second conduction type forms the second conductivity type body region；Carry out second to lead
Second injection of the ion of electricity type forms the second conduction type buried regions, also includes:
Photoresist is utilized to define the injection zone of described second conduction type buried regions；
Second injection of the ion carrying out described second conduction type forms described second conduction type buried regions；
Remove described photoresist；
Carry out the first injection of the ion of described second conduction type, upper at described second conduction type buried regions
Described second conductivity type body region of square one-tenth.
Described first dosage injected is less than more than the described second dosage injected, the described first energy injected
Described second energy injected.
The described ion implanting carrying out the first conduction type, specifically includes:
Define described first conduction type source region by photoetching process, inject the first conductive type ion, logical
The ion crossing thermal anneal process activation injection forms described first conduction type source region.
Owing to two depletion regions are easiest at body district lower contact, the vertical double diffusion that the embodiment of the present invention provides
Metal oxide semiconductor transistor, adds a part of p-type doped region, i.e. in the lower section in PXing Ti district
P type buried layer so that the vertical depth in PXing Ti district increases, thus adds the distance between two depletion regions,
Add two depletion regions to contact with each other required voltage, solve VDMOS easily produce punch through from
And the problem of source and drain electric leakage, improve the breakdown voltage of VDMOS, enhance the reliability of device.It addition,
Only increase a part of p-type doped region rather than directly the degree of depth in PXing Ti district increased, it is to avoid body district is many
Horizontal proliferation under crystal silicon increases, and causes channel length to increase, and then avoids threshold voltage increase, conducting
Resistance drift, the problem affecting the performance of device.
Accompanying drawing explanation
For the technical scheme being illustrated more clearly that in the embodiment of the present invention, institute in embodiment being described below
The accompanying drawing used is needed to briefly introduce, it should be apparent that, the accompanying drawing in describing below is only the present invention's
Some embodiments, from the point of view of those of ordinary skill in the art, in the premise not paying creative work
Under, it is also possible to other accompanying drawing is obtained according to these accompanying drawings.
Fig. 1 is the cross-sectional view of VDMOS in prior art；
Fig. 2 is the cross-sectional view of VDMOS in the embodiment of the present invention one；
Fig. 3 is the schematic diagram of the manufacture method flow process of VDMOS in the embodiment of the present invention one；
Fig. 4 (a) to Fig. 4 (g) is the structure in each stage in the Making programme of VDMOS in the embodiment of the present invention two
Schematic diagram.
Detailed description of the invention
For convenience's sake, following description employs specific terminology, and this is not restricted
's.Word "left", "right", "up" and "down" represent the direction in the accompanying drawing of reference.Word " to
In " and " outwards " refer respectively to toward and away from description object and the geometric center of specified portions.
Term includes above word, its derivant and the similar word introduced specifically mentioned.
Traditional plane VDMOS is as it is shown in figure 1, by the N-type substrate 1 of high-concentration dopant, lightly doped
N-type extension 2, gate oxide 3, polysilicon gate 4, PXing Ti district 5 and heavily doped N-type source region 6 form.
Inadequate owing to the width in district is lightly doped, two depletion regions in device can be in the situation far below breakdown voltage
Under, at the lower contact in PXing Ti district 5, depletion region exists the strongest internal electric field, upper and lower two depletion regions
After contact, the electronics of source region can be made to flow to drain electrode, thus produce source and drain electric leakage, and then affect the performance of device.
In order to make the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing to this
Bright it is described in further detail, it is clear that described embodiment is only some embodiments of the present invention,
Rather than whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art are not doing
Go out all other embodiments obtained under creative work premise, broadly fall into the scope of protection of the invention.
Concrete, illustrating as a example by N-type channel, the i.e. first conduction type is N-type, the second conduction
Type is p-type, the most merely illustrative, and this invents the embodiment of equally applicable P-type channel.
Embodiment one
As in figure 2 it is shown, a kind of vertical DMOS provided for the embodiment of the present invention one
The cross-sectional view of transistor, including:
First conductive type semiconductor substrate；
It is positioned at the first conductive type epitaxial layer of described first conductive type semiconductor substrate；
It is positioned at the gate oxide on described first conductive type epitaxial layer；And,
It is positioned at the polysilicon gate on described gate oxide；
The first conduction type source region, the second conductive-type it is provided with among described first conductive type epitaxial layer
Xing Ti district and the second conduction type buried regions；
Described second conduction type buried regions is positioned at described first conduction type source region and hangs down in described Semiconductor substrate
Nogata upwards and is positioned at below described second conductivity type body region, described second conduction type buried regions and described the
Two conductivity type body region contact, and described second conduction type buried regions is along described Semiconductor substrate horizontal direction
Length less than described second conductivity type body region along the length of described Semiconductor substrate horizontal direction.
The vertical DMOS transistor that the embodiment of the present invention one provides, in PXing Ti district
Lower section add p type buried layer so that the lightly doped vertical depth of p-type increases, thus adds two consumptions
The to the greatest extent distance between district, adds two depletion regions and contacts with each other required voltage, solve VDMOS and hold
It is easily generated punch through thus the problem of source and drain electric leakage, improves the breakdown voltage of VDMOS, enhance device
The reliability of part.It addition, only increase a part of p-type doped region rather than directly by the degree of depth in PXing Ti district
Increase, it is to avoid the horizontal proliferation under polysilicon of the body district increases, and causes channel length to increase, and then avoids
Threshold voltage increases, conducting resistance drift, the problem affecting the performance of device.
It is preferred that the ion doping concentration of described second conduction type buried regions is less than described second conduction type body
The ion doping concentration in district.After ion implanting forms buried regions and body district, the ion injected need to be driven in,
If the ion doping concentration of buried regions is excessive, through superheating process, Hui Duiti district produces impact, change body district from
Sub-doping content, has influence on the performance of device, and buried regions meeting horizontal proliferation, and then has influence on the raceway groove of centre.
It is preferred that described second conduction type buried regions along the length of described Semiconductor substrate horizontal direction more than institute
State the first conduction type source region length along described Semiconductor substrate horizontal direction.
Specifically, described second conduction type buried regions thickness is 2～4 μm, and the width of cross section is 2～4 μm.
It is preferred that the thickness of described gate oxide isThe thickness of described gate oxide can basis
Being actually needed and be set, thickness should not be the thickest, and most injection ion retardation otherwise can be made at this oxygen
Change in layer, or make the ion of the injection injection degree of depth in N-type epitaxy layer the most shallow；Thickness also should not be the thinnest,
Otherwise cannot play inhibition, and the thinnest meeting of gate oxide thickness makes device in case of high pressures, easily
Breakdown.
The embodiment of the present invention one also provides for the making of a kind of vertical DMOS transistor
Method, as it is shown on figure 3, include:
S11: sequentially form the first conductive type epitaxial layer, grid in the first conductive type semiconductor substrate
Oxide layer and polysilicon gate；
S12: the first injection of the ion carrying out the second conduction type forms the second conductivity type body region；
S13: the second injection of the ion carrying out the second conduction type forms the second conduction type buried regions；
S14: carry out ion and drive in, forms raceway groove；
S15: carry out the ion implanting of the first conduction type, forms the in described second conductivity type body region
One conduction type source region；
Described second conduction type buried regions is positioned at described first conduction type source region and hangs down in described Semiconductor substrate
Nogata upwards and is positioned at below described second conductivity type body region, described second conduction type buried regions and described the
Two conductivity type body region contact, and described second conduction type buried regions prolongs described Semiconductor substrate horizontal direction
Length prolong the length of described Semiconductor substrate horizontal direction less than described second conductivity type body region.
The injection ion of a pair body district of the embodiment of the present invention and buried regions drives in simultaneously so that vertical and horizontal all produce
Give birth to diffusion, especially horizontal proliferation so that a part for body district and buried regions extends to below polysilicon gate,
And then define raceway groove, simultaneously as longitudinal diffusion so that body district lower part contacts with the upper part of buried regions
Even overlapping, play the effect stoping depletion region contact.
Gate oxide not only acts as isolation polysilicon gate and the effect of N-type epitaxy layer, is also injecting ion
During play inhibition, inject ion when entering back into N-type epitaxy layer by gate oxide, ion
Injection direction will be random, therefore can effectively control the range of ion.
It is preferred that the described first dosage injected is more than the described second dosage injected, described first injection
Energy is less than the described second energy injected.
The ion doping concentration of body district and buried regions is by the dosage control injected, and the degree of depth injected is by energy control
System, the energy of injection is the biggest, enters the degree of depth in N-type epitaxy layer the deepest.
It is preferred that the first injection carrying out the ion of the second conduction type forms the second conductivity type body region；Enter
Second injection of the ion of row the second conduction type forms the second conduction type buried regions, specifically includes:
The first step: the first injection of the ion carrying out described second conduction type forms described second conduction type
Body district；
Second step: utilize photoresist to define the injection zone of described second conduction type buried regions；
3rd step: carry out the second injection of the ion of described second conduction type, at described second conduction type
The formed below described second conduction type buried regions in body district；
4th step: remove described photoresist.
Injecting body district and can not define its injection zone with photoresist, the injection zone in body district is at polysilicon gate
In the epitaxial layer of both sides, pole, the p-type ion being injected in polysilicon gate is neutralized, and polysilicon gate plays
The effect stopped, will not be injected into p-type ion in epitaxial layer below, and due to polysilicon gate extremely
N-type heavy doping, and to be p-type be lightly doped in body district, p-type is injected the impact on polysilicon gate and can be ignored.
Therefore, utilize polysilicon gate to replace the injection zone in photoresist definition PXing Ti district, can walk with Simplified flowsheet
Suddenly, production cost is saved.
Further, the order that body district and buried regions inject can be exchanged.Described carry out the second conduction type from
First injection of son forms the second conductivity type body region；Carry out the second injection shape of the ion of the second conduction type
Become the second conduction type buried regions, specifically include:
One: utilize photoresist to define the injection zone of described second conduction type buried regions；
Two: the second injection of the ion carrying out described second conduction type forms described second conduction type and buries
Layer；
Three: remove described photoresist；
Four: carry out the first injection of the ion of described second conduction type, at described second conduction type buried regions
Top form described second conductivity type body region.
Carry out the ion implanting of the first conduction type described in it is preferred that, specifically include:
Define described first conduction type source region by photoetching process, inject the first conductive type ion, logical
The ion crossing thermal anneal process activation injection forms described first conduction type source region.
Embodiment two
Below as a example by N-type semiconductor, describe technical scheme in detail.As shown in Fig. 4 (a)～4 (g),
The structural representation in each stage in the Making programme of VDMOS disclosed in the embodiment of the present invention two.
Such as Fig. 4 (a), N-type substrate 1 generates N-type epitaxy layer 2, the thickness of the N-type epitaxy layer 2 of formation
Degree is 30～100 μm, utilizes thermal oxidation technology manufacturing gate oxide layers 3 in N-type epitaxy layer 2, and thickness is
Such as Fig. 4 (b), on gate oxide 3, form polysilicon gate 4.
Specifically, utilizing low-pressure chemical vapor deposition to generate polysilicon layer on gate oxide 3, thickness isPolysilicon layer is carried out chemical wet etching, forms the polysilicon gate that width is 0.25～1.0 μm
4。
Such as Fig. 4 (c), implanting p-type ion is as body district 5.Injection ion is boron (symbol of element B), dosage
It is 1 × 1013～1 × 1014Individual ion/cm2, energy is 80keV～120keV, in the both sides of polysilicon gate 4
N-type epitaxy layer 2 in formed PXing Ti district 5.
Carry out second time p-type ion implanting, form buried regions 7, such as Fig. 4 (e).
Specifically, such as Fig. 4 (d), coating photoresist 8, utilize reticle to etch photoresist 8, define buried regions 7
Injection zone, injects boron ion, and the dosage of injection is 1 × 1012～1 × 1013Individual ion/cm2, energy is
100keV～200keV so that below body district, the subregion of the left and right sides of polysilicon gate forms and bury
Layer 7.Finally remove photoresist 8.
Such as Fig. 4 (f), p-type ion is driven in.Driving in temperature is 900～1200 DEG C, the time be 50～
200min, meanwhile, is passed through nitrogen (N2), flow is 8～12L/min, is passed through oxygen (O2), flow is
0.04～0.2L/min.Eventually forming PXing Ti district, thickness is 2～5 μm；Forming p type buried layer 7, thickness is
2～4 μm, the width of cross section is 2～4 μm.
Such as Fig. 4 (g), PXing Ti district forms N-type source region 6.By lithographic etch process, define N
Type source region 6, injection ion is arsenic (As), and implantation dosage is 1 × 1015～1 × 1016Individual ion/cm2, energy
For 50keV～120keV, carry out thermal annealing afterwards and activate and inject ion, the temperature of thermal annealing be 800～
950 DEG C, the time is 30～60min.
After completing, further growth dielectric layer, formed contact hole and front metal, carry out thinning back side with
And back metal sputter etc., these are all traditional handicrafts, do not repeat at this.
Although preferred embodiments of the present invention have been described, but those skilled in the art once know base
This creativeness concept, then can make other change and amendment to these embodiments.So, appended right is wanted
Ask and be intended to be construed to include preferred embodiment and fall into all changes and the amendment of the scope of the invention.
Obviously, those skilled in the art can carry out various change and modification without deviating from this to the present invention
Bright spirit and scope.So, if the present invention these amendment and modification belong to the claims in the present invention and
Within the scope of its equivalent technologies, then the present invention is also intended to comprise these change and modification.
Claims (10)
1. a vertical DMOS transistor, it is characterised in that including:
First conductive type semiconductor substrate；
It is positioned at the first conductive type epitaxial layer of described first conductive type semiconductor substrate；
It is positioned at the gate oxide on described first conductive type epitaxial layer；And,
It is positioned at the polysilicon gate on described gate oxide；
The first conduction type source region, the second conduction type it is provided with among described first conductive type epitaxial layer
Body district and the second conduction type buried regions；
Described second conduction type buried regions is positioned at described first conduction type source region and hangs down in described Semiconductor substrate
Nogata upwards and is positioned at below described second conductivity type body region, described second conduction type buried regions and described the
Two conductivity type body region contact, and described second conduction type buried regions is along described Semiconductor substrate horizontal direction
Length less than described second conductivity type body region along the length of described Semiconductor substrate horizontal direction.
2. transistor as claimed in claim 1, it is characterised in that described second conduction type buried regions
Ion doping concentration is less than the ion doping concentration of described second conductivity type body region.
3. transistor as claimed in claim 1, it is characterised in that described second conduction type buried regions edge
The length of described Semiconductor substrate horizontal direction serves as a contrast along described quasiconductor more than described first conduction type source region
The length of end horizontal direction.
4. transistor as claimed in claim 1, it is characterised in that described second conduction type buried regions is thick
Degree is 2～4 μm, and the width of cross section is 2～4 μm.
5. transistor as claimed in claim 1, it is characterised in that the thickness of described gate oxide is
6. the manufacture method of a vertical DMOS transistor, it is characterised in that
Described method includes:
The first conductive type epitaxial layer, gate oxide is sequentially formed in the first conductive type semiconductor substrate
And polysilicon gate；
First injection of the ion carrying out the second conduction type forms the second conductivity type body region；
Second injection of the ion carrying out the second conduction type forms the second conduction type buried regions；
Carry out ion to drive in, form raceway groove；
Carry out the ion implanting of the first conduction type, in described second conductivity type body region, form the first conduction
Type source region；
Described second conduction type buried regions is positioned at described first conduction type source region and hangs down in described Semiconductor substrate
Nogata upwards and is positioned at below described second conductivity type body region, described second conduction type buried regions and described the
Two conductivity type body region contact, and described second conduction type buried regions prolongs described Semiconductor substrate horizontal direction
Length prolong the length of described Semiconductor substrate horizontal direction less than described second conductivity type body region.
7. manufacture method as claimed in claim 6, it is characterised in that carry out the second conduction type from
First injection of son forms the second conductivity type body region；Carry out the second injection shape of the ion of the second conduction type
Become the second conduction type buried regions, specifically include:
First injection of the ion carrying out described second conduction type forms described second conductivity type body region；
Photoresist is utilized to define the injection zone of described second conduction type buried regions；
Carry out the second injection of the ion of described second conduction type, under described second conductivity type body region
The described second conduction type buried regions of square one-tenth；
Remove described photoresist.
8. manufacture method as claimed in claim 6, it is characterised in that carry out the second conduction type from
First injection of son forms the second conductivity type body region；Carry out the second injection shape of the ion of the second conduction type
Become the second conduction type buried regions, also include:
Photoresist is utilized to define the injection zone of described second conduction type buried regions；
Second injection of the ion carrying out described second conduction type forms described second conduction type buried regions；
Remove described photoresist；
Carry out the first injection of the ion of described second conduction type, upper at described second conduction type buried regions
Described second conductivity type body region of square one-tenth.
9. method as claimed in claim 6, it is characterised in that
Described first dosage injected is less than more than the described second dosage injected, the described first energy injected
Described second energy injected.
10. method as claimed in claim 6, it is characterised in that described in carry out the first conduction type from
Son injects, and specifically includes:
Define described first conduction type source region by photoetching process, inject the first conductive type ion, logical
The ion crossing thermal anneal process activation injection forms described first conduction type source region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510303482.2A CN106298926A (en) | 2015-06-05 | 2015-06-05 | A kind of vertical DMOS transistor and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510303482.2A CN106298926A (en) | 2015-06-05 | 2015-06-05 | A kind of vertical DMOS transistor and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106298926A true CN106298926A (en) | 2017-01-04 |
Family
ID=57656663
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510303482.2A Pending CN106298926A (en) | 2015-06-05 | 2015-06-05 | A kind of vertical DMOS transistor and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106298926A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107958937A (en) * | 2017-11-29 | 2018-04-24 | 贵州大学 | A kind of power MOSFET device and its manufacture method based on retrograde well technique |
| CN109494253A (en) * | 2017-09-11 | 2019-03-19 | 三星电子株式会社 | Vertical field-effect transistor and semiconductor devices including it |
| CN110221547A (en) * | 2018-03-01 | 2019-09-10 | Dialog半导体（英国）有限公司 | More level gates of transistor device control |
| CN115939178A (en) * | 2023-03-10 | 2023-04-07 | 广东芯聚能半导体有限公司 | Semiconductor structure and preparation method thereof |
| CN116646401A (en) * | 2023-07-19 | 2023-08-25 | 成都蓉矽半导体有限公司 | Silicon carbide heterojunction cascode MOSFET device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090057713A1 (en) * | 2007-08-31 | 2009-03-05 | Infineon Technologies Austria Ag | Semiconductor device with a semiconductor body |
| CN102208439A (en) * | 2010-03-30 | 2011-10-05 | 新电元工业株式会社 | Semiconductor device and method for manufacturing the semiconductor device |
| CN103503146A (en) * | 2011-06-07 | 2014-01-08 | 住友电气工业株式会社 | Semiconductor device |
-
2015
- 2015-06-05 CN CN201510303482.2A patent/CN106298926A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090057713A1 (en) * | 2007-08-31 | 2009-03-05 | Infineon Technologies Austria Ag | Semiconductor device with a semiconductor body |
| CN102208439A (en) * | 2010-03-30 | 2011-10-05 | 新电元工业株式会社 | Semiconductor device and method for manufacturing the semiconductor device |
| CN103503146A (en) * | 2011-06-07 | 2014-01-08 | 住友电气工业株式会社 | Semiconductor device |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109494253A (en) * | 2017-09-11 | 2019-03-19 | 三星电子株式会社 | Vertical field-effect transistor and semiconductor devices including it |
| US10944003B2 (en) | 2017-09-11 | 2021-03-09 | Samsung Electronics Co., Ltd. | Vertical field effect transistor and semiconductor device including the same |
| CN109494253B (en) * | 2017-09-11 | 2021-04-06 | 三星电子株式会社 | Vertical field effect transistor and semiconductor device including the same |
| CN107958937A (en) * | 2017-11-29 | 2018-04-24 | 贵州大学 | A kind of power MOSFET device and its manufacture method based on retrograde well technique |
| CN110221547A (en) * | 2018-03-01 | 2019-09-10 | Dialog半导体（英国）有限公司 | More level gates of transistor device control |
| CN110221547B (en) * | 2018-03-01 | 2024-06-07 | Dialog半导体（英国）有限公司 | Multi-level gate control for transistor devices |
| CN115939178A (en) * | 2023-03-10 | 2023-04-07 | 广东芯聚能半导体有限公司 | Semiconductor structure and preparation method thereof |
| CN116646401A (en) * | 2023-07-19 | 2023-08-25 | 成都蓉矽半导体有限公司 | Silicon carbide heterojunction cascode MOSFET device |
| CN116646401B (en) * | 2023-07-19 | 2024-01-23 | 成都蓉矽半导体有限公司 | Silicon carbide heterojunction cascode MOSFET device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5136674B2 (en) | Semiconductor device and manufacturing method thereof | |
| CN106298926A (en) | A kind of vertical DMOS transistor and preparation method thereof | |
| US9196702B2 (en) | Power semiconductor device and method of manufacturing the same | |
| CN102376762B (en) | Super junction LDMOS(Laterally Diffused Metal Oxide Semiconductor) device and manufacturing method thereof | |
| CN102130012B (en) | LDD, LDS and buffer layer integrated manufacturing method for SOI super-junction LDMOS device | |
| CN103579353B (en) | Half hyperconjugation VDMOS of buried regions assisted by a kind of P of having type | |
| US9741844B2 (en) | Lateral double-diffused MOS transistor having deeper drain region than source region | |
| CN102751332B (en) | Depletion type power semiconductor device and manufacturing method thereof | |
| KR101699585B1 (en) | High voltage semiconductor device and method of manufacturing the same | |
| CN102184944A (en) | Junction terminal structure of lateral power device | |
| CN102760754A (en) | Depletion type VDMOS (Vertical Double-diffusion Metal Oxide Semiconductor) and manufacturing method thereof | |
| CN103779414A (en) | Semiconductor device and method for manufacturing the same | |
| CN102709190B (en) | LDMOS (Laterally Diffused Metal Oxide Semiconductor) field effect transistor and manufacturing method thereof | |
| CN208028069U (en) | Novel two-sided step buried oxide SOI LDMOS with buried structure | |
| CN110047930A (en) | VDMOS device | |
| CN102637744B (en) | Signal operation instruction (SOI) transverse super junction power metal oxide semiconductor field effect transistor (MOSFET) device | |
| CN104201203B (en) | High withstand voltage LDMOS device and manufacture method thereof | |
| CN102769038B (en) | Latch-up resisting N-type SOI laterally diffused metal oxide semiconductor | |
| KR20110078861A (en) | Lateral double diffused metal oxide semiconductor | |
| CN104810288A (en) | Manufacturing method of double-diffusion metal-oxide-semiconductor (DMOS) device | |
| CN202736927U (en) | Depletion type power semiconductor device | |
| CN104037206A (en) | Super-junction device and manufacturing method thereof | |
| CN103779404B (en) | P Channeling implantation enhanced efficiency insulated gate bipolar transistor | |
| KR102088548B1 (en) | High voltage semiconductor device | |
| JP6430650B2 (en) | Horizontal insulated gate bipolar transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170104 |