CN202736927U - Depletion type power semiconductor device - Google Patents
Depletion type power semiconductor device Download PDFInfo
- Publication number
- CN202736927U CN202736927U CN 201220355522 CN201220355522U CN202736927U CN 202736927 U CN202736927 U CN 202736927U CN 201220355522 CN201220355522 CN 201220355522 CN 201220355522 U CN201220355522 U CN 201220355522U CN 202736927 U CN202736927 U CN 202736927U
- Authority
- CN
- China
- Prior art keywords
- well region
- power semiconductor
- gate electrode
- type power
- epitaxial loayer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn - After Issue
Links
Images
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The utility model provides a depletion type power semiconductor device. The depletion type power semiconductor device comprises a semiconductor substrate, an epitaxial layer of a first doped type located on the semiconductor substrate, well regions of a second doped type formed in the epitaxial layer, and a gate medium layer and a gate electrode which are successively located on the epitaxial layer, wherein the second doped type is opposite to the first doped type, surfaces of the well regions have inversion layers of the first doped type, the well regions transversely extend to a position below the gate electrode with a distance of 0.75*Xj+b, Xj is junction depth of the well region, and b is greater than or equal to -2mum and smaller than or equal to 5mum. The depletion type power semiconductor device has advantages of simple technology process, low cost and good controllability of threshold voltage.
Description
Technical field
The utility model relates to a kind of depletion type power semiconductor.
Background technology
Mosfet transistor, igbt transistor constant power semiconductor device have the advantages such as high withstand voltage, large electric current, low on-resistance and are widely used in middle and high power field because of it.Depletion type power semiconductor (such as MOSFET, IGBT etc.) is for often opening device, its grid G, source S (or emitter E) termination zero potential break-over of device during use, the rising of source S after the conducting (or emitter E) terminal potential (VS (E)〉0), so that the voltage VGS (E)＜0 between grid and the source electrode (or emitter).When VGS (E) (is S for MOSFET, E for IGBT)＜during VTH, device automatically shuts down, thereby has simplified the grid driving, can effectively reduce system power dissipation, be widely used in solid-state relay, linear amplifier, inverter, constant-current source, the power circuit.
In the prior art, traditional depletion type power semiconductor or threshold voltage poor controllability, flexible design degree are little; Manufacturing process is complicated; Preparation needs the extra mask plate that increases, and increases chip cost; Device reliability reduces, and threshold voltage shift is serious.
The patent No. is the formation method that discloses a kind of depletion device in 5,021,356 the american documentation literature, and it carries out P type ion light dope (p-) to polysilicon gate, develops the depletion type P channel mosfet transistor of threshold voltage about+0.25V.But the method mainly reaches the purpose of threshold voltage adjustments by the selective doping to polysilicon, so the threshold voltage designs flexibility ratio is little.
The patent No. is 4,786,611 american documentation literature reaches threshold voltage adjustments to the diffusing, doping of polysilicon gate by the insoluble metal silicide purpose, but the manufacturing process more complicated of the method, the poor controllability of threshold voltage.
The patent No. is 3,667,115 american documentation literature by in channel region growth oxide layer, utilize suction " boron " row " phosphorus " characteristic of oxide layer to make the raceway groove transoid, produce depletion type MOS FET transistor, but the transoid degree limited and be difficult to control, the threshold voltage poor controllability, the flexible design degree is little.
To be 5,907,777 american documentation literature mix and produce depletion type MOS FET by gate medium being carried out mobile ion the patent No., but device reliability is low, threshold voltage shift is large.
Also having a kind of method in the prior art is to develop depletion mode transistor by channel region is carried out the transoid Implantation, because it only carries out selectivity transoid Implantation to channel region, therefore needs the extra mask plate that increases, and has increased cost.
The utility model content
The technical problems to be solved in the utility model provides a kind of depletion type power semiconductor, and manufacturing process is simple, cost is low, the threshold voltage controllability is good.
For solving the problems of the technologies described above, the utility model provides a kind of depletion type power semiconductor, comprising:
Semiconductor substrate;
Be positioned at the epitaxial loayer of the first doping type on the described Semiconductor substrate;
Be formed at the well region of the second doping type in the described epitaxial loayer, described the second doping type is opposite with described the first doping type, and the surface of described well region has the inversion layer of the first doping type;
Be positioned at successively gate dielectric layer and gate electrode on the described epitaxial loayer, the distance that described well region extends laterally to described gate electrode below is 0.75 * Xj+b, and wherein Xj is the junction depth of described well region ,-2 μ m≤b≤5 μ m.
Alternatively, the span of described b is: 0 μ m≤b≤1 μ m.
Alternatively, to extend laterally to the distance of described gate electrode below be 1.5 μ m ~ 5.5 μ m to described well region.
Alternatively, to extend laterally to the distance of described gate electrode below be 2.25 μ m ~ 4.75 μ m to described well region.
Alternatively, the span of the threshold V T H of described depletion type power semiconductor is :-10V≤VTH≤10V.
Alternatively, described depletion type power semiconductor is the n channel device, and the span of its threshold V T H is :-5V≤VTH≤0V.
Alternatively, described depletion type power semiconductor is the p channel device, and the span of its threshold V T H is: 0V≤VTH≤5V.
Alternatively, described depletion type power semiconductor is the VDMOS device, described Semiconductor substrate is the first doping type, and described gate dielectric layer and gate electrode cover the epitaxial loayer between the adjacent well region, also is formed with the source region of the first doping type in the well region of described gate electrode both sides.
Alternatively, described Semiconductor substrate comprises nucleus and is positioned at the terminal area of described nucleus periphery, is formed with the pressure ring of the second doping type in the epitaxial loayer of described terminal area; Be formed with field oxide on the epi-layer surface of described terminal area; Be filled with oxide layer between described pressure ring top, the opposite field oxide layer; Be coated with dielectric layer on described field oxide, the oxide layer, be formed with through hole in the described dielectric layer, Metal field plate links to each other with described pressure ring by this through hole.
Alternatively, be formed with the protection Zener diode of one or more series connection in the described dielectric layer, its negative electrode and described gate electrode are electrically connected, and its anode and described source region are electrically connected.
Alternatively, described depletion type power semiconductor is the IGBT device, described Semiconductor substrate is the first doping type, described Semiconductor substrate face also is formed with the collector region of the second doping type, described gate dielectric layer and gate electrode cover the epitaxial loayer between the adjacent well region, also are formed with the emitter region of the first doping type in the well region of described gate electrode both sides.
Alternatively, described depletion type power semiconductor is the LDMOS device, described Semiconductor substrate is the second doping type, be formed with the source region of the first doping type in the described well region, also be formed with the drain region with described well region the first doping type arranged side by side in the described epitaxial loayer, also be formed with field oxide on the epitaxial loayer between described drain region and the well region, described gate dielectric layer and gate electrode cover the epitaxial loayer between described field oxide and the source region.
Alternatively, described depletion type power semiconductor is the LIGBT device, described Semiconductor substrate is the second doping type, the upper surface of described Semiconductor substrate is formed with the buried regions of the first doping type, described epitaxial loayer is positioned on the described buried regions, be formed with the emitter region of the first doping type in the described well region, also be formed with the current collection end well region with described well region the first doping type arranged side by side in the described epitaxial loayer, be formed with the collector region of the second doping type in the described current collection end well region, also be formed with field oxide on the epitaxial loayer between described collector region and the well region, described gate dielectric layer and gate electrode cover the epitaxial loayer between described field oxide and the emitter region.
Compared with prior art, the utlity model has following advantage:
In the depletion type power semiconductor of the utility model embodiment, the surface of well region has the inversion layer opposite with the well region doping type, and has deviation value b between the etch mask version of the injection mask plate of well region and described gate electrode, thereby can be by regulating this deviation value b adjustment channel length that becomes more meticulous, and then adjusting threshold voltage more effectively, improved the flexibility ratio of design.
The technical scheme manufacturing process of the utility model embodiment is simple, can be compatible with the enhanced power semiconductor device technology, can be applicable to multiple type of device, such as MOSFET device, IGBT device etc.
In the technical scheme of the utility model embodiment, the ion implantation process that forms inversion layer can adopt and before be formed with the mask plate that adopt in the source region, need not additionally to increase mask plate, is conducive to reduce cost.
Description of drawings
Fig. 1 is the schematic flow sheet of manufacture method of the depletion type power semiconductor of the utility model embodiment;
Fig. 2 to Fig. 5 is device profile structural representation corresponding to each step in the manufacture method of depletion type VDMOS device of the utility model embodiment;
Fig. 6 is the cross-sectional view of the IGBT device of the utility model embodiment;
Fig. 7 is the cross-sectional view of the LDMOS device of the utility model embodiment;
Fig. 8 is the cross-sectional view of the LIGBT device of the utility model embodiment;
Fig. 9 is the cross-sectional view of the another kind of VDMOS device of the utility model embodiment;
Figure 10 is the cellular domain of the described VDMOS device of Fig. 9;
Figure 11 is the puncture curve of the described VDMOS device of Fig. 9;
Figure 12 is the current distributing figure of the described VDMOS device of Fig. 9;
Figure 13 is the raceway groove moulding close up view of the described VDMOS device of Fig. 9 when deviant b=0;
Figure 14 is the raceway groove moulding close up view of the described VDMOS device of Fig. 9 when deviant b=1.6 μ m;
Figure 15 is the Impurity Distribution curve of the described VDMOS device of Fig. 9;
Figure 16 is the threshold voltage curve of the described VDMOS device of Fig. 9.
Embodiment
The utility model is described in further detail below in conjunction with specific embodiments and the drawings, but should not limit protection range of the present utility model with this.
Fig. 1 shows the schematic flow sheet of the depletion type power semiconductor manufacture method of the present embodiment, may further comprise the steps:
Step S11 provides Semiconductor substrate;
Step S12 is at the epitaxial loayer of described Semiconductor substrate formation the first doping type;
Step S13 uses well region to inject mask plate described epitaxial loayer is carried out Implantation, and the ionic type of injection is second doping type opposite with described the first doping type, to form the well region of the second doping type in described epitaxial loayer;
Step S14 carries out Implantation to described epitaxial loayer, and the ionic type of injection is the first doping type, forms the inversion layer with first doping type with the surface at described well region;
Step S15 forms gate dielectric layer and gate electrode layer successively on the surface of described epitaxial loayer;
Step S16 uses gate electrode etch mask version that described gate electrode layer is carried out etching to form gate electrode, has deviation value b between the etch mask version of described well region injection mask plate and described gate electrode.
Below in conjunction with Fig. 2 to Fig. 5 each step in the VDMOS device making method is elaborated.Need to prove, as a nonrestrictive example, the first doping type is N-shaped in this article, and the second doping type is p-type.But it will be appreciated by those skilled in the art that in actual applications, the first doping type also can be p-type, and correspondingly, the second doping type is N-shaped.
At first with reference to figure 2, at first provide Semiconductor substrate 11, it can be substrate commonly used in the field of semiconductor manufacture such as silicon substrate, silicon-Germanium substrate.In the present embodiment, the silicon substrate that Semiconductor substrate 11 is mixed for n+.
The epitaxial loayer 12 that mixes at the upper surface growth n-of Semiconductor substrate 11 afterwards.And at the superficial growth field oxide (not shown) of epitaxial loayer 12, and define active area (the epitaxial loayer zone shown in Fig. 2 all is active area) by photoetching and etching.In addition, can also form oxide layer 100 on the active area surface partly of epitaxial loayer 12.Epitaxial loayer 12 can be the semiconductor layer of the formed doping of conventional epitaxial growth, and super junction (SJ, the Super Junction) structure that also can adopt p/n to replace is used for reducing conducting resistance, further improves device performance.
Adopt afterwards well region to inject 101 pairs of epitaxial loayers of mask plate 12 and carry out photoetching, Implantation, thereby in epitaxial loayer 12, form p-type well region 13.Ion can be boron ion or other p-type ions in the present embodiment, and the dosage of ion is 5e12 ~ 3e14cm
-2, be preferably 2e13 ~ 7e13cm
-2, its concrete value can be determined according to the threshold voltage of device.
Next with reference to figure 3, epitaxial loayer 12 is carried out Implantation, the ion type is opposite and identical with the doping type of epitaxial loayer 12 with the doping type of well region 3, thereby forms the inversion layer 14A that N-shaped mixes on the surface of well region 13.In the present embodiment, forming the mask plate 102 that adopts in the ion implantation process of inversion layer 14A can be the active area mask plate, thereby need not additionally to increase mask plate.In the present embodiment, the ionic type that this step is injected is N-shaped, and the dosage of Implantation is 1e12 ~ 5e13cm
-2, be preferably 5e12 ~ 1e13cm
-2
Adopt after the injection of active area mask plate, the doping content of epitaxial loayer 12 surf zones beyond the well region 13 is strengthened, and forms the accumulation layer 14B that doping content is higher than epitaxial loayer 12.The oxide layer 100 on epitaxial loayer 12 surfaces can be removed afterwards.
Through after the Implantation, the doping content of accumulation layer 14B is strengthened, so that have larger concentration gradient between accumulation layer 14B and the epitaxial loayer 12, for example in one embodiment, the concentration of accumulation layer 14B is 1E17cm
-3, and epitaxial layer concentration is 1E14cm
-3, the two differs 3 orders of magnitude.
Next with reference to figure 4, form successively gate dielectric layer 15 and gate electrode layer 16 on the surface of epitaxial loayer 12, use afterwards 103 pairs of gate electrode layers 16 of gate electrode etch mask version and gate dielectric layer 15 to carry out etching, thereby form gate electrode G and be positioned at gate dielectric layer 15 under it.Wherein, gate electrode G and the epitaxial loayer 12 between the adjacent well region 13 of gate dielectric layer 15 coverings under it.In the present embodiment, the material of gate dielectric layer 15 is silica, and the material of gate electrode layer 16 is the polysilicon of polysilicon or doping.
Wherein, well region injects between mask plate 101 and the gate electrode etch mask version 103 and has deviation value b.Particularly, it is not to align that well region injects between mask plate 101 defined window edges and the gate electrode etch mask version 103 defined window edges, but has deviation value b.The span of deviation value b is-2 μ m≤b≤5 μ m, is preferably 0 μ m≤b≤1 μ m, and the concrete value of deviation value b can be determined according to the threshold voltage of device.Because injecting between mask plate 101 and the gate electrode etch mask version 103, well region has deviation value b, thereby can regulate the distance that well region 13 extends to gate electrode G below by regulating deviation value b, thereby become more meticulous the adjustment channel length, and then adjusting threshold voltage more effectively, improve the flexibility ratio of design, can satisfy various application demands.
Prior art typically uses gate electrode etch mask version 103 etchings and forms after the gate electrode G, carry out the autoregistration Implantation take gate electrode G as mask and form well region 13, thereby the distance that well region 13 extends to gate electrode G below depends on ion implantation technology and annealing process subsequently, formula rule of thumb, the distance that well region 13 extends laterally to gate electrode G below is 0.75 * Xj, and wherein Xj is the junction depth of well region.But, in the present embodiment, well region 13 usefulness well regions inject mask plate 101 and form, has deviation value b between itself and the gate electrode etch mask version 103, thereby the distance that well region 13 extends laterally to gate electrode G below is 0.75 * Xj+b, value according to deviation value b is different, and it can be greater than or less than 0.75 traditional * Xj.
For example, in the prior art, the distance range that well region 13 extends laterally to gate electrode G below is 0.75 * Xj=1.5 μ m ~ 4.5 μ m, and better scope is 2.25 μ m ~ 3.75 μ m.And in the present embodiment, the value of deviation value b is-2 μ m≤b≤5 μ m, is preferably 0 μ m≤b≤1 μ m, and is corresponding, and the distance that well region 13 extends to gate electrode G below is 0.75 * Xj+b=1.5 μ m ~ 5.5 μ m, and better scope is 2.25 μ m ~ 4.75 μ m.
Afterwards with reference to figure 5, the well region 13 of gate electrode G both sides is carried out Implantation, the ionic type of injection is N-shaped, thereby forms source region 17 in well region 13, this ion implantation process can be that the autoregistration take gate electrode G as mask is injected.In addition, can also in well region 13, form the well region contact zone 18 identical with well region 13 doping types by Implantation.Next can be at whole surface deposition dielectric layer 19, and this dielectric layer 19 carried out etching to form contact hole, expose gate electrode G and source region 17, can in contact hole, fill afterwards metal (for example the mode by sputter forms aluminium) thereby formation source electrode S.Next can also form drain electrode 1D in the bottom surface of Semiconductor substrate 11.
So far, the VDMOS device of the present embodiment forms, and its structure mainly comprises as shown in Figure 5: the Semiconductor substrate 11 that n+ mixes; Be positioned at the epitaxial loayer 12 that the n-on the Semiconductor substrate 11 mixes; Be positioned at the well region 13 of the p doping of epitaxial loayer 12, the surface of well region 13 has the inversion layer 14A that N-shaped mixes; The surface of the epitaxial loayer 12 beyond the well region 13 has the accumulation layer 14B that concentration is deepened; Gate dielectric layer 15 and gate electrode G cover the epitaxial loayer 12 between the adjacent well region 13; The contact zone 18 that the source region 17 that n+ mixes and p+ mix is arranged in the well region 13 of gate electrode G both sides.Wherein, has deviation value b between the injection mask plate 101 of well region 13 and the gate electrode etch mask version 103.Wherein, the distance that well region 13 extends laterally to gate electrode G below is 0.75 * Xj+b, and wherein Xj is the junction depth of described well region, for example can be 1.5 μ m ~ 5.5 μ m, 2.25 μ m ~ 4.75 μ m preferably, the span of b is-2 μ m≤b≤5 μ m, preferably: 0 μ m≤b≤1 μ m.(height of doping content is described as follows: n+〉n〉n-, p+〉p〉p-, lower same)
Fig. 6 shows the profile of the IGBT device that the present embodiment provides, and comprising: the Semiconductor substrate 61 that n+ mixes; Be positioned at the epitaxial loayer 62 that the n-on the Semiconductor substrate 61 mixes; Be arranged in the well region 63 of the p doping of epitaxial loayer 62; The surface of well region 63 has the inversion layer 64A that N-shaped mixes; The surface of the epitaxial loayer 62 beyond the well region 63 has the accumulation layer 64B that concentration is deepened; Be formed with the emitter region 67 of n+ doping and the contact zone 68 that p+ mixes in the well region 63; Stacking gate dielectric layer 65 and gate electrode G cover the epitaxial loayer 62 between the adjacent well region 63, and emitter region 67 is positioned at the both sides of gate electrode G; Emitter E with emitter region 67 electric connections; Dielectric layer 69 around emitter E; Be formed at the collector region 610A that the p-type on Semiconductor substrate 61 bottom surfaces is mixed; The collector electrode C that contacts with collector region 610A electricity.Wherein, the mask plate that adopts in well region 63 forming processes is that well region injects mask plate 601, the mask plate that adopts in the inversion layer 64A forming process is active area mask plate 602, and the mask plate that adopts in the gate electrode G forming process is gate electrode etch mask version 603.Wherein, the distance that well region 63 extends laterally to gate electrode G below is 0.75 * Xj+b, and wherein Xj is the junction depth of described well region, for example can be 1.5 μ m ~ 5.5 μ m, 2.25 μ m ~ 4.75 μ m preferably, the span of b is-2 μ m≤b≤5 μ m, preferably: 0 μ m≤b≤1 μ m.
The formation method of IGBT device shown in Figure 6 and the formation method of aforementioned VDMOS device are similar, difference mainly is the forming process that the forming process in source region is replaced with emitter region 67, and the collector region 610A that forms the p-type doping in the bottom surface of Semiconductor substrate 61, collector region 610A can form by the Implantation by the back side after the attenuate of the bottom surface of Semiconductor substrate 61.With VDMOS device forming process in the same manner, well region injects between mask plate 601 and the gate electrode etch mask version 603 and has deviation value b.
Fig. 7 shows the cross-sectional view of the LDMOS device that the present embodiment provides, and comprising: the Semiconductor substrate 71 that p+ mixes; Be positioned at the epitaxial loayer 72 that the n-on the Semiconductor substrate 71 mixes; Be formed at the field oxide 72A ' on the epitaxial loayer 72, the zone beyond the field oxide 72A ' overlay area is active area 2A; Be arranged in the well region 73 of the p doping of epitaxial loayer 72; Be arranged in the drain terminal buffering area 73A of the n doping of epitaxial loayer 72; The surface of well region 73 has the inversion layer 74A that N-shaped mixes; Epitaxial loayer 72 beyond the well region 73 and the surface of drain terminal well region 73A have the accumulation layer 74B that concentration is deepened; Be formed with the source region 77 of n+ doping and the contact zone 78 that p+ mixes in the well region 73; Be formed with n+ impure drain region 77A among the drain terminal well region 73A, drain region 77A can form in same ion implantation process together with source region 77; Stacking gate dielectric layer 75 and gate electrode G cover the epitaxial loayer 72 between field oxide 72A ' and the source region 77; Source electrode S with source region 77 electric connections; Dielectric layer 79 around source electrode S; Drain electrode D with drain region 77A electrical contact; Be formed at the underlayer electrode Sub on Semiconductor substrate 71 bottom surfaces.Wherein, the mask plate that adopts in well region 73 forming processes is that well region injects mask plate 701, the mask plate that adopts in the inversion layer 74A forming process is active area mask plate 702, and the mask plate that adopts in the gate electrode G forming process is gate electrode etch mask version 703.Wherein, the distance that well region 73 extends laterally to gate electrode G below is 0.75 * Xj+b, and wherein Xj is the junction depth of described well region, for example can be 1.5 μ m ~ 5.5 μ m, 2.25 μ m ~ 4.75 μ m preferably, the span of b is-2 μ m≤b≤5 μ m, preferably: 0 μ m≤b≤1 μ m.
The formation method of LDMOS device shown in Figure 7 and the formation method of aforementioned VDMOS device are similar, and difference mainly is that drain region 77A and well region 73 are to be formed on side by side in the epitaxial loayer 72, but not is formed on the back side of Semiconductor substrate 71; In addition, formed field oxide 72A ' is between drain region 77A and well region 73, and gate dielectric layer 75 and gate electrode G cover the epitaxial loayer 72 between field oxide 72A ' and the source region 77.With VDMOS device forming process in the same manner, well region injects between mask plate 701 and the gate electrode etch mask version 703 and has deviation value b.
Fig. 8 shows the cross-sectional view of the LIGBT device that the present embodiment provides, and comprising: the Semiconductor substrate 81 that p+ mixes, be formed with the buried regions 81A that n+ mixes on its surface, and buried regions 81A can form by Semiconductor substrate 81 is carried out Implantation; Be positioned at the epitaxial loayer 82 that the n-on the buried regions 81A mixes; Be formed at the field oxide 82A ' on the epitaxial loayer 82, the zone beyond the field oxide 82A ' overlay area is active area 2A; Be arranged in the well region 83 of the p doping of epitaxial loayer 82; Be arranged in the current collection end well region 83A of the n doping of epitaxial loayer 82; The surface of well region 83 has the inversion layer 84A that N-shaped mixes; Epitaxial loayer 82 beyond the well region 83 and the surface of current collection end well region 83A have the accumulation layer 84B that concentration is deepened; Be formed with the emitter region 87 of n+ doping and the contact zone 88 that p+ mixes in the well region 83; Be formed with the collector region 88A that p+ mixes among the current collection end well region 83A; Stacking gate dielectric layer 85 and gate electrode G cover the epitaxial loayer 82 between field oxide 82A ' and the emitter region 87; Emitter E with emitter region 87 electric connections; Dielectric layer 89 around emitter E; Collector electrode C with collector region 88A electrical contact; Be formed at the underlayer electrode Sub on Semiconductor substrate 81 bottom surfaces.Wherein, the mask plate that adopts in well region 83 forming processes is that well region injects mask plate 801, the mask plate that adopts in the inversion layer 84A forming process is active area mask plate 802, and the mask plate that adopts in the gate electrode G forming process is gate electrode etch mask version 803.Wherein, the distance that well region 83 extends laterally to gate electrode G below is 0.75 * Xj+b, and wherein Xj is the junction depth of described well region, for example can be 1.5 μ m ~ 5.5 μ m, 2.25 μ m ~ 4.75 μ m preferably, the span of b is-2 μ m≤b≤5 μ m, preferably: 0 μ m≤b≤1 μ m.
The formation method of LIGBT device shown in Figure 8 and the formation method of aforementioned IGBT device are similar, difference mainly is that collector region 88A and well region 83 are to be formed on side by side in the epitaxial loayer 82, but not be formed on the back side of Semiconductor substrate 81, be formed with buried regions 81A on the surface of Semiconductor substrate 81 in addition.With above-mentioned several device forming processes in the same manner, well region injects between mask plate 801 and the gate electrode etch mask version 803 and has deviation value b.
In the above formed various depletion devices, the span of threshold V T H is :-10V≤VTH≤10V; Preferred range is-5V≤VTH≤5V to select according to different demands.Need to prove in addition, for the n channel device, the span of its threshold V T H is preferably :-5V≤VTH≤0V; For the p channel device, the span of its threshold V T H is preferably: 0V≤VTH≤5V.
Fig. 9 shows the sectional structure chart of the another kind of VDMOS device of the present embodiment, substantially similar with VDMOS device shown in Figure 5, wherein Fig. 5 only shows the regional 2A of core (cell) of device, and Fig. 9 also shows terminal area (termination zone) 2B of nucleus 2A periphery.The concrete structure of nucleus 2A and formation method see also Fig. 5 and associated description, and wherein identical label stands good in Fig. 9, repeats no more here.
In the 2B of terminal area, be formed with the pressure ring 13B that a plurality of p-types are mixed in the epitaxial loayer 12; Be formed with field oxide 12A ' on the surface of epitaxial loayer 12; Can be filled with oxide layer 19A between pressure ring 13B top, the opposite field oxide layer 12A '; Dielectric layer 19 covers the surface of whole device; Can be formed with through hole in the dielectric layer 19, Metal field plate 10 links to each other with pressure ring 13B by this through hole.In addition; can also be formed with esd protection structure between gate electrode G and the source electrode S; for example the protection Zener (Zener) of the polysilicon layer 16A of a plurality of N-shapeds doping of space and the polysilicon layer 16B formation series connection that p-type is mixed is managed; wherein polysilicon layer 16A and the gate electrode G of a N-shaped doping are electrically connected, and the polysilicon layer 16B that p-type is mixed and source electrode S are electrically connected.Adopt the protection diode to strengthen the ESD ability in the present embodiment; nucleus 2A has adopted strip, circular array domain (as shown in figure 10); terminal area 2B adopts the mode of Metal field plate 10 and pressure ring 13B combination to improve puncture voltage in addition, makes its puncture voltage can reach 655V(as shown in figure 11).Certainly, in other embodiments, can also adopt field plate (FP, Field Plate), linear varying doping (VLD, Variation ofLateral Doping), field limiting ring (FLR, Field Limiting Ring) etc. other to well known to a person skilled in the art that terminal technology improves withstand voltage.
Figure 12 be the described VDMOS device of Fig. 9 at VGS=0V, the current distributing figure during VDS=25V, as seen from the figure, the VGS=0V device gets final product conducting, has verified " exhausting " characteristic.Figure 13 is the described VDMOS device of Fig. 9 at deviant b=0(channel length L1 this moment ≈ 1.8 μ m) time raceway groove moulding close up view, Figure 14 is that the described VDMOS device of Fig. 9 is at deviant b=1.6 μ m(channel length L2 this moment ≈ 3.2 μ m) time raceway groove moulding close up view.Figure 15 is the Impurity Distribution curve of the described VDMOS device of Fig. 9, Figure 16 is the threshold voltage curve of the described VDMOS device of Fig. 9, because concentration namely is total raceway groove depletion of charge amount (Q) to the integration of channel depth, under other the same terms, the Q value has determined threshold V T H, and larger VTH is less for the Q value; Increase with the b value, VTH also increases gradually, when the b value increases to a certain degree, and VTH〉0, device becomes enhancement mode by depletion type.
To sum up, in the technical scheme of the present embodiment, well region injects between mask plate and the gate electrode etch mask version and has deviation value b, can become more meticulous by this deviation value b and regulate the channel length of device, and then effectively regulate the threshold voltage of device, improved the flexible design degree.The depletion type power semiconductor that the present embodiment provides can be used for solid-state relay, linear amplifier, inverter, constant-current source, power circuit etc. and use.
Although the utility model with preferred embodiment openly as above; but it is not to limit the utility model; any those skilled in the art are not within breaking away from spirit and scope of the present utility model; can make possible change and modification, therefore protection range of the present utility model should be as the criterion with the scope that the utility model claim is defined.
Claims (13)
1. a depletion type power semiconductor is characterized in that, comprising:
Semiconductor substrate;
Be positioned at the epitaxial loayer of the first doping type on the described Semiconductor substrate;
Be formed at the well region of the second doping type in the described epitaxial loayer, described the second doping type is opposite with described the first doping type, and the surface of described well region has the inversion layer of the first doping type;
Be positioned at successively gate dielectric layer and gate electrode on the described epitaxial loayer, the distance that described well region extends laterally to described gate electrode below is 0.75 * Xj+b, and wherein Xj is the junction depth of described well region ,-2 μ m≤b≤5 μ m.
2. depletion type power semiconductor according to claim 1 is characterized in that, the span of described b is: 0 μ m≤b≤1 μ m.
3. depletion type power semiconductor according to claim 1 is characterized in that, the distance that described well region extends laterally to described gate electrode below is 1.5 μ m ~ 5.5 μ m.
4. depletion type power semiconductor according to claim 1 is characterized in that, the distance that described well region extends laterally to described gate electrode below is 2.25 μ m ~ 4.75 μ m.
5. depletion type power semiconductor according to claim 1 is characterized in that, the span of the threshold V T H of described depletion type power semiconductor is :-10V≤VTH≤10V.
6. depletion type power semiconductor according to claim 1 is characterized in that, described depletion type power semiconductor is the n channel device, and the span of its threshold V T H is :-5V≤VTH≤0V.
7. depletion type power semiconductor according to claim 1 is characterized in that, described depletion type power semiconductor is the p channel device, and the span of its threshold V T H is: 0V≤VTH≤5V.
8. depletion type power semiconductor according to claim 1, it is characterized in that, described depletion type power semiconductor is the VDMOS device, described Semiconductor substrate is the first doping type, described gate dielectric layer and gate electrode cover the epitaxial loayer between the adjacent well region, also are formed with the source region of the first doping type in the well region of described gate electrode both sides.
9. depletion type power semiconductor according to claim 7, it is characterized in that, described Semiconductor substrate comprises nucleus and is positioned at the terminal area of described nucleus periphery, is formed with the pressure ring of the second doping type in the epitaxial loayer of described terminal area; Be formed with field oxide on the epi-layer surface of described terminal area; Be filled with oxide layer between described pressure ring top, the opposite field oxide layer; Be coated with dielectric layer on described field oxide, the oxide layer, be formed with through hole in the described dielectric layer, Metal field plate links to each other with described pressure ring by this through hole.
10. depletion type power semiconductor according to claim 8 is characterized in that, is formed with the protection Zener diode of one or more series connection in the described dielectric layer, and its negative electrode and described gate electrode are electrically connected, and its anode and described source region are electrically connected.
11. depletion type power semiconductor according to claim 1, it is characterized in that, described depletion type power semiconductor is the IGBT device, described Semiconductor substrate is the first doping type, described Semiconductor substrate face also is formed with the collector region of the second doping type, described gate dielectric layer and gate electrode cover the epitaxial loayer between the adjacent well region, also are formed with the emitter region of the first doping type in the well region of described gate electrode both sides.
12. depletion type power semiconductor according to claim 1, it is characterized in that, described depletion type power semiconductor is the LDMOS device, described Semiconductor substrate is the second doping type, be formed with the source region of the first doping type in the described well region, also be formed with the drain region with described well region the first doping type arranged side by side in the described epitaxial loayer, also be formed with field oxide on the epitaxial loayer between described drain region and the well region, described gate dielectric layer and gate electrode cover the epitaxial loayer between described field oxide and the source region.
13. depletion type power semiconductor according to claim 1, it is characterized in that, described depletion type power semiconductor is the LIGBT device, described Semiconductor substrate is the second doping type, the upper surface of described Semiconductor substrate is formed with the buried regions of the first doping type, described epitaxial loayer is positioned on the described buried regions, be formed with the emitter region of the first doping type in the described well region, also be formed with the current collection end well region with described well region the first doping type arranged side by side in the described epitaxial loayer, be formed with the collector region of the second doping type in the described current collection end well region, also be formed with field oxide on the epitaxial loayer between described collector region and the well region, described gate dielectric layer and gate electrode cover the epitaxial loayer between described field oxide and the emitter region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220355522 CN202736927U (en) | 2012-07-20 | 2012-07-20 | Depletion type power semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220355522 CN202736927U (en) | 2012-07-20 | 2012-07-20 | Depletion type power semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202736927U true CN202736927U (en) | 2013-02-13 |
Family
ID=47662596
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220355522 Withdrawn - After Issue CN202736927U (en) | 2012-07-20 | 2012-07-20 | Depletion type power semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202736927U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102751332A (en) * | 2012-07-20 | 2012-10-24 | 杭州士兰微电子股份有限公司 | Depletion type power semiconductor device and manufacturing method thereof |
| CN111968974A (en) * | 2020-08-28 | 2020-11-20 | 电子科技大学 | Integrated power semiconductor device and manufacturing method |
-
2012
- 2012-07-20 CN CN 201220355522 patent/CN202736927U/en not_active Withdrawn - After Issue
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102751332A (en) * | 2012-07-20 | 2012-10-24 | 杭州士兰微电子股份有限公司 | Depletion type power semiconductor device and manufacturing method thereof |
| CN102751332B (en) * | 2012-07-20 | 2014-11-12 | 杭州士兰微电子股份有限公司 | Depletion type power semiconductor device and manufacturing method thereof |
| CN111968974A (en) * | 2020-08-28 | 2020-11-20 | 电子科技大学 | Integrated power semiconductor device and manufacturing method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10727334B2 (en) | Lateral DMOS device with dummy gate | |
| CN102751332B (en) | Depletion type power semiconductor device and manufacturing method thereof | |
| CN107204372B (en) | Trench type semiconductor device with optimized terminal structure and manufacturing method | |
| US8659076B2 (en) | Semiconductor device structures and related processes | |
| CN102184944B (en) | Junction terminal structure of lateral power device | |
| CN102376762B (en) | Super junction LDMOS(Laterally Diffused Metal Oxide Semiconductor) device and manufacturing method thereof | |
| CN1851923A (en) | SOI LIGBT device unit of integrated ESD diode | |
| CN106571394A (en) | Power device and manufacturing method thereof | |
| CN104377244A (en) | Device structure lowering LDMOS on resistance | |
| CN102760754A (en) | Depletion type VDMOS (Vertical Double-diffusion Metal Oxide Semiconductor) and manufacturing method thereof | |
| CN102184945A (en) | Groove gate type MOSFET device | |
| CN208028069U (en) | Novel two-sided step buried oxide SOI LDMOS with buried structure | |
| CN102709190A (en) | LDMOS (Laterally Diffused Metal Oxide Semiconductor) field effect transistor and manufacturing method thereof | |
| CN105140289A (en) | N-type LDMOS device and technical method thereof | |
| CN202736927U (en) | Depletion type power semiconductor device | |
| CN102637744B (en) | Signal operation instruction (SOI) transverse super junction power metal oxide semiconductor field effect transistor (MOSFET) device | |
| CN104201203B (en) | High withstand voltage LDMOS device and manufacture method thereof | |
| CN102646712A (en) | Laterally diffused metal oxide semiconductor (LDMOS) and manufacturing method thereof | |
| CN102522338B (en) | Forming method of high-voltage super-junction metal oxide semiconductor field effect transistor (MOSFET) structure and P-shaped drift region | |
| CN104518027A (en) | LDMOS (laterally diffused metal oxide semiconductor) device and manufacturing method thereof | |
| CN113659011A (en) | Integrated device based on super junction MOSFET and manufacturing method thereof | |
| CN109192777B (en) | Deep-groove semi-super-junction structure power device and manufacturing method | |
| CN104037206A (en) | Super-junction device and manufacturing method thereof | |
| CN109994549B (en) | Semiconductor power device | |
| CN103681839A (en) | NLDMOS (N-type laterally diffused metal oxide semiconductor) device and manufacture method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20130213 Effective date of abandoning: 20141112 |
|
| RGAV | Abandon patent right to avoid regrant |