CN106298692B - The production method of chip-packaging structure - Google Patents
The production method of chip-packaging structure Download PDFInfo
- Publication number
- CN106298692B CN106298692B CN201510200591.1A CN201510200591A CN106298692B CN 106298692 B CN106298692 B CN 106298692B CN 201510200591 A CN201510200591 A CN 201510200591A CN 106298692 B CN106298692 B CN 106298692B
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- layer
- chip
- conductive circuit
- conductive
- circuit layer
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 239000002184 metal Substances 0.000 claims description 53
- 229910052751 metal Inorganic materials 0.000 claims description 53
- 239000000463 material Substances 0.000 claims description 35
- 238000000465 moulding Methods 0.000 claims description 34
- 230000004888 barrier function Effects 0.000 claims description 33
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 27
- 239000010931 gold Substances 0.000 claims description 25
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 24
- 229910052737 gold Inorganic materials 0.000 claims description 24
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 14
- 229910052802 copper Inorganic materials 0.000 claims description 14
- 239000010949 copper Substances 0.000 claims description 14
- 229910052759 nickel Inorganic materials 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 11
- 238000007747 plating Methods 0.000 claims description 7
- 238000011161 development Methods 0.000 claims description 3
- 230000000295 complement effect Effects 0.000 claims description 2
- 238000009713 electroplating Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 claims 50
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 239000002344 surface layer Substances 0.000 claims 1
- 239000000084 colloidal system Substances 0.000 description 6
- 239000010408 film Substances 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 238000012856 packing Methods 0.000 description 5
- 238000007654 immersion Methods 0.000 description 4
- 238000011010 flushing procedure Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000003973 paint Substances 0.000 description 3
- 238000003466 welding Methods 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 229910001369 Brass Inorganic materials 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 239000002390 adhesive tape Substances 0.000 description 1
- 239000010951 brass Substances 0.000 description 1
- 239000013039 cover film Substances 0.000 description 1
- 229920006336 epoxy molding compound Polymers 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001151 other effect Effects 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000003755 preservative agent Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The present invention relates to a kind of chip package base plates, comprising: help layer, first conductive circuit layer, conductive column and soldermask layer, the soldermask layer includes multiple first openings, it is described that layer and first conductive circuit layer is helped to be both formed in multiple first openings, first conductive circuit layer is formed in the surface for helping layer, and the conductive column is formed in the surface of first conductive circuit layer, and extends to the surface far from first conductive circuit layer.The present invention also provides a kind of chip-packaging structure and a kind of production methods of chip-packaging structure.
Description
Technical field
The present invention relates to a kind of production methods of chip-packaging structure.
Background technique
Chip package base plate is produced due to that can provide electrical connection, protection, support, heat dissipation, assembling and other effects for chip in electronics
It is widely used in product.With the lightening development of electronic product, chip package base plate is also increasingly lightening.Chip package
Structure includes chip package base plate and the chip that is arranged on chip package base plate.However, providing a kind of lightening chip
Package substrate is those skilled in the art's letter project to be solved.
Summary of the invention
In view of this, it is necessary to provide a kind of production methods of chip-packaging structure that can solve the above problem.
A kind of production method of chip-packaging structure, comprising steps of
Double-sided copper-clad substrate is provided, the double-sided copper-clad substrate includes insulating layer, positioned at opposite two surfaces of insulating layer
The first metal layer and second metal layer；
Soldermask layer is formed on the first metal layer surface, the soldermask layer includes multiple first openings, and the first opening is naked
The first metal layer described in exposed portion；
It is formed in first opening and helps layer, helping layer surface to form the first conductive circuit layer, described first
The surface far from the first metal layer of conductive circuit layer forms conductive column；
Third opening is formed from second metal layer to the direction of the first metal layer in double-sided copper-clad substrate, the third is opened
Mouth exposes part soldermask layer and first conductive circuit layer；
It helps layer surface that one chip is set described, forms the chip-packaging structure.
Compared with prior art, the production method of chip package base plate and chip-packaging structure provided by the invention, will
First conductive circuit layer is formed between the first opening in the soldermask layer, reduces the thickness of chip-packaging structure, also
It is made conducive to the fine rule road of conducting wire.
Detailed description of the invention
Fig. 1 is the diagrammatic cross-section for the double-sided copper-clad substrate that first embodiment of the invention provides.
Fig. 2 is forming soldermask layer on the first metal layer and form the first barrier layer in second metal layer in Fig. 1
Diagrammatic cross-section.
Fig. 3 is to form the diagrammatic cross-section of layer gold on the first metal layer surface.
Fig. 4 is the diagrammatic cross-section that nickel layer is formed on the basis of Fig. 3.
Fig. 5 is the diagrammatic cross-section for forming internal layer circuit layer on the basis of fig. 4.
Fig. 6 is to form third barrier layer, and the copper on the second metal layer surface on the surface of the soldermask layer
The surface of layer forms the diagrammatic cross-section on the 4th barrier layer.
Fig. 7 is to form the diagrammatic cross-section of conductive column on the surface of the wire line layer.
Fig. 8 is the diagrammatic cross-section after the conductive column formed to Fig. 7 is ground.
Fig. 9 is the diagrammatic cross-section for removing third barrier layer and the 4th barrier layer.
Figure 10 is the diagrammatic cross-section that moulding material is formed on the basis of Fig. 9.
Figure 11 is the diagrammatic cross-section after the moulding material described in Figure 10 is ground.
Figure 12 is to form the diagrammatic cross-section on the 4th barrier layer in the layers of copper and the moulding material surface.
Figure 13 is the section signal for forming the opening exposure layer gold in the second metal layer on the basis of Figure 12
Figure.
Figure 14 is the diagrammatic cross-section for removing the 4th barrier layer.
Figure 15 is the diagrammatic cross-section that the chip-packaging structure that chip obtains is arranged on the basis of Figure 14.
Main element symbol description
The present invention that the following detailed description will be further explained with reference to the above drawings.
Specific embodiment
The technical program is provided below in conjunction with accompanying drawings and embodiments chip package base plate, chip-packaging structure and its
Production method is described in further detail.
The production method for the chip package base plate 100 that the technical program first embodiment provides, comprising steps of
The first step, referring to Fig. 1, providing a double-sided copper-clad substrate 10.The double-sided copper-clad substrate 10 includes insulating layer
11, the first metal layer 12 and second metal layer 13 and at least one through hole on 11 opposite two surfaces of insulating layer are located at
14.The first metal layer 12 and the material of the second metal layer 13 can be copper, iron or brass etc..In present embodiment
In, the material of the first metal layer 12 and the second metal layer 13 is copper.
Second step please refers to Fig. 2-5, forms the first conductive circuit layer 34 and the second conductive circuit layer 36.Wherein form institute
State the first conductive circuit layer 34 and the second conductive circuit layer 36 comprising steps of
Firstly, cleaning to double-sided copper-clad substrate 10, the spot of 14 inner wall of its surface and through hole is removed, in favor of rear
The progress of continuous step.
Secondly, referring to Fig. 2, soldermask layer 21 is formed on 12 surface of the first metal layer, on 13 surface of second metal layer
Form the first barrier layer 22.The soldermask layer 21 forms multiple first openings 210 by exposure development processing procedure, to open from first
The part the first metal layer 12 is exposed at mouth 210.Second metal layer 13 is completely covered in first barrier layer 22.It is described anti-
Layer 21 is anti-welding green paint (SolderMask), and with a thickness of about 30um, first barrier layer 22 is dry film solder mask (Dry
film).Certainly, cover film, the adhesive tape etc. that first barrier layer 22 also could alternatively be low sticky (easily removing) block
Object.
Thirdly, it also referring to Fig. 3-4, is plated on the first metal layer 12 that first opening 210 is exposed and helps weldering
Layer 31.This helps layer 31 to be selected from electroless nickel layer, plating layer gold, electroless nickel plating layer gold (electroless Ni/Au), immersion silver
(immersion silver), immersion tin (immersion tin).In the present embodiment, described that layer 31 is helped to include plating
Layer gold 32 and electroless nickel layer 33, the layer gold 32 are located at the surface of the first metal layer 12, and the nickel layer 33 is located at the gold
The surface of layer 32.The thickness of the layer gold 32 is about 0.3um.
And then, hole wall, the nickel layer 33 referring to Fig. 5, removing first barrier layer 22, in the through hole 14
Surface and the second metal layer 13 one layer of layers of copper of electroplating surface, the layers of copper positioned at 33 surface of nickel layer forms described the
The second conduction is collectively formed in one conductive circuit layer 34, the layers of copper 35 and the second metal layer 13 on 13 surface of second metal layer
Line layer 36, second conductive circuit layer 36 for realizing chip-packaging structure increasing layer.Wherein, first conducting wire
Layer 34 keeps concordant with the soldermask layer 21.This step, which is realized, has been formed in 21 shapes of soldermask layer for the first conductive circuit layer 34
At first opening 210 in.Soldermask layer 21 in the present invention refers to anti-welding green paint, due to anti-welding green paint material molecule compared with
Small, intermolecular gap is less than 10um, the first conductive circuit layer 34 is embedded in the first opening for being placed in soldermask layer 21, thus
The thickness of the conducting wire of the first conductive circuit layer 34 can be made to drop to 10um, namely be conducive to the production of fine rule road.It is described to pass through
The inner wall of through-hole 14 is plated layers of copper, for realizing the first metal layer 12 and second metal layer on 11 opposite two surfaces of insulating layer
13 electrically conduct.
In the present embodiment, since the first metal layer 12 and second metal layer 13 are covered in the insulating layer 11
Whole surface, so the first metal layer 12 and second metal layer 13 can be used as the path of electric current conduction, so helping layer
31 and the first conductive circuit layer 34 being electroplated on layer 31 and the second conductive circuit layer 36 is helped to can use nothing described
The mode of electroplated lead (Bussless) plating is formed, namely can realize that plating helps layer it is not necessary that electroplated lead is additionally arranged
31 and first conductive circuit layer 34.
Third step please refers to Fig. 6-9, forms multiple conductive columns 44 on the surface of first conductive circuit layer 34.Wherein
Form the conductive column 44 comprising steps of
Firstly, referring to Fig. 6, the surface of the soldermask layer 21 and part first conductive circuit layer 34 surface shape
Third barrier layer 42 is formed at the second barrier layer 41, and on the surface of second conductive circuit layer 36.It is described in the present embodiment
Second barrier layer 41 and the third barrier layer 42 are dry film.In the present embodiment, second barrier layer 41 is through overexposure
Photodevelopment processing forms multiple second openings 410, the first conductive circuit layer 34 described in second opening, 410 expose portions.
Secondly, referring to Fig. 7, being electroplated from first conductive circuit layer 34 that second opening 410 exposes
Form the conductive column 44.The separate one end with first conductive circuit layer 34 of the conductive column 44 protrudes from second resistance
The diameter of conductive column 44 described in barrier 41 is about 150um, and length is about 90um.
Then, referring to Fig. 8, grinding to the conductive column 44, keep the conductive column 44 conductive far from described first
The end face of line layer 34 keeps flushing and be attached with other circuit boards or in favor of subsequent in the realization of the surface of conductive column 44
Increasing layer.Certainly, this step is not required, can also be subsequently formed again after moulding material 45 carry out again to the conductive column 44 into
Row grinding.
Finally, referring to Fig. 9, removing second resistance on the soldermask layer 21 and 34 surface of the first conductive circuit layer
The third barrier layer 42 on 36 surface of barrier 41 and the second conductive circuit layer.
4th step, referring to Fig. 10, forming moulding material (Molding on the surface of first conductive circuit layer 34
Material) 45, a chip bearing unit 50 is obtained, the moulding material 45 coats first conductive circuit layer 34 and institute
State conductive column 44.
Figure 11 is please referred to, being formed after the moulding material 45 further includes grinding the moulding material 45, makes the mold member
Surface and the conductive column 44 table far from first conductive circuit layer 34 of the material 45 far from first conductive circuit layer 34
Face keeps flushing, to expose the conductive column 44, expose the conductive column 44 in the moulding material 45 for increasing layer or
Person welds other circuit boards.The thermal expansion coefficient of the thermal expansion coefficient of the moulding material 45 and the subsequent chip 70 for needing to encapsulate
Quite.In the present embodiment, the moulding material 45 is epoxy resin, and the value of thermal expansion coefficient CTE is about 3~6ppm/
DEG C, and be to form moulding material 45 by way of molding (Molding), for example, can be with pre-production die cavity, the die cavity
Structure and the conductive column 44 complementary structure, then by third step it is final (remove second barrier layer 41 with it is described
Structure behind third barrier layer 42) formed structure be put into the die cavity, moulding material is flowed into and is filled out in a manner of mould stream
The full die cavity makes the moulding material coat first conductive circuit layer 34 and the conductive column 44, to the forming material
It is demoulded after material is dry, the moulding material 45 can coat the conductive column 44.
5th step please refers to Figure 12-13, along close on the chip bearing unit 50, from the second conductive circuit layer 36
The soldermask layer 21 opens up to form a third opening 51, and the third opening 51 exposes the layer gold 32 and part is described anti-
Layer 21.Wherein, the method for forming third opening 51 includes:
Firstly, please referring to Figure 12, formed respectively in second conductive circuit layer 36 and the surface of the moulding material 45
4th barrier layer 61, the 4th barrier layer 61 are photosensitive dry film.
Secondly, please referring to Figure 13, the part layers of copper 35 not covered by the 4th barrier layer 61, the second metal are etched away
Layer 13, laser cutting remove the insulating layer 11 and etch away the first metal layer 12 to form the third opening
51, the third opening 51 exposes the layer gold 32 and the part soldermask layer 21 at this time.
Figure 14 is please referred to, the 4th barrier layer 61 is removed, to obtain chip package base plate 100.In present embodiment
In, removing behind the 4th barrier layer 61 further includes carrying out cleaning treatment and surface treatment, Yi Ji to 32 surface of layer gold
One layer of 44 Surface Creation of conductive column organic guarantor welds film (not shown) (Organic Solderability
Preservatives, OSP).
6th step, please refers to Figure 15, will be described by routing combination technology, surface mounting technology or flip chip packaging technologies
70 structure of chip is loaded at the position for being exposed to third opening 51 of the chip package base plate 100 to form chip package knot
Structure 200.Chip 70 may include memory chip, logic chip or digit chip.Wherein, this chip-packaging structure 200
Second conductive circuit layer 36 for realizing chip-packaging structure route increasing layer.
In the present embodiment, the thermal expansion coefficient of the chip 70 (Coefficient of thermal expansion,
It CTE) is about 2.6ppm/ DEG C.Namely the thermal expansion coefficient of moulding material and the thermal expansion coefficient of chip are suitable in this case, so as to
To prevent chip warpage.
In the present embodiment, the chip 70 is loaded on by flip chip packaging technologies (Flip Chip Technology) structure
The surface for helping layer 31, specifically, one of surface of chip 70 are that 32 table of layer gold is welded in by soldered ball 71
Face, another surface are electrically connected (wire bonding, routing combination technology) by bonding lead 72 and the layer gold 32, thus
Realize that the signal of chip 70 and chip package base plate 100 transmits.Encapsulation is also perfused between the chip 70 and the layer gold 32
Colloid 73 better ensures that the chip 70 and the stability after the chip package base plate 100 encapsulation.Specifically, can pass through
Packing colloid 73 is arranged at third opening 51 in (molding) technology of molding, to obtain the chip package base plate 100.
In the present embodiment, the packing colloid 73 and the table for the layers of copper 35 for being located at 13 surface of second metal layer in third opening 51
Face keeps flushing.
Referring to Figure 15, the present invention also provides a kind of chips made of said chip encapsulating structure production method
Encapsulating structure 200.The chip-packaging structure 200 includes: chip package base plate 100 and chip 70.
The chip package base plate 100 includes soldermask layer 21, helps layer 31, the first conductive circuit layer 34, conductive column 44, mould
Moulding material 45 and circuit base plate 101.
The circuit base plate 101 include: the first metal layer 12, positioned at 12 surface of the first metal layer insulating layer 11,
The second conductive circuit layer 36 positioned at 11 surface of insulating layer.Conductive hole 15, the conductive hole are provided in the insulating layer 11
15 for being connected the first metal layer 12 and second metal layer 13.Second conductive circuit layer 36 includes being located at 11 surface of insulating layer
Second metal layer 13 be located at 13 surface of second metal layer layers of copper 35.
The soldermask layer 21 is formed in the surface of the first metal layer 12.The soldermask layer 21 includes multiple first openings
210, it is described that layer 31 and first conductive circuit layer 34 is helped to be both formed in first opening 210, it is described to help layer 31
Described that layer 31 is helped to be formed prior to first conductive circuit layer 34 including layer gold 32 and nickel layer 33, the nickel layer 33 is formed in
The surface of the layer gold 32, first conductive circuit layer 34 are formed in the surface of the nickel layer 33.The circuit base plate 101 wraps
Include a third opening 51, soldermask layer 21 and the layer gold 32 described in the third 51 expose portions of opening.
The soldermask layer 21 includes a bottom surface 211 and the upper surface 212 opposite with bottom surface.First conductive circuit layer
34 flush with the bottom surface 211, and surface of the layer gold 32 far from first conductive circuit layer 34 and the upper surface 212 are neat
It is flat.
The conductive column 44 is formed in the surface of first conductive circuit layer 34 and to far from first conducting wire
The surface of layer 34 extends, and the moulding material 45 is formed in described in the bottom surface 211 of the soldermask layer 21 and covering part first and leads
Electric line layer 34 and conductive column 44, surface of the conductive column 44 far from first conductive circuit layer 34 and the moulding material
45 are flush.
The chip 70 is arranged at the position of the third opening 51.The chip 70 by the soldered ball 71 with it is described
Chip package base plate 100 is fixedly connected, in addition, in present embodiment, surface of the chip 70 far from the layer gold 32 also
It is provided with bonding lead 72, the both ends of the bonding lead 72 are separately connected the chip 70 and the layer gold 32, to realize
The signal of chip 70 and chip package base plate 100 transmits.Packing colloid is also perfused between the chip 70 and the layer gold 32
73, better ensure that the stability between after the chip 70 and the chip package base plate 100 encapsulate.
It in the present embodiment, further include that packing colloid is filled to the position of third opening 51 after chip 70 being provided with
73, so that packing colloid 73 is coated the exposed soldermask layer 21 of the bonding lead 72, chip 70 and chip package base plate 100 and is helped weldering
Organic guarantor on 31 surface of layer welds film, is formed by third opening 51 so that chip 70 is embedded in circuit base plate 101.This implementation
In example, which is black glue or epoxy molding plastic (epoxy molding compound).
In conclusion the production method of chip package base plate provided by the invention and chip-packaging structure, by the first conduction
Line layer is formed between the first opening in the soldermask layer, is reduced the thickness of chip-packaging structure, is also helped conduction
The fine rule road of route makes.
It is understood that for those of ordinary skill in the art, can do in accordance with the technical idea of the present invention
Various other changes and modifications out, and all these changes and deformation all should belong to the protection model of the claims in the present invention
It encloses.
Claims (5)
1. a kind of production method of chip-packaging structure, comprising steps of
Double-sided copper-clad substrate is provided, the double-sided copper-clad substrate includes insulating layer, positioned at the first of opposite two surfaces of insulating layer
Metal layer and second metal layer；
Soldermask layer is formed on the first metal layer surface, the soldermask layer includes multiple first openings, and the first opening exposes
The part the first metal layer；
It is formed in first opening and helps layer, help layer surface to form the first conductive circuit layer described, described first
The surface far from the first metal layer of conductive circuit layer forms conductive column；
Third opening is formed from second metal layer to the direction of the first metal layer in double-sided copper-clad substrate, the third opening is naked
Soldermask layer described in exposed portion helps layer with described；
A chip is set in the third open inner, and makes to help layer described in the chip electrical connection, forms the chip package
Structure.
2. the production method of chip-packaging structure as described in claim 1, which is characterized in that further include before forming chip
Moulding material is formed on the surface of the soldermask layer, the moulding material coats first conductive circuit layer and the conduction
Column, surface of the conductive column far from first conductive circuit layer and the moulding material are far from first conductive circuit layer
Surface be flush.
3. the production method of chip-packaging structure as described in claim 1, which is characterized in that described that layer is helped to include nickel layer and gold
Layer, the layer gold are formed prior to the nickel layer, and first conductive circuit layer is by the nickel layer electroplating surface layers of copper shape
At, plating form first conductive circuit layer while further include the second metal layer surface formed one layer of copper
The second conductive circuit layer, the core is collectively formed in layer, the layers of copper and the second metal layer on the second metal layer surface
Piece is arranged on the layer gold surface.
4. the production method of chip-packaging structure as claimed in claim 3, which is characterized in that forming the conductive column includes step
It is rapid:
The surface of first conductive circuit layer and the surface of second conductive circuit layer be respectively formed the second barrier layer with
Third barrier layer is exposed development to second barrier layer, and second barrier layer is made to form multiple second openings, described
First conductive circuit layer described in second opening expose portion；
Conductive column is formed to plating is carried out from first conductive circuit layer that second opening is exposed；And
Remove second barrier layer and third barrier layer.
5. the production method of chip-packaging structure as claimed in claim 2, which is characterized in that forming the moulding material includes
Step:
Make die cavity, the complementary structure of the structure of the die cavity and the conductive column；
Carrier after formation conductive column is put into the die cavity；
Moulding material is flowed into in a manner of mould stream and filled up the die cavity, moulding material is made to coat first conductive circuit layer
With the conductive column, demoulded after the moulding material is dry, the moulding material coats first conducting wire
Layer and the conductive column.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510200591.1A CN106298692B (en) | 2015-04-24 | 2015-04-24 | The production method of chip-packaging structure |
| TW104113605A TWI562293B (en) | 2015-04-24 | 2015-04-28 | Manufacturing method of chip packaging structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510200591.1A CN106298692B (en) | 2015-04-24 | 2015-04-24 | The production method of chip-packaging structure |
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| CN106298692A CN106298692A (en) | 2017-01-04 |
| CN106298692B true CN106298692B (en) | 2019-02-01 |
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| CN201510200591.1A Active CN106298692B (en) | 2015-04-24 | 2015-04-24 | The production method of chip-packaging structure |
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| TW (1) | TWI562293B (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108461405B (en) * | 2017-02-21 | 2020-04-10 | 碁鼎科技秦皇岛有限公司 | Circuit carrier plate and manufacturing method thereof |
| CN107863325A (en) * | 2017-02-27 | 2018-03-30 | 西安华羿微电子股份有限公司 | High-power MOS FET's is fanned out to shape encapsulating structure and its manufacturing process |
| CN109935521B (en) * | 2019-01-30 | 2022-03-04 | 深圳市志金电子有限公司 | Packaging substrate manufacturing process, packaging substrate and chip packaging structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6306682B1 (en) * | 1999-05-31 | 2001-10-23 | Siliconware Precision Industries Co., Ltd. | Method of fabricating a ball grid array integrated circuit package having an encapsulating body |
| CN102136459A (en) * | 2010-01-25 | 2011-07-27 | 矽品精密工业股份有限公司 | Packaging structure and manufacture method thereof |
| TW201407695A (en) * | 2012-08-08 | 2014-02-16 | Subtron Technology Co Ltd | Package carrier and manufacturing method thereof |
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| US8350377B2 (en) * | 2008-09-25 | 2013-01-08 | Wen-Kun Yang | Semiconductor device package structure and method for the same |
| TWI503935B (en) * | 2011-10-17 | 2015-10-11 | 矽品精密工業股份有限公司 | Semiconductor package and fabrication method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6306682B1 (en) * | 1999-05-31 | 2001-10-23 | Siliconware Precision Industries Co., Ltd. | Method of fabricating a ball grid array integrated circuit package having an encapsulating body |
| CN102136459A (en) * | 2010-01-25 | 2011-07-27 | 矽品精密工业股份有限公司 | Packaging structure and manufacture method thereof |
| TW201407695A (en) * | 2012-08-08 | 2014-02-16 | Subtron Technology Co Ltd | Package carrier and manufacturing method thereof |
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| TWI562293B (en) | 2016-12-11 |
| CN106298692A (en) | 2017-01-04 |
| TW201639089A (en) | 2016-11-01 |
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