CN106249799A - A kind of full MOSFET reference voltage source of Low Drift Temperature - Google Patents
A kind of full MOSFET reference voltage source of Low Drift Temperature Download PDFInfo
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- CN106249799A CN106249799A CN201610664375.7A CN201610664375A CN106249799A CN 106249799 A CN106249799 A CN 106249799A CN 201610664375 A CN201610664375 A CN 201610664375A CN 106249799 A CN106249799 A CN 106249799A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
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Abstract
The invention discloses the full MOSFET reference voltage source of a kind of Low Drift Temperature, including positive temperature coefficient voltage generation circuit, core circuit, pole-zero compensation circuit three part.The outfan of positive temperature coefficient voltage generation circuit is connected with the input of core circuit, the outfan of core circuit is connected with the input of pole-zero compensation circuit, the outfan of pole-zero compensation circuit is connected to core circuit through resistance, provides bias voltage for core circuit.The present invention can simplify circuit structure, improves circuit work frequency, reduces reference voltage temperature coefficient so that reference voltage keeps stable output within the scope of the widest temperature, it is adaptable to great majority need in the analogy and digital circuit of reference voltage source.
Description
Technical field
The invention belongs to electronic technology field, further relate to a kind of Low Drift Temperature in Analogous Integrated Electronic Circuits technical field
All-metal-Oxide-Semiconductor Field effect transistor MOSFET (Metal Oxide Semiconductor Field
Effect Transistor) reference voltage source.The present invention can as analog circuit and the pith of Digital Analog Hybrid Circuits,
Can be used for providing reliable and stable reference voltage for the module such as agitator, LDO.
Background technology
Integrated circuit technology develops rapidly, and in integrated circuit design, reference voltage source is a key modules, and by extensively
General it is applied in analog circuit, digital circuit and Analog-digital circuit.Traditional benchmark voltage source generally uses " band gap " technology,
Be unableing to do without large-area resistance, amplifier and bipolar transistor in structure, and circuit structure is complicated, power consumption and temperature drift are the most relatively
Height, chip occupying area is bigger.In order to meet the high-stability requirement of reference voltage source, reference voltage source must have low temperature
Coefficient.
The patented technology " a kind of band-gap reference circuits based on two kinds of threshold voltage MOS device " that University of Electronic Science and Technology has
(patent No. ZL 201110440384.5, Authorization Notice No. CN 102495661 B) disclose a kind of based on two kinds of threshold value electricity
The band-gap reference circuit of pressure MOS device.This patented technology specifically includes that the start-up circuit of negative temperature parameter current source circuit, uses
In starting to become to bear the current source circuit of proportionate relationship with temperature；Become to bear the current source circuit of proportionate relationship with temperature, be used for producing
Become to bear the electric current of proportionate relationship with temperature；Reference voltage output circuit, for exporting the reference voltage with zero-temperature coefficient characteristic；With
The current source circuit of temperature direct proportionality, for producing the electric current with temperature direct proportionality；Biasing circuit, be used for be
The cascade pipe of current mirroring circuit provides bias voltage；The start-up circuit of positive temperature coefficient current source circuit, for start with
The current source circuit of temperature direct proportionality.The method achieve and reference voltage is carried out second order compensation, but, this patent skill
The weak point that art yet suffers from is, each road and the current source circuit of temperature proportional relation are required for extra startup electricity
Road so that circuit structure is the most complicated.
Paper " design in a kind of full MOS the Low-power-consumptioreference reference voltage source " (" electricity that Chi Shangsheng, Hu Wei, Xu Yusen deliver at it
Sub-technology is applied ", volume 40, the 5th phase in 2014) in disclose a kind of full MOS Low-power-consumptioreference reference voltage source.This reference voltage
Source specifically includes that Δ VthProduce circuit, utilize the NMOSFET of two different threshold voltages to produce the electricity with negative temperature characteristic
Pressure；VTProduce circuit, for producing the road voltage with positive temperature characterisitic；ΔVthWith VTCompensate circuit, will have negative temperature
The voltage Δ V of characteristicthWith the voltage V with positive temperature characterisiticTCompensate, obtain the reference voltage with zero-temperature coefficient characteristic.
Although the method utilizes two MOSFET threshold voltage differences and thermal voltage VTMutually compensate for the base having obtained that there is zero-temperature coefficient characteristic
Quasi-voltage, but, this reference voltage source yet suffers from being disadvantageous in that, one is that MOSFET element is biased in sub-threshold region
Territory can make the response speed of circuit slack-off, thus reduces the operating frequency of circuit, increases the temperature coefficient of reference voltage so that when
When temperature changes, the change of reference voltage is obvious；Two are the absence of pole-zero compensation circuit so that reference voltage steady
Qualitative reduction.
Summary of the invention
It is an object of the invention to overcome above-mentioned the deficiencies in the prior art, it is provided that the full MOSFET benchmark electricity of a kind of Low Drift Temperature
Potential source.
The concrete thought of the present invention is, uses full MOS structure, utilizes the voltage with positive temperature characterisitic to produce with core circuit
Raw voltage mutually compensates for, and produces the reference voltage of zero-temperature coefficient characteristic.Depletion type NMOS tube is utilized to start positive temperature coefficient voltage
Produce circuit, it is not necessary to extra start-up circuit, reduce circuit structure complexity, make reference voltage protect within the scope of the widest temperature
Hold relatively low temperature coefficient.Utilize pole-zero compensation circuit that the reference voltage of output is carried out zero pole point compensation, improve benchmark electricity
The stability of pressure, meets the requirement of reference voltage source performance indications.
For achieving the above object, the present invention includes that positive temperature coefficient voltage generation circuit, core circuit, zero pole point compensate electricity
Road, positive temperature coefficient voltage generation circuit include two p-type metal-oxide semiconductor fieldeffect transistor PMOSFET, two
Individual enhancement mode N-type metal-oxide semiconductor fieldeffect transistor NMOSFET, two depletion type N-type metal-oxide-half
Conductor field-effect transistor NMOSFET, the outfan of positive temperature coefficient voltage generation circuit is connected with the input of core circuit.
Core circuit includes two p-type metal-oxide semiconductor fieldeffect transistor PMOSFET, two enhancement mode N-type metal-oxygens
The output of compound-semiconductor field effect transistor NMOSFET, the input of core circuit and positive temperature coefficient voltage generation circuit
End connects, and the outfan of core circuit is connected with the input of pole-zero compensation circuit.Pole-zero compensation circuit includes an increasing
Strong type N-type metal-oxide semiconductor fieldeffect transistor NMOSFET, two electric capacity, three resistance, pole-zero compensation circuit
Input be connected with the outfan of core circuit, the outfan of pole-zero compensation circuit is connected to core circuit through resistance, for
Core circuit provides bias voltage.
Compared with prior art the invention have the advantages that
1st, the present invention utilizes positive temperature coefficient voltage generation circuit, produces the road voltage with positive temperature coefficient, profit
Start positive temperature coefficient voltage generation circuit by depletion type NMOS tube, it is not necessary to extra start-up circuit, overcome in prior art
Each road and the current source circuit of temperature proportional relation are required for complicated the lacking of circuit structure that extra start-up circuit causes
Point, greatly simplifies circuit structure.
2nd, the present invention utilizes core circuit to compensate positive temperature coefficient voltage generation circuit, MOSFET element work in circuit
In saturation region or linear zone, overcome MOSFET element is biased in by prior art subthreshold region can make circuit response speed
Spend slack-off, thus reduce the operating frequency of circuit, the shortcoming increasing the temperature coefficient of reference voltage so that the operating frequency of circuit
It is improved, and the varying less of reference voltage when the temperature varies.
3rd, the present invention utilizes pole-zero compensation circuit that the reference voltage of output is carried out zero pole point compensation, overcomes existing
The shortcoming lacking pole-zero compensation circuit in technology so that the output of the present invention keeps stable.
Accompanying drawing explanation
Fig. 1 is the electrical schematic diagram of the present invention；
Fig. 2 is the temperature characterisitic analogous diagram of the present invention；
Fig. 3 is the Transient figure of the present invention.
Detailed description of the invention
The present invention will be further described below in conjunction with the accompanying drawings.
With reference to Fig. 1, the physical circuit of the present invention is further described.
It is divided into positive temperature coefficient voltage to produce the electrical schematic diagram of the present invention by the dotted line in electrical schematic diagram Fig. 1 of the present invention
Circuit, core circuit, pole-zero compensation circuit three part.
The positive temperature coefficient voltage generation circuit described by dotted portion in electrical schematic diagram Fig. 1 of the present invention, including two
Individual p-type metal-oxide semiconductor fieldeffect transistor PMOSFET 8 and 9, two enhancement mode N-type metal-oxides-partly lead
Body field-effect transistor NMOSFET 2 and 7, two depletion type N-type metal-oxide semiconductor fieldeffect transistor NMOSFET
3 and 5, the outfan of positive temperature coefficient voltage generation circuit is connected with the input of core circuit.
The source electrode of first NMOS tube 5 in positive temperature coefficient voltage generation circuit respectively with its grid, common GND
Connect.The drain electrode of first NMOS tube 5 respectively with the source electrode of second NMOS tube 7, the grid of first PMOS 8, second
In the grid of PMOS 9, core circuit, in the grid of first PMOS 10, core circuit, the grid of second PMOS 11 connects
Connect.The drain electrode of second NMOS tube 7 is connected with supply voltage VDD, the grid of second NMOS tube 7 respectively with the 3rd NMOS tube
The drain electrode of 2, the drain electrode of second PMOS 9 connect.The drain electrode of the source electrode of the 3rd NMOS tube 2 and the 4th NMOS tube 3 connects,
The grid of the 3rd NMOS tube 2 respectively with second NMOS tube in the grid of first NMOS tube 1, core circuit in core circuit
The grid of 4 connects.The grid of the 4th NMOS tube 3 is connected with its source electrode, common GND respectively.The source of first PMOS 8
Pole is connected with supply voltage VDD, and the drain electrode of first PMOS 8 is connected with the source electrode of second PMOS 9.
The core circuit described by dotted portion in electrical schematic diagram Fig. 1 of the present invention, including two p-type metal-oxides
Thing-semiconductor field effect transistor PMOSFET 10 and 11, two enhancement mode N-type Metal-oxide-semicondutor field effect transistors
Pipe NMOSFET 1 and 4, the input of core circuit is connected with the outfan of positive temperature coefficient voltage generation circuit, core circuit
Outfan be connected with the input of pole-zero compensation circuit.
The source electrode of first PMOS 10 in core circuit is connected with supply voltage VDD, the grid of first PMOS 10
Pole respectively with the grid of first PMOS 8, just temperature in the grid of second PMOS 11, positive temperature coefficient voltage generation circuit
Second NMOS tube 7 in the grid of second PMOS 9, positive temperature coefficient voltage generation circuit in degree coefficient voltages generation circuit
Source electrode, in positive temperature coefficient voltage generation circuit the drain electrode of first NMOS tube 5 connect, the drain electrode of first PMOS 10 with
The source electrode of second PMOS 11 connects.The drain electrode of second PMOS 11 respectively with drain electrode, the zero pole point of first NMOS tube 1
Compensate the grid of NMOS tube 6 in circuit to connect.The drain electrode of the source electrode of first NMOS tube 1 and second NMOS tube 4 connects, and first
The grid of individual NMOS tube 1 respectively with the 3rd NMOS tube in the grid of second NMOS tube 4, positive temperature coefficient voltage generation circuit
Resistance R in the grid of 2, pole-zero compensation circuit2, resistance R3 connects in pole-zero compensation circuit.The source electrode of second NMOS tube 4
It is connected with common GND.
The pole-zero compensation circuit described by dotted portion in electrical schematic diagram Fig. 1 of the present invention, including enhancement mode N
6, two electric capacity C of type metal-oxide semiconductor fieldeffect transistor NMOSFET1With C2, three resistance R1、R2With R3, zero pole
Point compensates the input of circuit and is connected with the outfan of core circuit, and the outfan of pole-zero compensation circuit is through resistance R2It is connected to
Core circuit, provides bias voltage for core circuit.
The grid of the NMOS tube 6 in pole-zero compensation circuit respectively with resistance R1, second PMOS 11 in core circuit
Drain electrode, in core circuit the drain electrode of first NMOS tube 1 connect, the drain electrode of NMOS tube 6 is connected with supply voltage VDD, NMOS
The source electrode of pipe 6 respectively with electric capacity C2, resistance R2Connect.Resistance R1With electric capacity C1Series connection, respectively with the grid of NMOS tube 6, publicly
End GND connects.Resistance R2With resistance R3Series connection, then with electric capacity C2Parallel connection, source electrode, common GND with NMOS tube 6 connect respectively
Connect.
Below in conjunction with analogous diagram, the effect of the present invention is further described.
1. simulated conditions:
The emulation experiment of the present invention is based on MaxChip_0.18 μm CMOS technology, application Cadence software
HspiceD emulation tool.Temperature characterisitic emulation and Transient is carried out respectively during emulation.During temperature characterisitic emulation, supply voltage
Being set as 5V, simulated temperature is-40 DEG C～125 DEG C；During Transient, simulation time is set to 1ms, and simulated temperature is set to often
Temperature (25 DEG C), supply voltage rises to 5V.
2. emulation content:
Under LINUX operating system, based on MaxChip_0.18 μm CMOS technology, application Cadence software
HspiceD emulation tool carries out temperature characterisitic emulation and Transient respectively to this reference voltage source.During temperature characterisitic emulation, electricity
Source voltage is set to 5V, and simulated temperature scope, from-40 DEG C～125 DEG C, rationally arranges device parameters, makes reference voltage in this temperature
In the range of meet the requirement of zero-temperature coefficient characteristic；During Transient, simulation time is set to 1ms, and simulated temperature is set to room temperature (25
DEG C), supply voltage rises to 5V, rationally arranges device parameters, makes reference voltage can have quickly response in this process.Rationally
The parameter of each device of pole-zero compensation circuit is set, makes reference voltage remain stable.
3. analysis of simulation result:
Analogous diagram Fig. 2 of the present invention is temperature characterisitic analogous diagram.Axis of abscissas in Fig. 2 represents temperature, axis of ordinates generation
Table voltage.From analogous diagram Fig. 2 of the present invention, the abscissa of some M0 is-82.85 DEG C, represents when temperature is at-40 DEG C～125
In the range of DEG C, during change, at the maxima and minima 2 of reference voltage, the difference of temperature is 82.85 DEG C, the vertical coordinate of some M0
It is 999.5 μ V, represents when temperature changes in the range of-40 DEG C～125 DEG C at the maxima and minima 2 of reference voltage
The difference of voltage is 999.5 μ V.The abscissa of some M2 is 25 DEG C, and vertical coordinate is 1.313V, represents when temperature is 25 DEG C, benchmark
The size of voltage is 1.313V.Being computed, the temperature coefficient of reference voltage is 4.6ppm/ DEG C, meets reference voltage zero-temperature coefficient special
The requirement of property.
Analogous diagram Fig. 3 of the present invention is the analogous diagram of Transient.Axis of abscissas in Fig. 3 represents time, axis of ordinates
Represent voltage.From analogous diagram Fig. 3 of the present invention, the abscissa of some M0 is 17.69 μ s, and vertical coordinate is 1.313V, represents
During 17.69 μ s, the size of reference voltage is 1.313V.Analogous diagram Fig. 3 of the present invention shows, rises to the mistake of 5V on the supply voltage
Cheng Zhong, reference voltage has quickly response, rises very rapidly up to 1.313V, and remains stable, meets reference voltage and quickly ring
The requirement answered and stability requirement.Being computed, when supply voltage is 5V, the power consumption of this reference voltage is 15.7 μ W, meets base
The requirement of quasi-voltage low-power consumption.
Above-mentioned simulation result shows, instant invention overcomes in prior art that circuit structure is complicated, temperature coefficient is higher, circuit
The shortcomings such as response speed is slow, within the scope of the widest temperature, the change of reference voltage is little, response is fast, stability is high, low in energy consumption,
Meet the requirement of reference voltage source performance indications.
Claims (4)
1. a full MOSFET reference voltage source for Low Drift Temperature, including positive temperature coefficient voltage generation circuit, core circuit, zero pole
Point compensates circuit, it is characterised in that described positive temperature coefficient voltage generation circuit includes two p-type metal-oxides-partly lead
Body field-effect transistor PMOSFET (8) and (9), two enhancement mode N-type metal-oxide semiconductor fieldeffect transistors
NMOSFET (2) and (7), two depletion types N-type metal-oxide semiconductor fieldeffect transistor NMOSFET (3) and (5), just
Temperaturecoefficient voltage produces the outfan of circuit and is connected with the input of core circuit；Described core circuit includes two p-type gold
Genus-Oxide-Semiconductor Field effect transistor PMOSFET (10) and (11), two enhancement mode N-type Metal-oxide-semicondutors
Field-effect transistor NMOSFET (1) and the outfan of (4), the input of core circuit and positive temperature coefficient voltage generation circuit
Connecting, the outfan of core circuit is connected with the input of pole-zero compensation circuit；Described pole-zero compensation circuit includes one
Enhancement mode N-type metal-oxide semiconductor fieldeffect transistor NMOSFET (6), two electric capacity C1With C2, three resistance R1、R2
With R3, the input of pole-zero compensation circuit is connected with the outfan of core circuit, and the outfan of pole-zero compensation circuit is through electricity
Resistance R2It is connected to core circuit, provides bias voltage for core circuit.
The full MOSFET reference voltage source of a kind of Low Drift Temperature the most according to claim 1, it is characterised in that: described positive temperature
Degree coefficient voltages produces first NMOS tube (5) in circuit and the 4th NMOS tube (3) is depletion type NMOS tube, first
The source electrode of NMOS tube (5) is connected with its grid, common GND respectively；The drain electrode of first NMOS tube (5) respectively with second
In the source electrode of NMOS tube (7), the grid of first PMOS (8), the grid of second PMOS (9), core circuit first
In the grid of PMOS (10), core circuit, the grid of second PMOS (11) connects；The drain electrode of second NMOS tube (7) with
Supply voltage VDD connects, the grid of second NMOS tube (7) respectively with drain electrode, second PMOS of the 3rd NMOS tube (2)
(9) drain electrode connects；The drain electrode of the source electrode of the 3rd NMOS tube (2) and the 4th NMOS tube (3) connects, the 3rd NMOS tube
(2) grid respectively with the grid of second NMOS tube (4) in the grid of first NMOS tube (1), core circuit in core circuit
Pole connects；The grid of the 4th NMOS tube (3) is connected with its source electrode, common GND respectively；The source of first PMOS (8)
Pole is connected with supply voltage VDD, and the drain electrode of first PMOS (8) is connected with the source electrode of second PMOS (9).
The full MOSFET reference voltage source of a kind of Low Drift Temperature the most according to claim 1, it is characterised in that: described core
In circuit, the source electrode of first PMOS (10) is connected with supply voltage VDD, and the grid of first PMOS (10) is respectively with
The grid of first PMOS (8), positive temperature coefficient in the grid of two PMOS (11), positive temperature coefficient voltage generation circuit
Second NMOS tube (7) in the grid of second PMOS (9), positive temperature coefficient voltage generation circuit in voltage generation circuit
In source electrode, positive temperature coefficient voltage generation circuit, the drain electrode of first NMOS tube (5) connects, the drain electrode of first PMOS (10)
It is connected with the source electrode of second PMOS (11)；The drain electrode of second PMOS (11) respectively with the leakage of first NMOS tube (1)
In pole, pole-zero compensation circuit, the grid of NMOS tube (6) connects；The source electrode of first NMOS tube (1) and second NMOS tube (4)
Drain electrode connect, the grid of first NMOS tube (1) produces with the grid of second NMOS tube (4), positive temperature coefficient voltage respectively
Resistance R in the grid of the 3rd NMOS tube (2), pole-zero compensation circuit in raw circuit2, resistance R in pole-zero compensation circuit3Even
Connect；The source electrode of second NMOS tube (4) is connected with common GND.
The full MOSFET reference voltage source of a kind of Low Drift Temperature the most according to claim 1, it is characterised in that: zero described pole
Point compensate in circuit the grid of NMOS tube (6) respectively with resistance R1, the drain electrode of second PMOS (11), core in core circuit
In circuit, the drain electrode of first NMOS tube (1) connects, and the drain electrode of NMOS tube (6) is connected with supply voltage VDD, NMOS tube (6)
Source electrode respectively with electric capacity C2, resistance R2Connect；Resistance R1With electric capacity C1Series connection, respectively with grid, the common of NMOS tube (6)
GND connects；Resistance R2With resistance R3Series connection, then with electric capacity C2Parallel connection, source electrode, common GND with NMOS tube (6) connect respectively
Connect.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113296571A (en) * | 2021-07-27 | 2021-08-24 | 上海南麟集成电路有限公司 | Reference voltage source circuit |
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