CN106226963A - A kind of array base palte, display floater and display device - Google Patents
A kind of array base palte, display floater and display device Download PDFInfo
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- CN106226963A CN106226963A CN201610601460.9A CN201610601460A CN106226963A CN 106226963 A CN106226963 A CN 106226963A CN 201610601460 A CN201610601460 A CN 201610601460A CN 106226963 A CN106226963 A CN 106226963A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
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- Microelectronics & Electronic Packaging (AREA)
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- Optics & Photonics (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
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Abstract
nullThe invention discloses a kind of array base palte、Display floater and display device,Periphery cabling in the non-display area of array base palte include in sector arrangement at least two group the first cablings and with each first cabling one_to_one corresponding and the second cabling of the fold-line-shaped of electric connection,Compared with the structure arranged in sector overall with the periphery cabling in the non-display area of existing array base palte,The negligible amounts of each the first cabling comprised in one group of first cabling of arrangement in sector,Often organize the first cabling being positioned at zone line in the first cabling less with the resistance difference of the first cabling being positioned at two side areas,It is easy to the length by increasing the first cabling in zone line or increases the live width of the first cabling in two side areas to realize often organizing the resistance of each first cabling in the first cabling equal,And,The length of each second cabling is equal and live width is equal,The resistance of the most each second cabling is equal,Therefore,The resistance difference of periphery cabling can be compensated well for.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of array base palte, display floater and display device.
Background technology
In existing display floater, organic EL display panel (Organic Light Emitting Diode,
OLED) have that preparation technology is simple, low cost, luminous efficiency high and is easily formed the advantages such as flexible structure;Display panels
(Liquid Crystal Display, LCD) have low in energy consumption, display quality is high, electromagnetic-radiation-free and applied range etc.
Advantage.
As a example by display panels, generally comprise array base palte, opposite substrate and the liquid crystal between two substrates
Layer.Array base palte, generally comprises viewing area and surrounds the non-display area of viewing area;Wherein, general in viewing area
It is provided with pixel and for transmitting the holding wire of signal, such as, grid line, data wire, it is provided with in non-display area for inciting somebody to action
Holding wire in viewing area is connected to the periphery cabling of drive circuit, and such as, grid line is connected to grid by periphery cabling and drives
Galvanic electricity road, data wire is connected to source electrode drive circuit by periphery cabling.
In the non-display area of array base palte, as it is shown in figure 1, periphery cabling 100 is arranged in sector, it is positioned at zone line
The length of the periphery cabling 100 in a is less than the length of the periphery cabling 100 being positioned at two side areas b so that be positioned at zone line
The resistance of the periphery cabling 100 in a is less than being positioned at the resistance of periphery cabling 100 of two side areas b, so, can cause with in
Between the holding wire that is electrically connected with of periphery cabling 100 in a of region receive time delay of signal less than and the week in two side areas b
Limit cabling 100 be electrically connected with holding wire receive signal time delay, thus can cause in viewing area with zone line a pair
The charging duration answering the pixel in region is more than the charging duration with the pixel in two side areas b corresponding region, and then causes showing
Show in region with the display brightness of zone line a corresponding region more than the display brightness with two side areas b corresponding region, make display
It is bad that panel produces various displays.
The method of existing compensation periphery trace resistances difference has two kinds: a kind of is by increasing the periphery in zone line
The length of cabling increases the resistance of the periphery cabling in zone line, and another kind is to be walked by the periphery in increase two side areas
The live width of line reduces the resistance of the periphery cabling in two side areas.But, along with the improving constantly of resolution of display floater,
In display floater, the quantity of pixel gets more and more, and correspondingly the quantity of holding wire and periphery cabling also gets more and more, so, middle
The resistance difference of the periphery cabling in region and the periphery cabling in two side areas can be increasing, it is clear that above two method
Can not compensate well for the resistance difference of periphery cabling.
Summary of the invention
In view of this, a kind of array base palte, display floater and display device are embodiments provided, in order to well
Compensate the resistance difference of periphery cabling.
Therefore, embodiments provide a kind of array base palte, including: viewing area and non-display area;Wherein, institute
There is in stating non-display area the periphery cabling that the holding wire in described viewing area is electrically connected to driving chip;
Described periphery cabling include in sector arrangement at least two group the first cablings and with each described first cabling one a pair
Second cabling of the fold-line-shaped that should and be electrically connected with;Wherein,
The resistance of each described first cabling is equal, is electrically connected with described holding wire;
The length of each described second cabling is equal and live width is equal, is electrically connected with described driving chip.
In a kind of possible implementation, in the above-mentioned array base palte that the embodiment of the present invention provides, each described first
The length of cabling is equal and live width is equal.
In a kind of possible implementation, in the above-mentioned array base palte that the embodiment of the present invention provides, every described the
One cabling include the first sub-cabling being electrically connected with corresponding described second cabling and with described holding wire be electrically connected with the
Two sub-cablings;
Often organize in described first cabling, every described first sub-cabling be shaped as straight line, each described first sub-cabling
Extended line converges to a little less, and convergent point is positioned at each described first sub-cabling near the side of described driving chip, along described
The arragement direction of the first cabling, the length of described first sub-cabling is first gradually reduced and is gradually increased afterwards;
Often organize in described first cabling, be positioned at zone line described second sub-cabling be shaped as curve, be positioned at two
Described second sub-cabling in side region be shaped as straight line, along the arragement direction of described first cabling, described second sub-cabling
Length be first gradually increased and be gradually reduced afterwards.
In a kind of possible implementation, in the above-mentioned array base palte that the embodiment of the present invention provides, often organize described the
In one cabling, along the arragement direction of described first cabling, the live width of described first cabling is first gradually reduced and is gradually increased afterwards, described
The length of the first cabling is first gradually reduced and is gradually increased afterwards.
In a kind of possible implementation, in the above-mentioned array base palte that the embodiment of the present invention provides, every described the
One cabling include the first sub-cabling being electrically connected with corresponding described second cabling and with described holding wire be electrically connected with the
Two sub-cablings;
Often organize in described first cabling, every described first sub-cabling be shaped as straight line, each described first sub-cabling
Extended line converges to a little less, and convergent point is positioned at each described first sub-cabling near the side of described driving chip, along described
The arragement direction of the first cabling, the length of described first sub-cabling is first gradually reduced and is gradually increased afterwards;
Often organize in described first cabling, every described second sub-cabling be shaped as straight line, each described second sub-cabling
Length is equal.
In a kind of possible implementation, in the above-mentioned array base palte that the embodiment of the present invention provides, each group described the
The quantity of described first cabling comprised in one cabling is equal.
In a kind of possible implementation, in the above-mentioned array base palte that the embodiment of the present invention provides, described driving core
Sheet is gate driver circuit;
Described holding wire is grid line.
In a kind of possible implementation, in the above-mentioned array base palte that the embodiment of the present invention provides, described driving core
Sheet is source electrode drive circuit;
Described holding wire is data wire.
The embodiment of the present invention additionally provides a kind of display floater, including: the above-mentioned array base palte that the embodiment of the present invention provides.
The embodiment of the present invention additionally provides a kind of display device, including: the above-mentioned display floater that the embodiment of the present invention provides.
Above-mentioned array base palte, display floater and the display device that the embodiment of the present invention provides, the non-display area of array base palte
Periphery cabling in territory include in sector arrangement at least two group the first cablings and with each first cabling one_to_one corresponding and electrically connecting
Second cabling of the fold-line-shaped connect, with the periphery cabling entirety arrangement in sector in the non-display area of existing array base palte
Structure is compared, the negligible amounts of each the first cabling comprised in one group of first cabling of arrangement in sector, often organizes the first cabling
In to be positioned at the first cabling of zone line less with the difference in length of the first cabling being positioned at two side areas, often group first is walked
The first cabling being positioned at zone line in line is less with the resistance difference of the first cabling being positioned at two side areas, it is easy to logical
The length crossing the first cabling increased in zone line or the live width increasing the first cabling in two side areas realize often organizing the
The resistance of each first cabling in one cabling is equal, and, the length of each second cabling is equal and live width is equal, and the most each second walks
The resistance of line is equal, therefore, it can compensate well for the resistance difference of periphery cabling, it is to avoid owing to periphery cabling exists resistance difference
Different and that cause display is bad.
Accompanying drawing explanation
Fig. 1 is the structural representation of the periphery cabling in existing array base palte;
Fig. 2-Fig. 4 is respectively the structural representation of the periphery cabling in the array base palte that the embodiment of the present invention provides.
Detailed description of the invention
Below in conjunction with the accompanying drawings, the concrete reality to array base palte, display floater and the display device that the embodiment of the present invention provides
The mode of executing is described in detail.
A kind of array base palte that the embodiment of the present invention provides, including: viewing area and non-display area;Wherein, such as Fig. 2 and
Shown in Fig. 3, there is in non-display area the periphery cabling 2 that the holding wire in viewing area is electrically connected to driving chip 1;
Periphery cabling 2 includes that in sector (Fig. 2 and Fig. 3 is shown respectively two group first at least two group the first cablings 21 of arrangement
Cabling) and with each first cabling 21 one_to_one corresponding and the second cabling 22 of the fold-line-shaped of electric connection;Wherein,
The resistance of each first cabling 21 is equal, is electrically connected with holding wire;
The length of each second cabling 22 is equal and live width is equal, is electrically connected with driving chip 1.
The embodiment of the present invention provide above-mentioned array base palte, the periphery cabling in the non-display area of array base palte include in
At least two group the first cablings of fan-shaped arrangement and with each first cabling one_to_one corresponding and the second cabling of the fold-line-shaped of electric connection,
Overall with the periphery cabling in the non-display area of existing array base palte in sector compared with the structure of arrangement, each arrange in sector
The negligible amounts of the first cabling comprised in one group of first cabling of cloth, often organizes and is positioned at the first of zone line in the first cabling
Cabling is less with the difference in length of the first cabling being positioned at two side areas, often organizes and is positioned at the of zone line in the first cabling
One cabling is less with the resistance difference of the first cabling being positioned at two side areas, it is easy to by increasing by first in zone line
The length of cabling or the live width of the first cabling in two side areas of increasing realize often organizing each first cabling in the first cabling
Resistance is equal, and, the length of each second cabling is equal and live width is equal, and the resistance of the most each second cabling is equal, therefore, it can
Compensate well for the resistance difference of periphery cabling, it is to avoid the display caused owing to periphery cabling exists resistance difference is bad.
It should be noted that the above-mentioned array base palte that the embodiment of the present invention provides is particularly suited for high-resolution display surface
Plate, this is that in display floater, the quantity of pixel is the most owing to the resolution of display floater is the highest, and correspondingly holding wire and periphery are walked
The quantity of line is the most, and the difference in length of the periphery cabling in zone line and the periphery cabling in two side areas can be the biggest, in
Between the resistance difference of periphery cabling in region and the periphery cabling in two side areas can be the biggest, utilize the embodiment of the present invention to provide
Above-mentioned array base palte can improve the resistance difference of periphery cabling well.
In the specific implementation, in the above-mentioned array base palte that the embodiment of the present invention provides, can be according to the number of periphery cabling
Amount determines the group number of the first cabling of arrangement in sector of division, and such as, the quantity of periphery cabling is the most, arranging in sector of division
The group number of the first cabling of cloth is the most.
In the specific implementation, the above-mentioned array base palte that the embodiment of the present invention provides can apply to display panels
(Liquid Crystal Display,LCD);Or, the above-mentioned array base palte that the embodiment of the present invention provides can apply to
Organic electro luminescent display floater (Organic Light Emitting Diode, OLED), does not limits at this.Below the present invention
The embodiment be given all can apply to illustrate as a example by LCD by array base palte.
In the specific implementation, when the above-mentioned array base palte that the embodiment of the present invention provides is applied to LCD, driving chip is permissible
For gate driver circuit;Or, driving chip can also be source electrode drive circuit, does not limits at this.
In the specific implementation, in the above-mentioned array base palte that the embodiment of the present invention provides, it is raster data model at driving chip
During circuit, the holding wire being positioned at viewing area is then grid line, and grid line is electrically connected to gate driver circuit by periphery cabling,
Gate driver circuit can load gated sweep signal to each grid line.Specifically, gate driver circuit can be bound to array base
In the non-display area of plate.
In the specific implementation, in the above-mentioned array base palte that the embodiment of the present invention provides, it is source drive at driving chip
During circuit, the holding wire being positioned at viewing area is then data wire, and data wire is electrically connected to source drive by periphery cabling
Circuit, source electrode drive circuit can load grayscale signal to each data wire.Specifically, source electrode drive circuit can be directly arranged at
In the non-display area of array base palte.
In the specific implementation, in the above-mentioned array base palte that the embodiment of the present invention provides, in order to realize each first cabling
Resistance is equal, specifically can arrange structure by following two and realize: can be set to equal by the length of each first cabling
And live width is set to equal;Or, it is also possible in often organizing the first cabling, along the arragement direction of the first cabling, by the first cabling
Live width be set to first be gradually reduced be gradually increased afterwards, be set to first be gradually reduced be gradually increased afterwards by the length of the first cabling;
Do not limit at this.
The above-mentioned array base palte provided the embodiment of the present invention below by two concrete examples applies above-mentioned two respectively
Plant specific implementation when arranging structure to be described in detail.
Example one: the length of each first cabling is equal and live width is equal.
As in figure 2 it is shown, every first cabling 21 includes and the first sub-cabling 211 of the second corresponding cabling 22 electric connection
And with holding wire be electrically connected with the second sub-cabling 212;Often organize in the first cabling 21, being shaped as of every first sub-cabling 211
Straight line, the extended line of each first sub-cabling 211 converges to a little less, and convergent point is positioned at each first sub-cabling 211 near driving
The side of chip 1, the arragement direction along the first cabling 21 (is i.e. perpendicular to the bearing of trend of the second sub-cabling 212, as shown in Figure 2
Arrow shown in direction), the length of the first sub-cabling 211 is first gradually reduced and is gradually increased afterwards;Often organize in the first cabling 21, be positioned at
The second sub-cabling 212 in zone line a ' be shaped as curve, be positioned at two side areas b ' the shape of the second sub-cabling 212
For straight line, the arragement direction along the first cabling 21 (is i.e. perpendicular to the bearing of trend of the second sub-cabling 212, arrow as shown in Figure 2
Shown direction), the length of the second sub-cabling 212 is first gradually increased and is gradually reduced afterwards;Thereby may be ensured that and often organize the first cabling 21
In the length of each first cabling 21 equal.
Certainly, first it is gradually increased is gradually reduced afterwards to realize the length of the second sub-cabling, be not limited to as shown in Figure 2
The will be located in zone line a ' second sub-cabling 212 be shaped to curve, will be located in two side areas b ' in second
Sub-cabling 212 is shaped to straight line, it is also possible to will be located in the in zone line second sub-cabling and is shaped to broken line,
Will be located in the in two side areas second sub-cabling and be shaped to straight line, do not limit at this.
It should be noted that in the above-mentioned array base palte that the embodiment of the present invention provides, often organize in the first cabling, mesozone
The each shared ratio of territory and two side areas can be configured according to actual needs, is not specifically limited at this.
It is preferred that in the above-mentioned array base palte that the embodiment of the present invention provides, can will each group of the first cabling comprise
The quantity of the first cabling is set to equal, in this manner it is ensured that respectively the effect of group the first cabling compensation resistance difference is identical, thus
The effect of Optimization Compensation periphery trace resistances difference further.
Example two: often organize in the first cabling, along the arragement direction of the first cabling, after the live width of the first cabling is first gradually reduced
Being gradually increased, the length of the first cabling is first gradually reduced and is gradually increased afterwards.
As it is shown on figure 3, every first cabling 21 includes and the first sub-cabling 211 of the second corresponding cabling 22 electric connection
And with holding wire be electrically connected with the second sub-cabling 212;Often organize in the first cabling 21, being shaped as of every first sub-cabling 211
Straight line, the extended line of each first sub-cabling 211 converges to a little less, and convergent point is positioned at each first sub-cabling 211 near driving
The side of chip 1, the arragement direction along the first cabling 21 (is i.e. perpendicular to the bearing of trend of the second sub-cabling 212, as shown in Figure 3
Arrow shown in direction), the length of the first sub-cabling 211 is first gradually reduced and is gradually increased afterwards;Often organize in the first cabling 21, every
Second sub-cabling 212 be shaped as straight line, the length of each second sub-cabling 212 is equal;Thereby may be ensured that and often organize the first cabling
In 21, the length of the first cabling 21 is first gradually reduced and is gradually increased afterwards.
It is preferred that in the above-mentioned array base palte that the embodiment of the present invention provides, can will each group of the first cabling comprise
The quantity of the first cabling is set to equal, in this manner it is ensured that respectively the effect of group the first cabling compensation resistance difference is identical, thus
The effect of Optimization Compensation periphery trace resistances difference further.
In the specific implementation, in the above-mentioned array base palte that the embodiment of the present invention provides, the second cabling of fold-line-shaped is not
It is confined to structure as shown in Figures 2 and 3, it is also possible to for structure as shown in Figure 4, do not limit at this.
Based on same inventive concept, the embodiment of the present invention additionally provides a kind of display floater, including: the embodiment of the present invention carries
The above-mentioned array base palte of confession.The enforcement of this display floater may refer to the embodiment of above-mentioned array base palte, the most superfluous in place of repetition
State.
Based on same inventive concept, the embodiment of the present invention additionally provides a kind of display device, carries including the embodiment of the present invention
The above-mentioned display floater of confession, this display device can be: mobile phone, panel computer, television set, display, notebook computer, number
Any product with display function such as photo frame, navigator or parts.The enforcement of this display device may refer to above-mentioned display surface
The embodiment of plate, repeats no more in place of repetition.
A kind of array base palte, display floater and the display device that the embodiment of the present invention provides, the non-display area of array base palte
Periphery cabling in territory include in sector arrangement at least two group the first cablings and with each first cabling one_to_one corresponding and electrically connecting
Second cabling of the fold-line-shaped connect, with the periphery cabling entirety arrangement in sector in the non-display area of existing array base palte
Structure is compared, the negligible amounts of each the first cabling comprised in one group of first cabling of arrangement in sector, often organizes the first cabling
In to be positioned at the first cabling of zone line less with the resistance difference of the first cabling being positioned at two side areas, it is easy to pass through
The length increasing the first cabling in zone line or the live width increasing the first cabling in two side areas realize often organizing first
The resistance of each first cabling in cabling is equal, and, the length of each second cabling is equal and live width is equal, the most each second cabling
Resistance equal, therefore, it can compensate well for the resistance difference of periphery cabling.
Obviously, those skilled in the art can carry out various change and the modification essence without deviating from the present invention to the present invention
God and scope.So, if these amendments of the present invention and modification belong to the scope of the claims in the present invention and equivalent technologies thereof
Within, then the present invention is also intended to comprise these change and modification.
Claims (10)
1. an array base palte, including: viewing area and non-display area;Wherein, have described in described non-display area
Holding wire in viewing area is electrically connected to the periphery cabling of driving chip;It is characterized in that:
Described periphery cabling include in sector arrangement at least two group the first cablings and with each described first cabling one_to_one corresponding and
Second cabling of the fold-line-shaped being electrically connected with;Wherein,
The resistance of each described first cabling is equal, is electrically connected with described holding wire;
The length of each described second cabling is equal and live width is equal, is electrically connected with described driving chip.
2. array base palte as claimed in claim 1, it is characterised in that the length of each described first cabling is equal and live width phase
Deng.
3. array base palte as claimed in claim 2, it is characterised in that every described first cabling includes and corresponding described the
The first sub-cabling that two cablings are electrically connected with and the second sub-cabling of being electrically connected with described holding wire;
Often organize in described first cabling, every described first sub-cabling be shaped as straight line, the prolongation of each described first sub-cabling
Line converges to a little less, and convergent point is positioned at each described first sub-cabling near the side of described driving chip, along described first
The arragement direction of cabling, the length of described first sub-cabling is first gradually reduced and is gradually increased afterwards;
Often organize in described first cabling, be positioned at zone line described second sub-cabling be shaped as curve, be positioned at two lateral areas
Described second sub-cabling in territory be shaped as straight line, along the arragement direction of described first cabling, the length of described second sub-cabling
Degree is first gradually increased and is gradually reduced afterwards.
4. array base palte as claimed in claim 1, it is characterised in that often organize in described first cabling, along described first cabling
Arragement direction, the live width of described first cabling is first gradually reduced and is gradually increased afterwards, and the length of described first cabling first gradually subtracts
It is gradually increased after little.
5. array base palte as claimed in claim 4, it is characterised in that every described first cabling includes and corresponding described the
The first sub-cabling that two cablings are electrically connected with and the second sub-cabling of being electrically connected with described holding wire;
Often organize in described first cabling, every described first sub-cabling be shaped as straight line, the prolongation of each described first sub-cabling
Line converges to a little less, and convergent point is positioned at each described first sub-cabling near the side of described driving chip, along described first
The arragement direction of cabling, the length of described first sub-cabling is first gradually reduced and is gradually increased afterwards;
Often organize in described first cabling, every described second sub-cabling be shaped as straight line, the length of each described second sub-cabling
Equal.
6. the array base palte as described in any one of claim 1-5, it is characterised in that the institute comprised in described first cabling of each group
The quantity stating the first cabling is equal.
7. the array base palte as described in any one of claim 1-5, it is characterised in that described driving chip is raster data model electricity
Road;
Described holding wire is grid line.
8. the array base palte as described in any one of claim 1-5, it is characterised in that described driving chip is source drive electricity
Road;
Described holding wire is data wire.
9. a display floater, it is characterised in that including: the array base palte as described in any one of claim 1-8.
10. a display device, it is characterised in that including: display floater as claimed in claim 9.
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