CN101728344A - Signal connection circuit capable of compensating difference of transmission time delay of routing signal - Google Patents
Signal connection circuit capable of compensating difference of transmission time delay of routing signal Download PDFInfo
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- CN101728344A CN101728344A CN200810167062A CN200810167062A CN101728344A CN 101728344 A CN101728344 A CN 101728344A CN 200810167062 A CN200810167062 A CN 200810167062A CN 200810167062 A CN200810167062 A CN 200810167062A CN 101728344 A CN101728344 A CN 101728344A
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Abstract
The invention relates to a signal connection circuit, which is provided with a plurality of symmetrically distributed routing lines; two ends of each routing line are connected with an input end and an output end respectively, wherein half of the routing lines are formed on a first metal layer, and are in a fan-out shape or parallel; and the other half of routing lines are formed on a second metal layer, and are also in a fan-out shape or parallel. The half of the routing lines and the other half of the routing lines are symmetrically distributed in a staggered way. The wiring mode makes the product of a resistance value and a capacitance value of each of the plurality of the routing lines almost equivalent; therefore, the transmission time delay of the signal in each routing line is also almost equivalent.
Description
Technical field
The present invention discloses a kind of connection line, refers to a kind of signal connecting line road that signal transmission time that online resistance and electric capacity causes postpones that compensates away especially.
Background technology
On traditional TFT LCD active assembly array substrate, fan-out line (fanout wire) is arranged between output and the input, distance is different each other because each output is with the input that is connected, therefore every difference in length that connects cabling is very big, and the length of cabling is proportional to the resistance of cabling, cause the resistance of every cabling and between two cablings formed electric capacity also all inequality.These differences can cause same signal different walk online transmission in, different time delay (t=5*R*C) is arranged.It is inconsistent that different time delays can cause each input to receive time of signal, causes the signal zero-time asynchronous, makes circuit produce unexpected error result.Please refer to Fig. 1, Fig. 1 is that previous not consideration waits the general output of RC distribution and the winding diagram of input.Comprise input 101-108 among Fig. 1, output 111-118, and cabling 121-128.By finding out this simple mode of connection that links input and output among Fig. 1, can make that the distance of intermediate traces 124 and 125 is the shortest, the resistance value minimum that causes cabling 124 and 125, and the distance of left and right sides cabling 121,122,127,128 is longer, causes the resistance value of cabling 121,122,127,128 bigger.If the resistance value of intermediate traces and left and right sides cabling has a long way to go, also very big with causing each bar to walk the difference of time delay of online signal transmission, and the result who leads to errors.Please refer to Fig. 2.Fig. 2 postpones comparison diagram according to the resulting signal transmission time of this wiring mode.At Fig. 2, the signal that it is high that input 101 and 104 transmits a standard is given output 111 and 114, signal transmission time postpones: t1=5*R1*C1, t4=5*R4*C4, wherein R1 is the resistance value on the cabling 121, C1 is the capacitance on the cabling 121, R4 is the resistance value on the cabling 124, C4 is the capacitance on the cabling 124, and t1 is that the signal transmission time on the cabling 121 postpones, and t4 is that the signal transmission time on the cabling 124 postpones.Because the length of cabling 121 is greater than cabling 124, so R1＞R4; But the zone that does not mutually overlap between each cabling, so have only lateral capacitance between cabling, but because the value of lateral capacitance is very little, so capacitor C 1 and C4 can be considered much at one, therefore calculates t1＞t4 according to aforesaid formula.The waveform of its output signal and input signal as shown in Figure 2, input signal (being represented by dotted lines) is a square wave, the waveform (representing with solid line) of output 111 and 114 output signal then has difference clearly.Clearly the signal as can be seen from Figure time t1＞t4 of accurate high of putting in place that rises.
In order to proofread and correct sort signal walking the difference of online propagation time delay, in traditional technology, the someone has proposed to wait the method for RC distribution.Please refer to Fig. 3.Fig. 3 is for having considered to wait the winding diagram of RC distribution in the prior art.Comprise input 201-208 among Fig. 3, output 211-218, and cabling 221-228.As shown in Figure 3, the designer adjusts the resistance value that its length increases or reduce cabling according to the situation of every cabling, and for example cabling 213,214,215,216 is designed to different zigzags to increase the length of cabling, with the purpose of RC distributions such as reaching among the figure.But the shortcoming of this design is: very difficult in the design, because the impedance furnishing unanimity of each bar cabling just must will be calculated the resistance value of every cabling.And the practice that increases the length of cabling also can cause the increase of design space, in circuit design now is under the trend of target with compact, the way of this increase track lengths on highdensity TFT LCD active assembly array substrate, implements difficult.This practice also has another kind of embodiment promptly to dwindle the practice of the live width of cabling with the impedance of increase cabling, but this kind practice can be meticulous because of lead, and causes the fraction defective of processing procedure to rise.Also have other increase building-out capacitor the practice of RC distribution such as to reach in the conventional practice, please refer to Fig. 4, Fig. 4 is one according to prior art, walks online increase by one building-out capacitor to adjust the RC value of this cabling at every.Comprise input 311-317 among Fig. 4, cabling 321-327, and the crooked cabling 331-337 in capacitor compensating circuit district, wherein crooked cabling 331-337 comprise formation building-out capacitor pattern 301-307 respectively.The advantage of this practice is can be according to the size of the resistance value of each bar cabling, adjust the capacitance of this cabling, as can be seen from Figure, the length of cabling 321-327 shortens gradually, just resistance value diminishes gradually, and building-out capacitor pattern 301-307 just increases gradually, makes the RC value of each bar cabling equate that signal does not have too big difference every time delay of walking online transmission.But this method equally needs to calculate the resistance value of every cabling, with the building-out capacitor value of the required increase of arranging in pairs or groups; And just in case the distribution of signal need change to some extent the time, whole distribution must redesign, and implements very trouble.
Comprehensive the above, in the middle of the practice of conventional art, if the purpose of RC distribution such as reach, the designer of TFT LCD active assembly array substrate must calculate the resistance value and the building-out capacitor value of each cabling, the computational process complexity, and must extra length or the building-out capacitor that increases lead on glass substrate, occupied the very big space of glass substrate, be not very desirable.
Summary of the invention
The invention discloses a kind of signal connecting line road that compensates cabling signal transmission time delay variance, include 2n output, 2n input, and the cabling of live width such as 2n bar.This 2n output, be positioned at a first metal layer, wherein the 1st individual to n output and (n+1) to 2n output along a center line left-right symmetric, and the 1st of this 2n output each output to n the output comprise a via, n is a positive integer.This 2n input, be positioned at this first metal layer, wherein the 1st individual to n input and (n+1) to 2n input along this center line left-right symmetric, and (n+1) individual each input to 2n input of this 2n input comprises a via.The cabling of live widths such as this 2n bar, wherein (n+1) bar to the 2n bar cabling of this 2n bar cabling is formed at this first metal layer, it is individual to 2n output that first end of (n+1) bar to the 2n bar cabling of this 2n bar cabling is connected to this (n+1), second end of this (n+1) bar to the 2n bar cabling is connected to the 1st to n input, the 1st of this 2n bar cabling k bar cabling to the n bar cabling comprises one and is formed at one second metal level and with respect to the via of a k output, one is formed at one second metal level and with respect to the via of one (n+k) individual input, one first circuit, one cabling line segment, and one second circuit.This first circuit is connected in one and is formed at this first metal layer and is positioned at the via of this k output and this is formed at this second metal level and with respect to the via of this k output.This cabling line segment is formed on this second metal level, is connected in this and is formed at this second metal level and is formed at this second metal level and with respect to the via of this (n+k) individual input with respect to the via of this k output and this.This second circuit is connected in the via that this is formed at this second metal level and is formed at this first metal layer and is positioned at this (n+k) individual input with respect to the via and of this (n+k) individual input.Wherein the distribution of the cabling line segment of the 1st of the distribution of (n+k) bar cabling in (n+1) bar to the 2n bar cabling of this 2n bar cabling and this 2n bar cabling k bar cabling to the n bar cabling is symmetrical and interlaced, and wherein k is the positive integer that is not more than n.
Description of drawings
Fig. 1 is the schematic diagram of the embodiment of a conventional practice;
Fig. 2 is one according to the resulting signal transmission time delay of traditional wiring mode figure;
Fig. 3 is the schematic diagram of the embodiment of another conventional practice;
Fig. 4 is the schematic diagram of the embodiment of other conventional practice;
Fig. 5 is the schematic diagram of embodiments of the invention;
Fig. 6 is the part via that waits the RC wiring diagram of first embodiment of the invention and the structural representation of metal level;
Fig. 7 be one according to the present invention resulting signal transmission time delay figure;
The resistance difference comparison diagram of Fig. 8 for painting according to table 1 and table 2.
[primary clustering symbol description]
1-8,111-118,211-218 output
11-18,101-108,201-208,311-317 input
61,62,63,64 first vias
71,72,73,74 second vias
41,42,43,44 the 3rd vias
51,52,53,54 the 4th vias
21-28,121-128,221-228,321-327 cabling
The crooked cabling in 331-337 capacitor compensating circuit district
The M1 the first metal layer
M2 second metal level
The S substrate
The I insulating barrier
The P protective layer
The circuit that T electrically conducting transparent material is constituted
211-241 cabling line segment
301-307 building-out capacitor pattern
Embodiment
Please refer to Fig. 5.Fig. 5 is the wiring diagram such as RC such as grade of embodiments of the invention.Comprise 11,12,13,14,15,16,17,18,8 cabling 21,22,23,24,25,26,27,28, one the first metal layer M1 of 1,2,3,4,5,6,7,8,8 inputs of 8 outputs among Fig. 5, one second metal level M2.Wherein each output and input are formed at the first metal layer M1, and the center line of the center line of 8 outputs (just output 4 and 5 centre) and 8 inputs (just input 14 and 15 centre) is same straight line, and each output and input are along the mutual symmetric arrays of center line.Output 1,2,3,4 respectively comprises first via 61,62,63,64 that is formed at the first metal layer M1, and input 15,16,17,18 also respectively comprises second via 71,72,73,74 that is formed at the first metal layer M1.Cabling 21 comprises first circuit of a cabling line segment 211, the 3rd via 41, the 4th via 51, one cablings 21, and second circuit of a cabling 21.Cabling line segment 211 sees through the 3rd via 41, first via 61 and is connected in first circuit (figure does not show) of the cabling 21 that the electrically conducting transparent material that has specific pattern between two vias constituted, and is connected in output 1; And see through the 4th via 51, second via 71 and be connected in second circuit (figure does not show) of the cabling 21 that the electrically conducting transparent material that has specific pattern between two vias constituted, be connected in input 15.Cabling 22 comprises first circuit of a cabling line segment 221, the 3rd via 42, the 4th via 52, one cablings 22, and second circuit of a cabling 22.Cabling line segment 221 sees through the 3rd via 42, first via 62 and is connected in first circuit (figure does not show) of the cabling 22 that the electrically conducting transparent material that has specific pattern between two vias constituted, and is connected in output 2; And see through the 4th via 52, second via 72 and be connected in second circuit (figure does not show) of the cabling 22 that the electrically conducting transparent material that has specific pattern between two vias constituted, be connected in input 16.Cabling 23 comprises first circuit of a cabling line segment 231, the 3rd via 43, the 4th via 53, one cablings 23, and second circuit of a cabling 23.Cabling line segment 231 sees through the 3rd via 43, first via 63 and is connected in first circuit (figure does not show) of the cabling 23 that the electrically conducting transparent material that has specific pattern between two vias constituted, and is connected in output 3; And see through the 4th via 53, second via 73 and be connected in second circuit (figure does not show) of the cabling 23 that the electrically conducting transparent material that has specific pattern between two vias constituted, be connected in input 17.Cabling 24 comprises first circuit of a cabling line segment 241, the 3rd via 44, the 4th via 54, one cablings 24, and second circuit of a cabling 24.Cabling line segment 241 sees through the 3rd via 44, first via 64 and is connected in first circuit (figure does not show) of the cabling 24 that the electrically conducting transparent material that has specific pattern between two vias constituted, and is connected in output 4; And see through the 4th via 54, second via 74 and be connected in second circuit (figure does not show) of the cabling 24 that the electrically conducting transparent material that has specific pattern between two vias constituted, be connected in input 18.Cabling 25 connects output 5 and input 11, and cabling 26 connects output 6 and input 12, and cabling 27 connects output 7 and input 13, and cabling 28 connects output 8 and input 14.Cabling line segment 211,221,231,241, the 3rd via 41,42,43,44, and the 4th via 51,52,53,54 be formed at the second metal level M2, cabling 25,26,27,28 is formed at the first metal layer M1, and wide with cabling line segment 211,221,231,241.In Fig. 5, the cabling line segment 211-241 of the second metal level M2 is represented by dotted lines, and the cabling 25-28 of the first metal layer M1 represents with solid line.Output 1,2,3,4,5,6,7,8 is the viewing area on TFT LCD active assembly array substrate, input 11,12,13,14,15,16,17,18 is a terminal region on TFT LCD active assembly array substrate, and cabling 25,26,27,28 and cabling line segment 211,221,231,241 are lead district on TFT LCD active assembly array substrate.
Please refer to Fig. 6, Fig. 6 is the part via that waits the RC wiring diagram of first embodiment of the invention and the structural representation of metal level.Fig. 6 comprises the circuit T that one first via 61, the 3rd via, 41, one electrically conducting transparent materials are constituted, a protective layer P, an insulating barrier I, a first metal layer M1, one second metal level M2, and a substrate S.Substrate S is positioned at below, and the top covers the first metal layer M1.The top of the first metal layer M1 covers insulating barrier I, and substrate S does not have the top the first metal layer of covering M1 part, then directly covers insulating barrier I.Insulating barrier I top covers the second metal level M2, and the top of the second metal level M2 is protective mulch P then.Insulating barrier I does not have the second metal level M2 part of covering in the top, then direct protective mulch P.41 of the 3rd vias are directly to punch protective layer P, are connected in the second metal level M2; Similarly, first via 61 connects the first metal layer M1 for directly punching protective layer P and insulating barrier I.Between the first metal layer M1 and the second metal level M2, the circuit that has an electrically conducting transparent material with specific pattern to be constituted is connected to each other, conducting.This circuit with electrically conducting transparent material of specific pattern is made of the material of tin indium oxide (ITO) or indium zinc oxide (IZO).Similarly, between first via 62,63,64 and the 3rd via 42,43,44, and between second via 71,72,73,74 and the 4th via 51,52,53,54, also see through identical mode, connect respectively.
As shown in Figure 5, this kind span wire system can be so that the length of each bar cabling levels off to equally, so the resistance value of each bar cabling is also almost equal, has formed convergence constant resistance distribution.And this moment the right and left the cabling (left side: cabling line segment 211-241, the right: cabling 25-28) symmetry is also staggered and wide mutually, a zone that overlaps mutually that on TFT LCD active assembly array substrate, forms, and because this kind wiring mode, left-right symmetric, therefore each bar area convergence of walking online overlapping equates, form each bar walk online cabling capacitance also convergence equate.And because each bar is walked online resistance value and capacitance is all very approaching, so this kind wiring mode, compared with traditional wiring mode, can produce near the distribution that waits RC.Cabling line segment 211-241 and cabling 25-28 can be symmetrical in the fan-out shape (fan out) of center line (just output 4 and 5 centre) each other, or it is parallel to each other to be symmetrical in center line.Please note: in the present embodiment, the number of cabling, input and output etc., just an example is not to be used for limiting the present invention, and the number that the present invention can be applied to cabling, input and output etc. is any circuit of an even number.
Suppose that we will be by input 15 and 18 signals to output 1 and 4 output high position standards, then the signal transmission time delay according to computing formula is: t21=5*R21*C21, t24=5*R24*C24, wherein R21 is the resistance value on the cabling 21, C21 is the capacitance on the cabling 21, and R24 is the resistance value on the cabling 24, and C24 is the capacitance on the cabling 24, t21 is that the signal transmission time on the cabling 21 postpones, and t24 is that the signal transmission time on the cabling 24 postpones.Because it is equal that the length of cabling 21 and cabling 24 levels off to, so the resistance value of the R21 resistance value of R24 no better than; And the region area that overlaps mutually between each cabling is also almost equal, thus between each cabling electric capacity one much at one, promptly the capacitance of C21 also convergence equal the capacitance of C24.Then calculate the also approximate t24 of t21 according to aforesaid formula.Please refer to Fig. 7, Fig. 7 is resulting signal transmission time delay figure according to the present invention.The waveform of its output signal and input signal as shown in Figure 7, the input signal (being represented by dotted lines) that is transmitted by input 15 and 18 is a square wave, the waveform (representing with solid line) of output 1 and 4 input signal then much at one.Rise put in place the time t21 of accurate high of clearly signal as can be seen from Figure approximates t24.Respectively walk online signal rise to the position accurate high time more approaching, represent each input to receive the time unanimity of signal, the signal zero-time is synchronous, can prevent that more circuit from producing unexpected error result.
Please refer to following table 1, table 2 and the 8th figure.Table 1 is with reference to the track lengths of the traditional wired mode experiment measuring of figure 1 and the comparison sheet of resistance difference.Table 2 is with reference to the track lengths of the traditional wired mode experiment measuring of figure 5 and the comparison sheet of resistance difference.Fig. 8 is the resistance difference comparison diagram of painting according to table 1 and table 2.By can finding out in above three charts, according to the resistance value difference (23.84%) of 8 cablings that wiring mode of the present invention produced really much smaller than the resistance value difference (43%) of 8 cablings that wiring mode produced of traditional Fig. 1.
| Cabling | Track lengths (um) | Resistance difference % |
| Cabling 1 | ??4.96 | ??43.01 |
| |
??4.30 | ??23.61 |
| |
??3.76 | ??7.86 |
| Cabling 4 | ??3.48 | ??0.00 |
| |
??3.48 | ??0.00 |
| Cabling 6 | ??3.76 | ??7.86 |
| |
??1.30 | ??23.61 |
| Cabling 8 | ??1.98 | ??13.01 |
Table 1
| Cabling | Track lengths (um) | Resistance difference % |
| Cabling 1 | ??9.45 | ??23.64 |
| Cabling | Track lengths (um) | Resistance difference % |
| |
??10.45 | ??15.82 |
| |
??11.42 | ??8.72 |
| Cabling 4 | ??12.41 | ??0.00 |
| |
??12.41 | ??0.00 |
| Cabling 6 | ??11.42 | ??8.02 |
| |
??10.15 | ??15.82 |
| Cabling 8 | ??9.15 | ??23.81 |
Table 2
Please note: in the present embodiment, output 1-8, input 11-18 and cabling 25-28 are formed at the first metal layer M1 equally, cabling line segment 211-241 then is formed at the second metal level M2, but situation that the present invention is not limited to this, output, input and cabling can also be respectively at different metal levels, but see through via mutually and be connected the scope that this also contains for the present invention via first circuit and second circuit that the electrically conducting transparent material is constituted.
By The above results as can be known, wiring mode such as RC such as grade proposed by the invention, utilize even number bar cabling to fit over the symmetry of line at circuit, and carry out wiring at different metal interlevels, (for example output 1 connects input 15, but not in the similar conventional practice only to need the order of connection of change output and input, output 1 connects input 11), do not need additionally to remove to calculate each bar and walk online resistance capacitance value,, can obtain waiting the distribution of RC as long as distribution is finished.The present invention possess have design fast, the RC gap is little, revise advantages such as easy, and use two-layer different metal level to come distribution, also can be so that the increasing of the design space of cabling, the live width of cabling is widened, and walks line resistance and descends, and cabling is bigger at interval to each other, be more suitable for the highdensity application of cabling (for example resolution panels), these all are the advantages that is beyond one's reach in the prior art.Therefore the present invention one is applied to TFT LCD ARRAY side and IC pin position backguy part, or in the IC design, the optimal circuit wiring mode in place of inner distribution such as RC such as needs grade or the like.
The above only is preferred embodiment of the present invention, and all equalizations of doing according to claims of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (6)
1. the signal connecting line road that can compensate cabling signal transmission time delay variance is characterized in that, includes:
2n output, be positioned at a first metal layer, wherein the 1st individual to n output and (n+1) to 2n output along a center line left-right symmetric, and the 1st of this 2n output each output to n the output comprise a via, n is a positive integer;
2n input, be positioned at this first metal layer, wherein the 1st individual to n input and (n+1) to 2n input along this center line left-right symmetric, and (n+1) individual each input to 2n input of this 2n input comprises a via; And
The cabling of live widths such as 2n bar, wherein (n+1) bar to the 2n bar cabling of this 2n bar cabling is formed at this first metal layer, it is individual to 2n output that first end of (n+1) bar to the 2n bar cabling of this 2n bar cabling is connected to this (n+1), second end of this (n+1) bar to the 2n bar cabling is connected to the 1st to n input, and the 1st of this 2n bar cabling k bar cabling to the n bar cabling comprises:
One is formed at one second metal level and with respect to the via of a k output;
One is formed at one second metal level and with respect to the via of one (n+k) individual input;
One first circuit is connected in one and is formed at this first metal layer and is positioned at the via of this k output and this is formed at this second metal level and with respect to the via of this k output;
One cabling line segment is formed on this second metal level, is connected in this and is formed at this second metal level and is formed at this second metal level and with respect to the via of this (n+k) individual input with respect to the via of this k output and this; And
One second circuit is connected in the via that this is formed at this second metal level and is formed at this first metal layer and is positioned at this (n+k) individual input with respect to the via and of this (n+k) individual input;
The distribution of the cabling line segment of the distribution of (n+k) bar cabling in (n+1) bar to the 2n bar cabling of this 2n bar cabling and this 2n bar cabling the 1st the k bar cabling to the n bar cabling is symmetrical and interlaced, and wherein k is the positive integer that is not more than n.
2. as claims 1 described signal connecting line road, it is characterized in that first circuit and second circuit of the 1st of this 2n bar cabling k bar cabling to the n bar cabling are made of an electrically conducting transparent material.
3. as claims 1 described signal connecting line road, it is characterized in that the area convergence that is overlapped between the cabling line segment of (n+k) bar cabling in (n+1) bar to the 2n bar cabling of this 2n bar cabling and this 2n bar cabling the 1st the k bar cabling to the n bar cabling equates.
4. as claims 1 described signal connecting line road, it is characterized in that the length convergence of the cabling line segment of in (n+1) bar to the 2n bar cabling of this 2n bar cabling (n+k) bar cabling and this 2n bar cabling the 1st the k bar cabling to the n bar cabling equates.
5. as claims 1 described signal connecting line road, it is characterized in that (n+1) bar to the 2n bar cabling of this 2n bar cabling becomes the fan-out shape, the 1st of this 2n bar cabling to the n bar cabling dacron cabling line segment also become the fan-out shape.
6. as claims 1 described signal connecting line road, it is characterized in that (n+1) bar to the 2n bar cabling of this 2n bar cabling is parallel to each other, the 1st of this 2n bar cabling cabling line segment to the n bar cabling is also parallel to each other.
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