CN106206451B - Gate-division type flash memory device making method - Google Patents
Gate-division type flash memory device making method Download PDFInfo
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- CN106206451B CN106206451B CN201610596487.3A CN201610596487A CN106206451B CN 106206451 B CN106206451 B CN 106206451B CN 201610596487 A CN201610596487 A CN 201610596487A CN 106206451 B CN106206451 B CN 106206451B
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Abstract
The present invention provides a kind of gate-division type flash memory device making method, after the groove of the floating gate silicon nitride layer and the floating gate silicon nitride layer surface deposit certain thickness source line polysilicon layer, top flattening technique to the source line polysilicon layer is etched back to technique and carries out endpoint monitoring, with obtain the source line polysilicon layer in the width of the top of the groove or the loss height of first side wall, and after removing floating gate silicon nitride, according to the result of the monitoring, the side wall progress of the first side wall exposed is laterally etched back to accordingly, to expose the floating gate polysilicon layer of appropriate area, thus after guaranteeing the floating gate polysilicon layer that subsequent etching exposes, the floating gate tip with suitable height and corner angle can be obtained, the data of gate-division type flash memory device may finally be avoided to wipe failure and programming Problem of Failure.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of gate-division type flash memory device making methods.
Background technique
Flash memory, referred to as flash memory, are divided into two types: gatestack (stackgate) device and dividing grid
(splitgate) device, wherein divide gate device to form the wordline as erasing grid in the side of floating gate, wordline is as control
Grid, on wiping/writing performance, erasure effect, the circuit design excessively for dividing gate device to efficiently avoid gatestack device are relatively easy.And
And grid dividing structure is programmed using the injection of source thermoelectron, has higher programming efficiency, thus be widely used in all kinds of
In the electronic products such as smart card, SIM card, microcontroller, mobile phone.
Figure 1A is please referred to, Figure 1A is a kind of existing the schematic diagram of the section structure of typical gate-division type flash memory device, this point
Gate flash memory device includes: semiconductor substrate 10, drain region 111 and source region 112, source line polysilicon layer (Source Poly) 12, floats
Gate oxide 13, floating gate polysilicon layer (Floating gate Poly) 14, first side wall 151, the second side wall 152, tunnelling oxygen
Change layer (tunnel oxide) 16, word line polysilicon layer (Word Line Poly) 17 and wordline side wall 18, wherein floating gate is more
Crystal silicon layer (Floating gate Poly) 14 is used to form floating gate, with floating gate tip (Floating gate tip)
141, when carrying out data erasing (erase) or programming (program) to gate-division type flash memory device, arrived by floating gate tip 141
The electricity that F-N (Fowler-Nordheim) tunnel-effect release floating gate polysilicon layer 14 between word line polysilicon layer 17 is accumulated
Son makes floating gate polysilicon layer 14 capture electronics.In general, floating gate tip 141 is sharper, easier erasing, and floating gate is sharp
End 141 is shorter, and programming efficiency is higher, on the contrary, floating gate tip 141 is more blunt, is more unfavorable for wiping, floating gate tip 141 is higher, more not
Conducive to programming.
And in actual production, the production at floating gate tip 141 is not easy to, and needs to have sternly the critical size (CD) of front layer
The requirement of lattice.It please refers to Figure 1B, in common actual production technique, floating gate nitrogen can be formed on the surface of floating gate polysilicon layer 14
SiClx layer 19, source line polysilicon layer 12 can be deposited in the groove of floating gate silicon nitride layer 19 and the formation of floating gate polysilicon layer 14,
When forming floating gate tip, need to carry out the source line polysilicon layer 12 deposited top flattening (generally chemical machine in groove
Tool flatening process, CMP), which will have a direct impact on the shape and critical size of the first side wall 151, and then influence subsequent shape
At floating gate tip 141 height, and fewer first side wall 151 loss will form higher floating gate tip 141；Then, it goes
It is laterally etched back to except floating gate silicon nitride layer 19 and to the first side wall, to expose the floating gate polysilicon layer 14 of lower section, is finally done
The floating gate polysilicon layer 14 that method etching is exposed is to form floating gate tip 141, and in the step, the first side wall 151 side is to being etched back to
Thickness is bigger, and the more blunt the floating gate tip 141 of formation the shorter, easily causes the data erasing failure (Erase of gate-division type flash memory device
Fail), and 19 side of floating gate silicon nitride layer is smaller to the thickness being etched back to, and the sharper the floating gate tip 141 of formation the higher, easily causes
(program fail) is failed in the programming of gate-division type flash memory device.
Therefore, it is necessary to a kind of gate-division type flash memory device making methods, and it is suitably floating to be capable of forming height and corner angle
Grid tip, to avoid the data erasing failure and programming failure of gate-division type flash memory device.
Summary of the invention
The purpose of the present invention is to provide a kind of gate-division type flash memory device making methods, are capable of forming height and corner angle
Suitable floating gate tip, to avoid the data erasing failure and programming failure of gate-division type flash memory device.
To solve the above problems, the present invention proposes a kind of gate-division type flash memory device making method, comprising the following steps:
Semiconductor substrate is provided, floating gate oxide layers, floating gate polysilicon layer are sequentially formed in the semiconductor substrate and is floated
Grid silicon nitride layer, the floating gate oxide layers, floating gate polysilicon layer and floating gate silicon nitride layer, which are equipped with, exposes the semiconductor substrate
The groove on surface has the first side wall, the floating gate in the groove on the floating gate silicon nitride layer side wall in the groove
There is the second side wall on oxide layer and the floating gate polysilicon layer side wall；
In the groove and the floating gate silicon nitride layer surface sedimentary origin line polysilicon layer, the source line polysilicon layer
Deposition thickness can fill up the groove；
Top flattening is carried out to the source line polysilicon layer or is etched back to, until exposing the floating gate silicon nitride layer table
Face, and monitor the remaining source line polysilicon layer in the width of the top of the groove or the damage of monitoring first side wall
Consumption height；
Remove the floating gate silicon nitride layer, and according to the monitoring as a result, side to first side wall exposed
Wall progress is laterally etched back to accordingly, with the floating gate polysilicon layer of exposure lower section corresponding region；
Using first side wall as exposure mask, the floating gate oxygen of the floating gate polysilicon layer and lower section that expose is etched
Change layer, to obtain the FGS floating gate structure for having floating gate tip.
Further, the step of providing the semiconductor substrate include:
Semiconductor base is provided, sequentially forms the floating gate oxide layers, the floating gate polysilicon on the semiconductor base
Layer, the floating gate silicon nitride layer and graphical photoresist；
Using the graphical photoresist as exposure mask, etches the floating gate silicon nitride layer and stop at the floating gate polysilicon layer
Surface forms groove；
The graphical photoresist is removed, and using the floating gate silicon nitride layer as exposure mask, groove described in isotropic etching
In floating gate polysilicon layer to certain depth, for being subsequently formed floating gate tip；
The first side wall is formed in the floating gate silicon nitride layer of the groove and the inner sidewall of the floating gate polysilicon layer exposed；
Using first side wall as exposure mask, continue to etch the floating gate polysilicon layer and floating gate oxide layers in the groove,
Until exposing the semiconductor substrate surface of lower section；
The second side wall is formed on the inner sidewall of floating gate polysilicon layer and floating gate oxide layers in the trench.
Further, existed using line polysilicon layer in source described in the endpoint monitoring technical monitoring based on optical spectroscopic reflectivity
The width of the top of the groove or the loss height of monitoring first side wall.
Further, the hot phosphoric acid solution using temperature higher than 120 DEG C carrys out wet process and removes the floating gate nitrogen as corrosive liquid
SiClx layer, to expose the side wall of first side wall.
Further, using wet corrosion technique, the side wall of first side wall exposed is laterally etched back to.
Further, according to the monitoring as a result, adjusting at least one technological parameter of the wet corrosion technique, institute
The technological parameter for stating wet corrosion technique includes the concentration of corrosive liquid, temperature and etching time.
Further, the corrosive liquid of the wet corrosion technique is temperature between 40 DEG C~100 DEG C by ammonium hydroxide, double
The standard cleaning liquid that oxygen water and deionized water mix.
Further, the source line polysilicon layer monitored it is wider in the width of the top of the groove, or monitoring
Smaller, the thickness that the side wall of first side wall exposed is laterally etched back to of loss height of first side wall arrived
It spends bigger.
Further, the source line polysilicon layer monitored it is wider in the width of the top of the groove, or monitoring
Loss height smaller, the quarter that the side wall of first side wall exposed is laterally etched back to of first side wall arrived
It is longer to lose the time.
Compared with prior art, gate-division type flash memory device making method of the invention, in the ditch of the floating gate silicon nitride layer
After slot and the floating gate silicon nitride layer surface deposit certain thickness source line polysilicon layer, to the top of the source line polysilicon layer
Portion's flatening process or be etched back to technique carry out endpoint monitoring, with obtain the source line polysilicon layer in the top of the groove
Width or first side wall loss height, and after removing floating gate silicon nitride, according to the monitoring as a result, right
The side wall progress of first side wall exposed is laterally etched back to accordingly, to expose the floating gate polysilicon of appropriate area
Layer, to can obtain after guaranteeing the floating gate polysilicon layer that subsequent etching exposes with suitable height and corner angle
Floating gate tip may finally avoid the data of gate-division type flash memory device from wiping failure and programming Problem of Failure.
Detailed description of the invention
Figure 1A is a kind of the schematic diagram of the section structure of existing typical gate-division type flash memory device；
Figure 1B is the schematic diagram of the section structure in existing gate-division type flash memory device manufacturing processes；
Fig. 2 is the gate-division type flash memory device making method flow chart of the specific embodiment of the invention；
Fig. 3 A to Fig. 3 I is the cross-section structure signal in the gate-division type flash memory device making method of the specific embodiment of the invention
Figure.
Specific embodiment
To be clearer and more comprehensible the purpose of the present invention, feature, a specific embodiment of the invention is made with reference to the accompanying drawing
Further instruction, however, the present invention can be realized with different forms, it should not be to be confined to the embodiment described.
Referring to FIG. 2, the present invention provides a kind of gate-division type flash memory device making method, comprising the following steps:
S1 provides semiconductor substrate, be sequentially formed in the semiconductor substrate floating gate oxide layers, floating gate polysilicon layer and
Floating gate silicon nitride layer, the floating gate oxide layers, floating gate polysilicon layer and floating gate silicon nitride layer, which are equipped with, exposes the semiconductor lining
The groove of bottom surface has the first side wall on the floating gate silicon nitride layer side wall in the groove, described floating in the groove
There is the second side wall on gate oxide and the floating gate polysilicon layer side wall；
S2, in the groove and the floating gate silicon nitride layer surface sedimentary origin line polysilicon layer, the source line polysilicon
The deposition thickness of layer can fill up the groove；
S3 carries out top flattening to the source line polysilicon layer, until exposing the floating gate silicon nitride layer surface, and supervises
Survey the source line polysilicon layer in the width of the top of the groove or the loss height of monitoring first side wall；
S4 removes the floating gate silicon nitride layer, and according to the monitoring as a result, to first side wall exposed
Side wall progress is laterally etched back to accordingly, with the floating gate polysilicon layer of exposure lower section corresponding region；
S5 etches the floating gate oxide layers of the floating gate polysilicon layer and lower section that expose using first side wall as exposure mask,
To obtain the FGS floating gate structure for having floating gate tip.
The process for providing the semiconductor substrate in step sl is specific as follows:
Firstly, please referring to Fig. 3 A, semiconductor substrate 300 is provided, sequentially forms floating gate on the semiconductor base 300
Oxide layer 301, floating gate polysilicon layer 302, floating gate silicon nitride layer 303 and graphical photoresist layer 304.Wherein, described partly to lead
Body substrate 300 can be silicon substrate, silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator (SOI) substrate, germanium on insulator (GOI)
Substrate, glass substrate or III-V compound substrate (such as silicon nitrate substrate or gallium arsenide substrate), silicon carbide substrates or it is folded
Layer structure or diamond substrate, or well known to a person skilled in the art other semiconductive material substrates etc..Floating gate oxide layers 301
For isolation of semiconductor substrate 300 and floating gate polysilicon layer 302, thickness can be depending on specific process requirements, floating gate
Oxide layer 301 can be formed using depositing operation, such as chemical vapor deposition process (CVD), when the material of semiconductor base 300
When for silicon, the formation process of floating gate oxide layers 301 can also be thermal oxidation technology.Floating gate polysilicon layer 302 can be using deposition
Technique is formed, such as chemical vapor deposition process, can capture or lose electronics, so as to make finally formed sub-gate sudden strain of a muscle
Memory device has the function of to store and wipe；Floating gate silicon nitride layer 303 can be formed using depositing operation, such as chemical vapor deposition
Product technique.Graphical photoresist 304 is formed by photoetching processes such as coating, exposure, developments, for defining the position of floating gate formation
It sets, can be single layer structure or multilayered structure, when single layer structure can only include photoresist layer, and when multilayered structure may include
It covers the bottom anti-reflection layer of floating gate silicon nitride layer 303, the photoresist layer in bottom anti-reflection layer and is located at photoresist
Top anti-reflective layer on layer.
It then, is exposure mask, dry etching floating gate silicon nitride layer with the graphical photoresist 304 please continue to refer to Fig. 3 A
303 to 302 surface of floating gate polysilicon layer, by the pattern transfer of graphical photoresist 304 to floating gate silicon nitride layer 303, i.e., floating
Groove 303a is formed in grid silicon nitride layer 303, the region that the floating gate silicon nitride layer 303 of the two sides groove 303a is covered is subsequent portion
Divide the region of the formation such as floating gate and wordline.In the present embodiment, using the mixed gas of carbon fluorine gas and oxygen come dry etching
Floating gate silicon nitride layer 303, while guaranteeing 303 etch rate of floating gate silicon nitride layer and homogeneity, moreover it is possible to reduce etching
The polymer residue gathered on 303 side wall of floating gate silicon nitride layer in the process, the carbon fluorine gas includes CF4、CF3H、CF2H2、
CFH3、C3F8At least one of.Such as in the mixed gas of the carbon fluorine gas and oxygen, CF4Flow be 20sccm~
40sccm, CFH3Flow be 15sccm~20sccm；The flow of oxygen is 3sccm~7sccm.
Then, Fig. 3 B is please referred to, Oxygen plasma ashing technique and wet clean process can be used, remove the figure
Shape photoresist 304.The process gas in Oxygen plasma ashing technique in the present embodiment is also passed through in addition to oxygen
At least one of hydrogen, nitrogen or fluorine base gas, fluorine base gas therein can be NF3、CF4、C2F6At least one of.
The wet cleaning processes can first carry out 303 surface of floating gate silicon nitride layer using the mixed solution of sulfuric acid and hydrogen peroxide clear
It washes, then 303 surface of floating gate silicon nitride layer is cleaned with the mixed solution of ammonium hydroxide, hydrogen peroxide and water again.By above-mentioned etc.
After plasma ashing technique, the polymer residue of photoresist and etching formation is after the two steps cleaning that wet process is removed photoresist, energy
Enough thoroughly remove.In other embodiments of the invention, can also first user's hydrofluoric acid and sulfuric acid mixed solution or sulfuric acid
303 surface of floating gate silicon nitride layer is cleaned with the mixed solution of ozone, it is then molten with the mixing of ammonium hydroxide, hydrogen peroxide and water again
Liquid cleans 303 surface of floating gate silicon nitride layer, and essentially identical technical effect also may be implemented.
It then, is exposure mask, isotropic dry etch technique with the floating gate silicon nitride layer 303 please continue to refer to Fig. 3 B
Or wet-etching technology etches the floating gate polysilicon layer 302 in the groove 303a to certain depth, and make to expose
The floating gate polysilicon layer 302 forms curved surfaces, is ready for the ultimately forming for floating gate tip at the top of floating gate below,
The depth capacity of middle curved surfaces is H.
Then, Fig. 3 C is please referred to, first forms the first side wall 305 on the inner wall of the floating gate silicon nitride layer 303 of groove 303a.
In the present embodiment, the material of the first side wall 305 can be silica, to guarantee the first side in subsequent etching process
Etching selection ratio with higher between wall 305 and floating gate silicon nitride layer 303.The formation process of first side wall 305 may include:
The first side wall film layer is deposited on 303 surface of floating gate silicon nitride layer and 302 surface of floating gate polysilicon layer exposed (not show
Out)；The first side wall film layer is etched back to until exposing 302 surface of part floating gate polysilicon layer of bottom, and remaining institute
On the inner sidewall for stating floating gate silicon nitride layer 303 and floating gate polysilicon layer 302 that the first side wall film layer is covered in groove 303a,
Form the first side wall 305.In the present embodiment, the thickness of floating gate silicon nitride layer 303 determines the height of the first side wall 305, then
Determine the height of subsequent source line polysilicon layer and word line polysilicon layer.And in a certain range, the word line polysilicon layer is got over
Height, the performance for being formed by flash memories is more excellent, therefore, the thickness of floating gate silicon nitride layer 303 can for 1500 angstroms~
4500 angstroms.
Then, Fig. 3 D is please referred to, is exposure mask with the first side wall 305, continues to etch the groove using dry etch process
Floating gate polysilicon layer 302 and floating gate oxide layers 301 in 303a to 300 surface of semiconductor base, groove 303a bottom-exposed
300 surface of semiconductor base is total area surface.
Then, the floating gate polysilicon layer 302 and floating gate oxide layers please continue to refer to Fig. 3 D, in the groove 303a
301 surroundings formed the second side wall 306, the second side wall 306 can cover simultaneously the first side wall 305 exposure surface, first
Side wall 305 and the second side wall 306 constitute floating gate side wall.The material of second side wall 306 is silicon oxide or silicon nitride, the second side wall
306 can protect floating gate polysilicon layer 302 and floating gate to aoxidize in the source region ion implantation process of subsequent semiconductor base 300
Layer is 301 injury-free, is exposure mask with the first side wall 305 and the second side wall 306, the semiconductor base 300 that lower section is exposed into
Row ion implanting forms the technique that source region (not shown) so far completes offer semiconductor substrate in step S1.
Fig. 3 E is please referred to, in step s 2, can be nitrogenized using chemical vapor deposition process in groove 303a and floating gate
The surface of silicon layer 303 deposits certain thickness source line polysilicon layer 307, and the thickness of the source line polysilicon layer 307 of deposition can make
It obtains groove 303a to fill up, the height of the first side wall 305 is H1 at this time.The formation process of source line polysilicon layer 307 can be with are as follows: adopts
With selective epitaxial depositing operation, using the area surface of semiconductor base 300 as the seed layer of growth monocrystalline silicon, by source region table
Face gradually epitaxial growth source line polysilicon layer 307 upwards, until filling up groove 303a.
Fig. 3 F is please referred to, in step s3, is carried out using source line polysilicon layer 307 of the CMP process to deposition
Top flattening, or using 307 top of technique etching source line polysilicon layer is etched back to, until exposing the floating gate silicon nitride layer
303 top surface, and endpoint monitoring is carried out to the CMP process or the technique that is etched back to, to obtain residue
The source line polysilicon layer 307 the width L or first side wall 305 at the top of the groove 303a loss height
Δ H=H1-H2 accurately monitors width L at the top of the groove 303a or the institute of the remaining source line polysilicon layer 307
The loss height Δ H for stating the first side wall 305, can accurately control the thickness deltat L of subsequent first side wall being laterally etched back to, in turn
Accurately control the height and corner angle at the floating gate tip being subsequently formed.
Fig. 3 G is please referred to, in step s 4, it is possible, firstly, to which the hot phosphoric acid solution wet process using temperature higher than 120 DEG C removes
The floating gate silicon nitride layer, to expose the side wall of the first side wall 305；Then, according to monitoring the remaining of acquisition in step S3
The loss height Δ of the width L or first side wall 305 at the top of the groove 303a of the source line polysilicon layer 307
H, the technological parameter for being laterally etched back to technique of the next side wall to the first side wall 305 exposed is arranged, for example, connecing down
Use the wet corrosion technique to be laterally etched back to the side wall for exposing the first side wall 305, then it can be according to described
Monitoring as a result, adjust the wet corrosion technique at least one of technological parameter, the technological parameter of the wet corrosion technique
Concentration, temperature and etching time including corrosive liquid, for example, the corrosive liquid of the wet corrosion technique is temperature between 40 DEG C
~100 DEG C of the standard cleaning liquid mixed by ammonium hydroxide, hydrogen peroxide and deionized water, wherein ammonium hydroxide, dioxygen
The volume ratio of water and deionized water is 1: 2: 20~1:2:50.According to the adjustable etching time of monitoring result in 30s~600s
Middle variation.In the present embodiment, the width at the top of the groove 303a of the remaining source line polysilicon layer 307 monitored
L is wider or the loss height Δ H of first side wall 305 is smaller, to the side wall of first side wall 305 exposed into
The thickness deltat L=L1-L2 that row is laterally etched back to is bigger, or carries out to the side wall of first side wall 305 exposed lateral
The etch period being etched back to is longer, for example, 180s or 300s.Side is carried out to the side wall of first side wall 305 exposed
The height and corner angle at the floating gate tip to be formed, i.e., the described thickness deltat L are finally determined to the size for the thickness deltat L being etched back to
Bigger, the height at the floating gate tip of formation is lower, and apex angle is more blunt；Conversely, the thickness deltat L is smaller, the floating gate tip of formation
Height is higher, and apex angle is sharper.
Fig. 3 H is please referred to, is exposure mask with remaining first side wall 305 in step s 5, the floating gate that etching lower section exposes
Polysilicon layer 302 and floating gate oxide layers 301 below, until exposing semiconductor base 300,305 He of the first side wall
The remaining floating gate polysilicon layer 302 of remaining floating gate silicon nitride layer covering becomes the FGS floating gate structure with floating gate tip 302a,
The floating gate tip 302a has meet the requirements height and corner angle.
Fig. 3 I is please referred to, it later can be in FGS floating gate structure outside side wall and the semiconductor base on the outside of FGS floating gate structure
300 surfaces form tunnel oxide 308, the word line polysilicon layer for electrically isolating floating gate polysilicon layer 302 Yu being subsequently formed
309 and word line polysilicon layer 309 and 300 surface of semiconductor base.In the present embodiment, the formation process of tunnel oxide 308
It can be thermal oxidation technology, since thermal oxidation technology can consume the side wall that part floating gate polysilicon layer 302 is etched, to protect
The height and acute angle shape at the floating gate tip on the top of the floating gate polysilicon layer 302 through over etching are demonstrate,proved, to meet erasing and programming
The demand of function.When carrying out erasing operation to Split-gate flash memory, floating gate tip reduces FN tunnel by point discharge principle
The channel voltage of effect is worn, can make the electronics be easier to be pulled away from floating gate polysilicon layer 302 from tip and flow into and be subsequently formed
Wordline polycrystal layer 309.In other embodiments of the invention, the formation process of tunnel oxide 308 may also is that high temperature deposition
Technique (High Temperature Oxidation, HTO), the method or other of TEOS (tetraethyl orthosilicate) process deposits
Similar deposition method, the reaction gas of the high-temperature deposition process include DCS (dichlorosilane, dichlo rosilance,
SiH2Cl2) and N2O, the temperature of high temperature deposition are 750 DEG C~850 DEG C.If depositing temperature is too high, equipment can be made by high temperature
It limits, be easy to make that technique thermal energy is excessive, increase resistance value, carrier infiltration is too deep, phenomena such as Yi Zengjia leakage current；Deposition temperature
If degree is too low, the of low quality of tunnel oxide 308 is formed.Technological reaction gas ratio, flow and technological reaction time can
To be adjusted at any time according to the case where technological reaction, belong to the known technology of those skilled in the art.Then, with tunnelling oxygen
The entire device surface deposit polycrystalline silicon layer for changing layer 308, and etches the polysilicon layer, on 308 surface of tunnel oxide with
And word line polysilicon layer 309 is formed on 305 side of the first side wall.It later, can be in the device table with word line polysilicon layer 309
Face deposits wordline spacer material, and etches wordline spacer material, in the side of word line polysilicon layer 309 and tunnel oxide 308
Face forms wordline side wall 310.
After tested, the programming of the gate-division type flash memory device manufactured using gate-division type flash memory device making method of the invention is lost
Effect and erasing Problem of Failure have obtained great alleviation, substantially increase shipment rate.For example, use is existing in one group of test
The shipment rate of the gate-division type flash memory device of conventional gate-division type flash memory device fabrication method manufacture is 78.6%, and uses this
After the gate-division type flash memory device making method of invention, the shipment rate of the gate-division type flash memory device of manufacture rises to 94.9%.
In conclusion depositing certain thickness in the groove of the floating gate silicon nitride layer and the floating gate silicon nitride layer surface
Source line polysilicon layer after, top flattening technique to the source line polysilicon layer or be etched back to technique and carry out terminal prison
Survey, with obtain the source line polysilicon layer in the width of the top of the groove or the loss height of first side wall, and
After removing the floating gate silicon nitride layer, according to the monitoring as a result, to the side wall of first side wall exposed into
Row is laterally etched back to accordingly, to expose the floating gate polysilicon layer of appropriate area, to guarantee that subsequent etching exposes floating
After gate polysilicon layer, the floating gate tip with suitable height and corner angle can be obtained, sub-gate sudden strain of a muscle may finally be avoided
The data erasing failure and programming Problem of Failure of memory device.
Obviously, those skilled in the art can carry out various modification and variations without departing from spirit of the invention to invention
And range.If in this way, these modifications and changes of the present invention belong to the claims in the present invention and its equivalent technologies range it
Interior, then the present invention is also intended to include these modifications and variations.
Claims (9)
1. a kind of gate-division type flash memory device making method, which comprises the following steps:
Semiconductor substrate is provided, is sequentially formed with floating gate oxide layers, floating gate polysilicon layer and floating gate nitrogen in the semiconductor substrate
SiClx layer, the floating gate oxide layers, floating gate polysilicon layer and floating gate silicon nitride layer, which are equipped with, exposes the semiconductor substrate surface
Groove, have the first side wall on the floating gate silicon nitride layer side wall in the groove, the floating gate oxidation in the groove
There is the second side wall on layer and the floating gate polysilicon layer side wall；
In the groove and the floating gate silicon nitride layer surface sedimentary origin line polysilicon layer, the deposition of the source line polysilicon layer
Thickness can fill up the groove；
Top flattening is carried out to the source line polysilicon layer or is etched back to, until the floating gate silicon nitride layer surface is exposed,
And monitor the loss of the width or monitoring first side wall in the top of the groove of the remaining source line polysilicon layer
Highly；
Remove the floating gate silicon nitride layer, and according to the monitoring as a result, to the side wall of first side wall exposed into
Row is laterally etched back to accordingly, with the floating gate polysilicon layer of exposure lower section corresponding region；
Using first side wall as exposure mask, the floating gate oxidation of the floating gate polysilicon layer and lower section that expose is etched
Layer, to obtain the FGS floating gate structure for having floating gate tip.
2. gate-division type flash memory device making method as described in claim 1, which is characterized in that provide the semiconductor substrate
Step includes:
Semiconductor base is provided, sequentially forms the floating gate oxide layers, the floating gate polysilicon layer, institute on the semiconductor base
State floating gate silicon nitride layer and graphical photoresist；
Using the graphical photoresist as exposure mask, etches the floating gate silicon nitride layer and stop at the floating gate polysilicon layer table
Face forms groove；
The graphical photoresist is removed, and using the floating gate silicon nitride layer as exposure mask, in groove described in isotropic etching
Floating gate polysilicon layer is to certain depth, for being subsequently formed floating gate tip；
The first side wall is formed in the floating gate silicon nitride layer of the groove and the inner sidewall of the floating gate polysilicon layer exposed；
Using first side wall as exposure mask, continue to etch the floating gate polysilicon layer and floating gate oxide layers in the groove, until
Expose the semiconductor substrate surface of lower section；
The second side wall is formed on the inner sidewall of floating gate polysilicon layer and floating gate oxide layers in the trench.
3. gate-division type flash memory device making method as described in claim 1, which is characterized in that reflected using based on optical spectroscopic
The width in the top of the groove of source line polysilicon layer described in the endpoint monitoring technical monitoring of rate or monitoring first side
The loss height of wall.
4. gate-division type flash memory device making method as described in claim 1, which is characterized in that using temperature higher than 120 DEG C
Hot phosphoric acid solution carrys out wet process and removes the floating gate silicon nitride layer, to expose the side wall of first side wall as corrosive liquid.
5. gate-division type flash memory device making method as described in claim 1, which is characterized in that wet corrosion technique is used, it is right
The side wall of first side wall exposed is laterally etched back to.
6. gate-division type flash memory device making method as claimed in claim 5, which is characterized in that according to the monitoring as a result,
At least one technological parameter of the wet corrosion technique is adjusted, the technological parameter of the wet corrosion technique includes corrosive liquid
Concentration, temperature and etch period.
7. such as gate-division type flash memory device making method described in claim 5 or 6, which is characterized in that the wet corrosion technique
Corrosive liquid be temperature it is clear between 40 DEG C~100 DEG C of the standard mixed by ammonium hydroxide, hydrogen peroxide and deionized water
Washing lotion.
8. gate-division type flash memory device making method as claimed in claim 5, which is characterized in that the source line polycrystalline monitored
The width in the top of the groove of silicon layer is wider, or the loss height of first side wall monitored is smaller, to exposure
The thickness that the side wall of first side wall out is laterally etched back to is bigger.
9. gate-division type flash memory device making method as claimed in claim 5, which is characterized in that the source line polycrystalline monitored
The width in the top of the groove of silicon layer is wider, or the loss height of first side wall monitored is smaller, to exposure
The etch period that the side wall of first side wall out is laterally etched back to is longer.
Priority Applications (1)
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| CN108257964B (en) * | 2016-12-29 | 2020-11-10 | 无锡华润上华科技有限公司 | Flash memory device and manufacturing method thereof |
| CN108257962A (en) * | 2016-12-29 | 2018-07-06 | 无锡华润上华科技有限公司 | Flash memory storage structure and its manufacturing method |
| CN108987403B (en) * | 2018-07-20 | 2020-11-13 | 上海华虹宏力半导体制造有限公司 | Method for controlling tip of floating gate of flash memory |
| CN109103085A (en) * | 2018-08-06 | 2018-12-28 | 上海华虹宏力半导体制造有限公司 | Flash memory and its manufacturing method |
| CN109638016B (en) * | 2019-01-02 | 2020-07-14 | 上海华虹宏力半导体制造有限公司 | Flash memory and forming method thereof |
| CN109872994B (en) * | 2019-03-07 | 2021-09-03 | 上海华虹宏力半导体制造有限公司 | Split-gate flash memory and preparation method thereof |
| CN110828463B (en) * | 2019-10-25 | 2022-05-31 | 上海华虹宏力半导体制造有限公司 | Layout and mask of split-gate flash memory and layout manufacturing method |
| CN111129024B (en) * | 2019-12-27 | 2022-06-07 | 华虹半导体(无锡)有限公司 | Method for manufacturing flash memory device |
| CN111128705B (en) * | 2019-12-27 | 2022-06-07 | 华虹半导体(无锡)有限公司 | Method for etching silicon oxide and polysilicon |
| CN112750790B (en) * | 2021-01-22 | 2023-11-21 | 上海华虹宏力半导体制造有限公司 | Flash memory and method for manufacturing the same |
| CN112908856B (en) * | 2021-03-09 | 2024-05-14 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing flash memory device |
| CN112908857A (en) * | 2021-03-09 | 2021-06-04 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing semiconductor device |
| CN113192838B (en) * | 2021-03-24 | 2024-02-02 | 上海华虹宏力半导体制造有限公司 | Flash memory forming method |
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