CN108091562B - ONO etching method of SONOS memory - Google Patents
ONO etching method of SONOS memory Download PDFInfo
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
Abstract
The invention provides an ONO etching method of an SONOS memory, which is characterized in that a barrier layer is deposited on a substrate on which an ONO lamination layer is formed, and the removal of ONO side walls at two sides of shallow trench isolation is easily finished without generating any plasma damage to a bottom gate oxide layer by utilizing the isotropic characteristic of a wet etching process, so that the reliability of a device is ensured; meanwhile, the method can also overcome the change of the step height of the wafer caused by the front-layer shallow trench isolation planarization grinding process, so that the etching window is greatly increased. The etching process is stable and controllable, and is suitable for batch production.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to an ONO etching method of a SONOS memory.
Background
With the continuous improvement of the integration level requirement of the market on the FLASH memory device, the contradiction between the reliability of data storage of the traditional FLASH memory device and the working speed, power consumption, size and the like of the device is increasingly highlighted. The SONOS memory has the characteristics of small cell size, low operating voltage, compatibility with CMOS processes, and the like, and the continuous improvement of the SONOS technology will push the development of semiconductor memories toward miniaturization, high performance, large capacity, low cost, and the like.
The SONOS (Silicon-Oxide-Nitride-Oxide-Silicon, SONOS) memory uses a substrate-tunneling Oxide layer-Silicon Nitride-Oxide layer-polysilicon gate stack layer to replace a floating gate structure in the traditional FLASH memory device, and is a charge trap type memory. An ONO (oxide-nitride-oxide) stack is formed using an in-situ process to implement a SONOS structure. After the ONO is formed, the ONO stack is not required in the device region and the peripheral region, and the ONO stack in the peripheral region and the device region is removed by photolithography, wet etching, dry etching, and the like.
There are many problems with the current ONO stack process for removing the periphery region as well as the device region. Firstly, the thickness of an ONO side wall can be changed along with the great change of the height (Step height) of a wafer in the process of polishing a front-layer STI (shallow trench isolation) CMP (chemical mechanical polishing), the oxide layer at the top of the ONO is finished by a dry etching process at present, if the height of the ONO side wall is increased, a dry etching process window is not enough, the residue of the oxide layer at the top can be generated, and the residue of a nitride layer is finally formed by protecting a nitride layer in the process of removing the next ONO nitride layer, which directly influences the performance of a device; if the etching amount of the ONO top oxide layer is increased to enlarge the process window, the gate oxide layer of the I/O area is directly damaged by the plasma from the dry etching process, which seriously affects the reliability performance of the device.
Disclosure of Invention
The invention aims to provide an ONO etching method of an SONOS memory, which aims to solve the problems that in the existing ONO lamination process for removing a peripheral region and a device region, the height of a wafer step is changed due to a front-layer STI CMP process, and plasma damage is generated on a bottom gate oxide layer when ONO side walls on two sides of the STI are removed.
In order to achieve the above object, the present invention provides an ONO etching method for a SONOS memory, comprising the steps of:
providing a substrate, wherein the substrate comprises a gate region, a device region and a peripheral region, and shallow trench isolation is formed in the device region;
forming an ONO lamination layer on the whole surface of the substrate, wherein the ONO layer comprises a first oxidation layer, a nitridation layer and a second oxidation layer which are sequentially laminated;
forming a barrier layer on the second oxide layer;
removing the barrier layer in the selective device region and the peripheral region by adopting a dry etching process to expose the second oxide layer;
removing the second oxide layer in the selective device region and the peripheral region by adopting a wet etching process to expose the nitride layer; and
and removing the nitride layers of the device region and the peripheral region and the barrier layer of the gate region simultaneously by adopting a wet etching process so as to expose the shallow trench isolation.
Optionally, the barrier layer is a silicon nitride barrier layer.
Optionally, before the barrier layer in the device region and the peripheral region is removed by using a dry etching process, a photoresist is coated by using a photolithography process, and the photoresist covers the gate region to expose the device region and the peripheral region.
Optionally, after the barrier layer in the device region and the barrier layer in the peripheral region are removed by using a dry etching process to expose the second oxide layer, and before the second oxide layer in the device region and the second oxide layer in the peripheral region are removed by using a wet etching process to expose the silicon nitride layer, the method further includes: and removing the residual photoresist by adopting an in-situ process.
Optionally, the thickness of the barrier layer does not exceed the thickness of the nitride layer.
Optionally, when the barrier layer in the device region and the barrier layer in the peripheral region are removed by using a dry etching process, the etching selectivity of the barrier layer to the second oxide layer is high.
Optionally, when the wet etching process is used to remove the device region and the second oxide layer in the peripheral region, the etching selectivity of the second oxide layer and the nitride layer is high.
Optionally, when the nitride layers of the device region and the peripheral region and the barrier layer of the gate region are removed simultaneously by using a wet etching process, the etching selection ratio of the nitride layer to the first oxide layer is high, and the etching selection ratio of the barrier layer to the first oxide layer is high.
Optionally, the barrier layer forming method adopts chemical vapor deposition.
Optionally, when the barrier layer in the device region and the peripheral region is removed by using a dry etching process, the device region and the peripheral region are stopped on the second oxide layer by using a stop manner when reaching an end point.
Optionally, the first oxide layer of the device region and the first oxide layer of the peripheral region are used as a protective layer during etching of the nitride layer, and the second oxide layer of the gate region is used as a protective layer during etching of the barrier layer.
In summary, in the ONO etching method for the SONOS memory provided in the present invention, a substrate is provided, the substrate includes a gate region, a device region and a peripheral region, and a shallow trench isolation is formed in the device region; forming an ONO lamination layer on the whole surface of the substrate, wherein the ONO layer comprises a first oxidation layer, a nitridation layer and a second oxidation layer which are sequentially laminated; forming a barrier layer on the second oxide layer; removing the barrier layer in the device region and the peripheral region by adopting a dry etching process to expose the second oxide layer; removing the second oxide layer in the device region and the peripheral region by adopting a wet etching process to expose the nitride layer; and removing the nitride layers of the device region and the peripheral region and the barrier layer of the gate region by adopting a wet etching process to expose the shallow trench isolation. The method provided by the invention utilizes the isotropic characteristic of the wet etching process to easily remove the ONO side walls on the two sides of the shallow trench isolation, thereby avoiding the residue of the ONO layer, avoiding the damage of plasma on the bottom gate oxide layer and ensuring the reliability of the device; meanwhile, the problems that the height of the steps of the wafer is changed and the etching window is greatly increased due to the chemical mechanical polishing and grinding process of the shallow trench isolation of the front layer can be solved, and the etching process is stable and controllable and is suitable for batch production.
Drawings
FIG. 1 is a schematic cross-sectional view illustrating an ONO layer formed in a method for fabricating a SONOS memory;
FIG. 2 is a schematic cross-sectional view illustrating etching of a second oxide layer in a method for fabricating a SONOS memory;
FIG. 3 is a schematic cross-sectional view illustrating a nitride layer etched in a method for fabricating a SONOS memory;
FIG. 4 is a schematic flow chart illustrating an ONO etching method for a SONOS memory according to an embodiment of the present invention;
FIG. 5 is a schematic cross-sectional view illustrating an ONO layer formed in a method for fabricating a SONOS memory according to an embodiment of the present invention;
fig. 6 is a schematic cross-sectional view illustrating a barrier layer formed in a method for fabricating a SONOS memory device according to an embodiment of the present invention;
fig. 7 is a schematic cross-sectional structure diagram of an etching stop layer in the method for manufacturing a SONOS memory according to an embodiment of the present invention;
fig. 8 is a schematic cross-sectional structure diagram illustrating etching of a second oxide layer in the method for manufacturing a SONOS memory device according to an embodiment of the invention;
FIG. 9 is a schematic cross-sectional view of an etching stop layer and a nitride layer in a method for fabricating a SONOS memory according to an embodiment of the present invention;
the device comprises a substrate, a gate oxide layer, a tunneling oxide layer, a nitriding layer, a top oxide layer, a substrate, a gate oxide layer, a tunneling oxide layer, a nitriding layer, a gate oxide layer, a 22-oxide layer, a 23-nitride layer, a 24-oxide layer and a 25-blocking layer.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. Advantages and features of the present invention will become apparent from the following description and claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
As described in the background, ONO etching of SONOS memory devices is an essential step in the semiconductor manufacturing industry, and there are problems with the current ONO etching process for SONOS memory devices.
Referring to fig. 1 to 3, referring to fig. 1, a semiconductor substrate 100 is first provided, where the surface of the semiconductor substrate 100 has at least a gate region, a device region and a peripheral region, and an ONO stack is formed at this time. The gate region in fig. 1 includes a tunnel oxide layer 102, a nitride layer 103, a top oxide layer 104, and the device region and the peripheral region include a gate oxide layer 101, a nitride layer 103, and a top oxide barrier layer 104. As shown in fig. 2, photoresist is coated and developed on the surface of the semiconductor substrate 100 to expose the device region and the peripheral region, and a dry etching process is used to remove a portion of the oxide layer 104 in the device region and the peripheral region, so as to remove the remaining photoresist. As shown in fig. 3, the nitride layer in the device region and the peripheral region is removed by a wet etching process, and finally the ONO etching process is completed. However, there are many problems with this process.
Firstly, the thickness of the ONO side wall can be changed due to large changes in the height surface of a wafer step and between batches in the grinding process of front-layer STI CMP (shallow trench isolation planarization), the residue of the oxide layer 14 can appear due to insufficient dry etching process window when the oxide layer 14 at the top of the ONO is finished by a dry etching process at present and the height of the ONO side wall is increased, and the residue of silicon nitride can be finally formed by protecting the silicon nitride in the subsequent removal process of the ONO silicon nitride layer 13, which directly influences the performance of a device; if the process window is increased by increasing the amount of etching of the ONO top oxide layer 14, the gate oxide layer 11 in the I/O region will be directly damaged by the plasma from the dry etching process, which seriously affects the reliability performance of the device.
Therefore, in order to solve the above problems in manufacturing a semiconductor device, the present invention provides an ONO etching method for a SONOS memory device.
Referring to fig. 4, which is a schematic flow chart of an ONO etching method for a SONOS memory according to an embodiment of the present invention, as shown in fig. 4, the ONO etching method for a SONOS memory includes the following steps:
step S1: providing a substrate, wherein the substrate comprises a gate region, a device region and a peripheral region, and shallow trench isolation is formed in the device region;
step S2: forming an ONO lamination layer on the whole surface of the substrate, wherein the ONO layer comprises a first oxidation layer, a nitridation layer and a second oxidation layer which are sequentially laminated;
step S3: forming a barrier layer on the second oxide layer;
step S4: removing the selective gate region and the peripheral barrier layer by adopting a dry etching process to expose the second oxide layer;
step S5: removing the selective gate region and the peripheral second oxide layer by adopting a wet etching process to expose the nitride layer; and
step S6: and removing the nitride layers of the gate region and the peripheral region and the barrier layer of the gate region by adopting a wet etching process so as to expose the shallow trench isolation.
Referring to fig. 5 to 9, cross-sectional structures of an ONO etching method for a SONOS memory according to an embodiment of the present invention are shown. The ONO etching method of the SONOS memory device in the embodiment is described in detail with reference to fig. 5 to 9.
In step S1, the base 20 is a P substrate in this embodiment.
In step S2, in the gate region, the first oxide layer is a tunnel oxide layer 22, in the device region and the peripheral region, the first oxide layer is a gate oxide layer 21, the first oxide layer and the second oxide layer may be silicon oxide layers, the nitride layer may be a silicon nitride layer, and in the gate region, the device region and the peripheral region, the second oxide layer is a top oxide layer; further, the ONO stack is formed using an in-situ method.
In step S3, the barrier layer 25 is a silicon nitride barrier layer, and the silicon nitride barrier layer is deposited by a Chemical Vapor Deposition (CVD) process, but may be deposited by other techniques known to those skilled in the art, wherein the thickness of the barrier layer 25 does not exceed the thickness of the nitride layer 23 in the ONO stack, and preferably, the thickness of the barrier layer 25 in this embodiment is in the range of 20 angstroms to 120 angstroms.
Referring to fig. 6 and 7, in step S4, the removing step may be specifically divided into 3 steps: firstly, photoresist coating is carried out through a photoetching process, a SONOS area is covered by a photomask for protection, and the photoresist in a device area and a peripheral area is developed and displayed; then, removing the silicon nitride barrier layer 25 in the device region and the peripheral region by using a dry etching method; finally, removing the residual photoresist by adopting an in-situ method; in the embodiment of the present invention, when the barrier layer 25 in the device region and the peripheral region is removed, the etching selectivity ratio between the barrier layer 25 and the second oxide layer 24 is high, that is, the etching selectivity ratio between the barrier layer and the second oxide layer is relatively high, by stopping on the second oxide layer 24 in a manner of stopping when reaching an endpoint. Generally, two ways of stopping when the etching reaches the time and stopping when the etching reaches the end point are performed, wherein the reaching time stopping way is to specify the time length of one etching, for example, to specify the etching time to be 10 minutes, and the etching stops when the time is up, no matter whether the medium required to be etched is etched. In the embodiment, when the etching of the barrier layer 25 is completed, the second oxide layer 24 will send a signal to stop the etching process.
Referring to fig. 7 and 8, in step S5, when the nitride layer 23 is used as a barrier layer and the second oxide layer 24 in the device region and the peripheral region is removed by wet etching, a chemical solution with a relatively high etching selectivity ratio between the second oxide layer and the nitride layer is used, and a silicon dioxide etching solution may be used in this embodiment.
Referring to fig. 8 and 9, in step S6, the nitride layer 23 in the device region and the peripheral region and the remaining barrier layer 25 in the gate region are simultaneously removed by a wet etching process. The etching selection ratio of the nitriding layer to the first oxidation layer of the chemical liquid adopted in the process is high, namely the etching selection ratio of the nitriding layer to the first oxidation layer is high; the barrier layer has a higher etch selectivity than the first oxide layer, i.e., the barrier layer has a higher etch selectivity than the first oxide layer.
The first oxide layer (gate oxide layer) 21 of the device region and the peripheral region is used as a protective layer when the nitride layer 23 is etched, and the second oxide layer 24 of the gate region is used as a protective layer when the barrier layer 25 is etched.
In summary, in the ONO etching method for the SONOS memory provided in the embodiment of the present invention, a substrate is provided, the substrate includes a gate region, a device region and a peripheral region, and a shallow trench isolation is formed in the device region; forming an ONO lamination layer on the whole surface of the substrate, wherein the ONO layer comprises a first oxidation layer, a nitridation layer and a second oxidation layer which are sequentially laminated; forming a barrier layer on the second oxide layer; removing the barrier layer in the device region and the peripheral region by adopting a dry etching process to expose the second oxide layer; removing the oxide layers of the device region and the peripheral region by adopting a wet etching process to expose the nitride layer; and removing the nitride layers of the device region and the peripheral region and the barrier layer of the gate region by adopting a wet etching process to expose the shallow trench isolation. Compared with the prior art, the method provided by the invention has the following advantages: the damage to the gate oxide layer caused by the current etching process can be avoided, namely the removal of the ONO side walls at the two sides of the shallow trench isolation can be easily finished without generating any plasma damage to the bottom gate oxide layer, and the reliability of the device is ensured; the method greatly increases the etching windows of the ONO side walls at two sides of the shallow trench isolation by utilizing the isotropic characteristics of the wet etching process; the method can overcome the height change of the wafer step in the height surface and between batches caused by the front-layer shallow trench isolation planarization grinding process, the etching window is greatly increased, and the etching process is stable and controllable and is suitable for batch production.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (11)
1. An ONO etching method of a SONOS memory is characterized by comprising the following steps:
providing a substrate, wherein the substrate comprises a gate region, a device region and a peripheral region, and shallow trench isolation is formed in the device region;
forming an ONO lamination layer on the whole surface of the substrate, wherein the ONO layer comprises a first oxidation layer, a nitridation layer and a second oxidation layer which are sequentially laminated;
forming a barrier layer on the second oxide layer;
removing the barrier layer in the device region and the peripheral region by adopting a dry etching process to expose the second oxide layer;
removing the second oxide layer in the device region and the peripheral region by adopting a wet etching process to expose the nitride layer; and
and removing the nitride layers of the device region and the peripheral region and the barrier layer of the gate region simultaneously by adopting a wet etching process so as to expose the shallow trench isolation.
2. The method of ONO etching for SONOS memory devices of claim 1, wherein the material of the barrier layer comprises silicon nitride.
3. The method of claim 1, wherein a photoresist coating is performed by a photolithography process before the barrier layer of the device region and the peripheral region is removed by a dry etching process, wherein the photoresist covers the gate region to expose the device region and the peripheral region.
4. The method of claim 3, wherein after the removing the barrier layer in the device region and the peripheral region by a dry etching process to expose the second oxide layer, and before the removing the second oxide layer in the device region and the peripheral region by a wet etching process to expose the nitride layer, further comprises: and removing the residual photoresist by adopting an in-situ process.
5. The method of ONO etching for SONOS memory devices of claim 1, wherein the thickness of the barrier layer does not exceed the thickness of the nitride layer.
6. The ONO etching method for SONOS memory device of claim 1, wherein an etch selectivity ratio of the blocking layer to the second oxide layer is high when the blocking layer of the device region and the peripheral region is removed using a dry etching process.
7. The method of claim 1, wherein a ratio of etch selectivity of the second oxide layer to that of the nitride layer is high when the wet etching process is used to remove the second oxide layer in the device region and the peripheral region.
8. The ONO etching method for SONOS memory device of claim 1, wherein, when the nitride layer of the device region and the peripheral region and the barrier layer of the gate region are simultaneously removed by a wet etching process, the nitride layer has a higher etching selectivity than the first oxide layer, and the barrier layer has a higher etching selectivity than the first oxide layer.
9. The method of ONO etching for SONOS memory devices of claim 1, wherein the barrier layer formation method employs chemical vapor deposition.
10. The method of claim 1, wherein the second oxide layer is stopped by stopping at an endpoint when the barrier layer in the device region and the peripheral region is removed by a dry etching process.
11. The method of claim 1, wherein the first oxide layer of the device region and the peripheral region serves as a protection layer during etching of the nitride layer, and the second oxide layer of the gate region serves as a protection layer during etching of the barrier layer.
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| CN109616475B (en) * | 2018-12-12 | 2020-09-01 | 上海华力微电子有限公司 | Process method for removing residual blocking oxide layer in side wall ONO structure |
| CN110047750B (en) * | 2019-03-28 | 2021-07-27 | 上海华力微电子有限公司 | Method for preventing substrate damage caused by ONO etching |
| CN111244104B (en) * | 2020-03-27 | 2023-09-15 | 上海华力微电子有限公司 | SONOS memory and manufacturing method thereof |
| CN113506804B (en) * | 2021-06-22 | 2023-07-04 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of memory device |
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| US6448137B1 (en) * | 2001-11-02 | 2002-09-10 | Macronix International Co. Ltd. | Method of forming an NROM embedded with mixed-signal circuits |
| CN104752363A (en) * | 2013-12-31 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Forming method of flash memory |
| CN106098694A (en) * | 2016-08-22 | 2016-11-09 | 上海华力微电子有限公司 | A kind of Nonvolatile memory structure and preparation method thereof |
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| US6448137B1 (en) * | 2001-11-02 | 2002-09-10 | Macronix International Co. Ltd. | Method of forming an NROM embedded with mixed-signal circuits |
| CN104752363A (en) * | 2013-12-31 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Forming method of flash memory |
| CN106098694A (en) * | 2016-08-22 | 2016-11-09 | 上海华力微电子有限公司 | A kind of Nonvolatile memory structure and preparation method thereof |
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