CN106169498A - 高热稳定性超结应变Si/SiGe异质结双极晶体管 - Google Patents
高热稳定性超结应变Si/SiGe异质结双极晶体管 Download PDFInfo
- Publication number
- CN106169498A CN106169498A CN201610617990.2A CN201610617990A CN106169498A CN 106169498 A CN106169498 A CN 106169498A CN 201610617990 A CN201610617990 A CN 201610617990A CN 106169498 A CN106169498 A CN 106169498A
- Authority
- CN
- China
- Prior art keywords
- strain
- superjunction
- relaxation
- collecting zone
- type layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910000577 Silicon-germanium Inorganic materials 0.000 title claims abstract description 49
- 229910006990 Si1-xGex Inorganic materials 0.000 claims abstract description 22
- 229910007020 Si1−xGex Inorganic materials 0.000 claims abstract description 22
- 239000000470 constituent Substances 0.000 claims description 8
- 230000015556 catabolic process Effects 0.000 abstract description 7
- 230000035945 sensitivity Effects 0.000 abstract description 6
- 230000005684 electric field Effects 0.000 abstract description 3
- 230000001629 suppression Effects 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 239000000463 material Substances 0.000 description 7
- 239000012535 impurity Substances 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- INQLNSVYIFCUML-QZTLEVGFSA-N [[(2r,3s,4r,5r)-5-(6-aminopurin-9-yl)-3,4-dihydroxyoxolan-2-yl]methoxy-hydroxyphosphoryl] [(2r,3s,4r,5r)-5-(4-carbamoyl-1,3-thiazol-2-yl)-3,4-dihydroxyoxolan-2-yl]methyl hydrogen phosphate Chemical compound NC(=O)C1=CSC([C@H]2[C@@H]([C@H](O)[C@@H](COP(O)(=O)OP(O)(=O)OC[C@@H]3[C@H]([C@@H](O)[C@@H](O3)N3C4=NC=NC(N)=C4N=C3)O)O2)O)=N1 INQLNSVYIFCUML-QZTLEVGFSA-N 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 210000000056 organ Anatomy 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/737—Hetero-junction transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0804—Emitter regions of bipolar transistors
- H01L29/0817—Emitter regions of bipolar transistors of heterojunction bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0821—Collector regions of bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1004—Base region of bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
本发明公开了一种具有高热稳定性的超结应变Si/SiGe异质结双极晶体管。所述晶体管采用SiGe虚拟衬底结构，其上分别外延生长弛豫Si1‑yGey次集电区、弛豫Si1‑yGey集电区、应变Si1‑xGex基区和应变Si发射区。所述晶体管通过在弛豫Si1‑yGey集电区引入与应变Si1‑xGex基区平行的超结p型层达到改善集电结空间电荷区电场分布、降低峰值电子温度、抑制碰撞电离和提高器件击穿电压的目的。同时，超结p型层的引入，将有效降低弛豫Si1‑yGey集电区的掺杂浓度和声子散射几率、提高弛豫Si1‑yGey集电区热导率。所述晶体管兼具大电流增益和高击穿电压特性，且内部温度分布显著降低，特征频率温度敏感性得到改善，可在较宽的工作温度范围内实现高热稳定性工作。
Description
技术领域
本发明涉及应变硅异质结双极晶体管，特别是应用于点对点无线通信***(>120GHz)、卫星***、光纤***、4G/5G移动通信***等射频和微波领域的高热稳定性超结应变Si/SiGe异质结双极晶体管。
背景技术
与传统SiGe异质结双极晶体管(heterojunction bipolar transistor，HBT)相比，应变Si/SiGe HBT具有大电流增益、高电流处理能力和优异的高频特性。特别是随着应变技术在***SiGe工艺的全面展开，应变Si/SiGe HBT将在面向太赫兹应用的传感器、成像仪、高宽带模拟-数字转换器、汽车雷达以及高线性放大器等领域中扮演越来越重要的角色。
应变Si/SiGe HBT采用SiGe虚拟衬底结构，可有效降低器件中衬底对基区SiGe外延层应力的影响，进而提高基区Ge组分，增大器件的电流增益。同时，较大的电流增益又可用于折中基区电阻、减小基区宽度，最终大幅度提升器件的高频特性。然而，虚拟衬底应变Si/SiGe HBT的集电区为SiGe材料，与Si材料相比，其击穿电场较低，使得器件击穿电压下降，进而导致***输出功率的降低。此外，SiGe材料的热导率远低于Si材料的热导率，使得自加热效应在应变Si/SiGe HBT中更加显著。当器件工作在大电流时，自加热效应易引起静态工作点的漂移，加剧热不稳定性，从而严重限制了器件的高功率稳定工作。可见，如何设计出既具有大电流增益、高击穿电压，又可有效削弱自加热效应，从而实现高热稳定性的应变Si/SiGe HBT，具有重要的理论和实际意义。
发明内容
本发明公开了一种具有高热稳定性的超结应变Si/SiGe异质结双极晶体管。
一种高热稳定性超结应变Si/SiGe异质结双极晶体管，其特征在于：
包括依次形成的SiGe虚拟衬底(10)，弛豫Si1-yGey次集电区(11)，弛豫Si1-yGey集电区(12)，超结p型层(13)，本征应变Si1-xGex下缓冲层(14)，应变Si1-xGex基区(15)，本征应变Si1-xGex上缓冲层(16)Si1-xGex外基区(17)，应变Si发射区(18)；
所述超结p型层(13)位于所述弛豫Si1-yGey集电区(12)内，同时平行于应变Si1-xGex基区(15)且位于本征应变Si1-xGex下缓冲层(14)下方100nm处；
所述超结p型层(13)的掺杂浓度与弛豫Si1-yGey集电区(12)的掺杂浓度相等，同时所述超结p型层由一层或多层p型层组成，其中p型层总厚度不超过50nm，且当多层时各个p型层之间的间距为50nm。
进一步，所述应变Si1-xGex基区(15)中的Ge组分含量x大于或等于0.3，且所述应变Si1-xGex基区(15)中的Ge组分含量x与所述弛豫Si1-yGey次集电区(11)和所述弛豫Si1-yGey集电区(12)中的Ge组分含量y需满足0<y<x。
所述晶体管通过在SiGe虚拟衬底上依次外延生长弛豫Si1-yGey次集电区、弛豫Si1-yGey集电区、应变Si1-xGex基区和应变Si发射区得到。其中通过发射区采用拉应变Si材料、基区采用压应变SiGe材料来调节应力，在实现发射区与基区界面处的晶格匹配的同时，也维持了应变Si/SiGe HBT更高的基区Ge组分和更大的电流增益。
所述晶体管通过在弛豫Si1-yGey集电区引入与应变Si1-xGex基区平行的超结p型层，不仅可以改善集电结空间电荷区电场分布、降低峰值电子温度、抑制碰撞电离和提高器件击穿电压，还可有效降低弛豫Si1-yGey集电区的掺杂浓度和声子散射几率、提高弛豫Si1-yGey集电区热导率，从而有效降低器件内部的温度分布，改善器件特征频率随温度变化的敏感性。
与常规应变Si/SiGe异质结双极晶体管相比，本发明所述的高热稳定性超结应变Si/SiGe异质结双极晶体管在具有大电流增益和高击穿电压特性的同时，器件内部的温度分布和特征频率随工作温度变化的敏感性得到显著改善，从而有效提高了应变Si/SiGe异质结双极晶体管的热稳定性。
附图说明
结合附图所进行的下列描述，可进一步理解本发明的目的和优点。在这些附图中：
图1示例了本发明实施例1的纵向剖面示意图；
图2示例了本发明实施例1的掺杂浓度分布图；
图3示例了本发明实施例2的纵向剖面示意图；
图4示例了本发明实施例2的掺杂浓度分布图；
图5示例了本发明实施例1、实施例2对器件电流增益的改善；
图6示例了本发明实施例1、实施例2对器件击穿电压BVCEO的改善；
图7(a)示例了常规器件温度分布；
图7(b)示例了发明实施例1温度分布；
图7(c)示例了发明实施例2温度分布；
图8示例了本发明实施例1、实施例2对器件特征频率随温度变化敏感性的改善；
具体实施方式
本发明实施例以具有单个发射极指的超结应变Si/SiGe HBT为例，对本发明内容进行具体表述。本发明涉及领域并不限制于此。
实施例1：
图1示出了具有一层超结p型层的应变Si/SiGe异质结双极晶体管的纵向剖面结构，包括依次外延生长的n+掺杂的SiGe虚拟衬底(10)，其Ge含量逐渐从0渐变为0.15；n+掺杂的弛豫Si1-yGey次集电区(11)，其Ge组分y＝0.15；n-掺杂的弛豫Si1-yGey集电区(12)，其Ge组分y＝0.15；超结p型层(13)，本征应变Si1-xGex下缓冲层(14)；p+掺杂的应变Si1-xGex基区(15)，其Ge组分含量x＝0.3；本征应变Si1-xGex上缓冲层(16)；p+掺杂的SiGe外基区(17)；n掺杂的应变Si发射区(18)；二氧化硅(SiO2)层(19)和金属引线(20)。
所述超结p型层(13)位于所述弛豫Si1-yGey集电区(12)内，同时平行于应变Si1-xGex基区(15)且位于本征应变Si1-xGex下缓冲层(14)下方100nm处，其厚度为50nm；，浓度为5×17cm-3。
图2示出了具有一层超结p型层应变Si/SiGe异质结双极晶体管的掺杂浓度分布。可以看出，本发明实施例1在所述弛豫Si1-yGey集电区(12)内引入了一层超结p型层，且超结p型层内的杂质浓度与n-集电区内杂质浓度相同。
本发明所述的具有高热稳定性的超结应变Si/SiGe异质结双极晶体管不仅可以设计为有一层超结p型层结构，还可根据器件的应用需要设计为多层超结p型层来进一步增大电流增益和击穿电压、改善器件内部的温度分布和特征频率温度敏感性，从而有效提高器件的热稳定性。
为此，本发明进一步以具有二层超结p型层的应变Si/SiGe异质结双极晶体管为例，给出适用于具有多层超结p型层的高热稳定性应变Si/SiGe异质结双极晶体管的设计。
实施例2：
图3示出了具有二层超结p型层的应变Si/SiGe异质结双极晶体管的纵向剖面结构，包括依次外延生长的n+掺杂的SiGe虚拟衬底(10)，其Ge含量逐渐从0渐变为0.15；n+掺杂的弛豫Si1-yGey次集电区(11)，其Ge组分y＝0.15；n-掺杂的弛豫Si1-yGey集电区(12)，其Ge组分y＝0.15；二层超结p型层下层(131)；二层超结p型层上层(132)；本征应变Si1-xGex下缓冲层(14)；p+掺杂的应变Si1-xGex基区(15)，其Ge组分含量x＝0.3；本征应变Si1-xGex上缓冲层(16)；p+掺杂的Si1-xGex外基区(17)，n掺杂的应变Si发射区(18)；二氧化硅(SiO2)层(19)和金属引线(20)。
所述二层超结p型层下层(131)和所述二层超结p型层上层(132)均位于所述弛豫Si1-yGey集电区(12)内，且同时平行于应变Si1-xGex基区(15)。其中，所述二层超结p型层上层(132)位于本征应变Si1-xGex下缓冲层(14)下方100nm处，其厚度为20nm；，浓度为5×17cm-3。所述二层超结p型层下层(131)位于所述二层超结p型层上层(132)下方50nm处，其厚度为30nm；，浓度为5×17cm-3。
图4示出了二层超结层应变Si/SiGe异质结双极晶体管的掺杂浓度分布。可以看出，本发明实施例2在所述弛豫Si1-yGey集电区(12)内引入了二层超结p型层，即所述二层超结p型层下层(131)和所述二层超结p型层上层(132)，且二层超结p型层内的杂质浓度与n-集电区内杂质浓度相同。
为了更好的展现本发明晶体管的性能，以本发明实施例为例，采用商用半导体仿真工具Silvaco TCAD分别对本发明实施例1、实施例2和常规应变Si/SiGe异质结双极晶体管进行器件建模及工艺仿真，并提取了相关的电学特性和频率特性。
图5示例了本发明实施例1、实施例2电流增益β随集电极电流Ic变化的关系曲线，并与常规应变Si/SiGe HBT进行了比较。可以看出，本发明实施例2具有最高的峰值电流增益，与常规应变Si/SiGe HBT相比提高了6.8％，同时实施例1保持了与常规应变Si/SiGeHBT相同的峰值电流增益。
图6示例了本发明实施例1、实施例2的基极电流IB与工作电压VCE的关系曲线，并与常规应变Si/SiGe HBT进行了比较。可以看出，本发明实施例1、实施例2的基极开路集电极-发射极间击穿电压BVCEO分别为2.5V和3V，与常规的应变Si/SiGe HBT相比，BVCEO分别提高了25％和50％。
图7(a)、(b)和(c)分别示例了常规应变Si/SiGe HBT、发明实施例1和发明实施例2的纵向剖面结构温度分布。可以看出，实施例1、实施例2的内部峰值温度分别为326.42K和324K，与常规应变Si/SiGe HBT相比，分别降低了8.12K和10.54K，且实施例1、实施例2的内部温度分布均低于常规应变Si/SiGe HBT的内部温度分布。
图8示例了本发明实施例1、实施例2的特征频率fT随温度变化的关系曲线图，并与常规应变Si/SiGe HBT进行了比较。可以看出，当工作温度在300K～380K范围变化时，与常规应变Si/SiGe HBT相比，本发明实施例1、实施例2的特征频率随温度变化的敏感性改善高达53.3％和53.2％，有利于器件的稳定工作。
上述结果均显示了本发明实施例的优越性，本发明对设计和制造可在射频微波功率领域稳定工作的兼具大电流增益、高击穿电压和、有高热稳定性的应变Si/SiGe HBT具有重要的指导意义。
Claims (2)
1.一种高热稳定性超结应变Si/SiGe异质结双极晶体管，其特征在于：
包括依次形成的SiGe虚拟衬底(10)，弛豫Si1-yGey次集电区(11)，弛豫Si1-yGey集电区(12)，超结p型层(13)，本征应变Si1-xGex下缓冲层(14)，应变Si1-xGex基区(15)，本征应变Si1-xGex上缓冲层(16)Si1-xGex外基区(17)，应变Si发射区(18)；
所述超结p型层(13)位于所述弛豫Si1-yGey集电区(12)内，同时平行于应变Si1-xGex基区(15)且位于本征应变Si1-xGex下缓冲层(14)下方100nm处；
所述超结p型层(13)的掺杂浓度与弛豫Si1-yGey集电区(12)的掺杂浓度相等，同时所述超结p型层可由一层或多层p型层组成，其中p型层总厚度不超过50nm，且当多层时各个p型层之间的间距为50nm。
2.根据权利要求1所述的高热稳定性超结应变Si/SiGe异质结双极晶体管，其特征在于：所述应变Si1-xGex基区(15)中的Ge组分含量x大于或等于0.3，且所述应变Si1-xGex基区(15)中的Ge组分含量x与所述弛豫Si1-yGey次集电区(11)和所述弛豫Si1-yGey集电区(12)中的Ge组分含量y需满足0<y<x。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610617990.2A CN106169498B (zh) | 2016-07-30 | 2016-07-30 | 高热稳定性超结应变Si/SiGe异质结双极晶体管 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610617990.2A CN106169498B (zh) | 2016-07-30 | 2016-07-30 | 高热稳定性超结应变Si/SiGe异质结双极晶体管 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106169498A true CN106169498A (zh) | 2016-11-30 |
| CN106169498B CN106169498B (zh) | 2019-03-05 |
Family
ID=58064995
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610617990.2A Active CN106169498B (zh) | 2016-07-30 | 2016-07-30 | 高热稳定性超结应变Si/SiGe异质结双极晶体管 |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106169498B (zh) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107046058A (zh) * | 2017-04-13 | 2017-08-15 | 中国电子科技集团公司第二十四研究所 | 一种具有应变Si组合发射区的异质结双极晶体管及其制备方法 |
| CN107169160A (zh) * | 2017-04-12 | 2017-09-15 | 西安电子科技大学 | 一种异质结双极晶体管非电离能量损失的计算方法 |
| CN107887430A (zh) * | 2017-11-09 | 2018-04-06 | 重庆邮电大学 | 衬底施加单轴应力的硅锗异质结双极晶体管及其制造方法 |
| CN108054203A (zh) * | 2017-12-22 | 2018-05-18 | 重庆邮电大学 | 一种绝缘体上硅锗衬底的异质结双极晶体管及其制造方法 |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07312371A (ja) * | 1994-05-17 | 1995-11-28 | Oki Electric Ind Co Ltd | ヘテロバイポーラトランジスタの製造方法 |
| EP0938140A2 (en) * | 1998-02-20 | 1999-08-25 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device with bipolar transistor |
| US20020139997A1 (en) * | 2001-03-29 | 2002-10-03 | Masahiro Tanomura | Compound semiconductor device having heterojunction bipolar transistor reduced in collector contact resistance by delta-doped region and process for fabrication thereof |
| CN103943670A (zh) * | 2014-04-12 | 2014-07-23 | 北京工业大学 | 超结集电区应变硅异质结双极晶体管 |
-
2016
- 2016-07-30 CN CN201610617990.2A patent/CN106169498B/zh active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07312371A (ja) * | 1994-05-17 | 1995-11-28 | Oki Electric Ind Co Ltd | ヘテロバイポーラトランジスタの製造方法 |
| EP0938140A2 (en) * | 1998-02-20 | 1999-08-25 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device with bipolar transistor |
| US20020139997A1 (en) * | 2001-03-29 | 2002-10-03 | Masahiro Tanomura | Compound semiconductor device having heterojunction bipolar transistor reduced in collector contact resistance by delta-doped region and process for fabrication thereof |
| CN103943670A (zh) * | 2014-04-12 | 2014-07-23 | 北京工业大学 | 超结集电区应变硅异质结双极晶体管 |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107169160A (zh) * | 2017-04-12 | 2017-09-15 | 西安电子科技大学 | 一种异质结双极晶体管非电离能量损失的计算方法 |
| CN107046058A (zh) * | 2017-04-13 | 2017-08-15 | 中国电子科技集团公司第二十四研究所 | 一种具有应变Si组合发射区的异质结双极晶体管及其制备方法 |
| CN107887430A (zh) * | 2017-11-09 | 2018-04-06 | 重庆邮电大学 | 衬底施加单轴应力的硅锗异质结双极晶体管及其制造方法 |
| CN108054203A (zh) * | 2017-12-22 | 2018-05-18 | 重庆邮电大学 | 一种绝缘体上硅锗衬底的异质结双极晶体管及其制造方法 |
| CN108054203B (zh) * | 2017-12-22 | 2020-01-10 | 重庆邮电大学 | 一种绝缘体上硅锗衬底的异质结双极晶体管及其制造方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106169498B (zh) | 2019-03-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106169498A (zh) | 高热稳定性超结应变Si/SiGe异质结双极晶体管 | |
| CN103117303B (zh) | 一种氮化物功率器件及其制造方法 | |
| CN101477999B (zh) | 用于功率器件的具有界面电荷岛soi耐压结构 | |
| CN104091825B (zh) | 超结集电区SiGe异质结双极晶体管 | |
| CN109192771B (zh) | 一种电荷存储型绝缘栅双极型晶体管及其制备方法 | |
| CN107342319A (zh) | 一种复合应变Si/SiGe异质结双极晶体管及其制备方法 | |
| CN109166916B (zh) | 一种绝缘栅双极型晶体管及其制备方法 | |
| CN105990423A (zh) | 横向双扩散场效应管 | |
| CN105870178A (zh) | 一种双向igbt器件及其制造方法 | |
| CN107305909A (zh) | 一种逆导型igbt背面结构及其制备方法 | |
| CN104681599B (zh) | 晶体管、放大器电路和集成电路 | |
| CN113270492A (zh) | 一种沟槽型GaN绝缘栅双极型晶体管 | |
| CN109346509B (zh) | 一种电荷存储型绝缘栅双极型晶体管及其制备方法 | |
| CN108054203B (zh) | 一种绝缘体上硅锗衬底的异质结双极晶体管及其制造方法 | |
| CN113611738B (zh) | 一种异质结注入的沟槽型GaN绝缘栅双极型晶体管 | |
| CN103943670B (zh) | 超结集电区应变硅异质结双极晶体管 | |
| CN106505100A (zh) | 异质接面双极晶体管 | |
| CN113540224B (zh) | 一种N衬底沟槽型GaN绝缘栅双极型晶体管 | |
| CN206322705U (zh) | 一种GaN HEMT器件 | |
| CN107731817B (zh) | 制造双极互补金属氧化半导体器件的方法及硅基多层结构 | |
| US10892332B2 (en) | Gate insulating layer having a plurality of silicon oxide layer with varying thickness | |
| CN106981510A (zh) | 一种碳化硅双极结型晶体管 | |
| CN103606560B (zh) | 减小微裂缝的影响，且用在微波集成电路和交换电路的高电荷迁移率晶体管 | |
| Sun et al. | Analysis of the novel Si/SiC heterojunction IGBT characteristics by TCAD simulation | |
| Zerounian et al. | SiGe HBT featuring fT> 600GHz at cryogenic temperature |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |