CN106158729B - The forming method of semiconductor structure - Google Patents
The forming method of semiconductor structure Download PDFInfo
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- CN106158729B CN106158729B CN201510163917.8A CN201510163917A CN106158729B CN 106158729 B CN106158729 B CN 106158729B CN 201510163917 A CN201510163917 A CN 201510163917A CN 106158729 B CN106158729 B CN 106158729B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
Abstract
A kind of forming method of semiconductor structure, comprising: substrate is provided；Form barrier layer in substrate surface, the barrier layer have with the first surface of substrate joint and the second surface opposite with first surface, the material of the barrier layer first surface is different from the material of second surface；Second surface on the barrier layer forms initiation layer, and the material of the barrier layer second surface is identical as the material of the initiation layer；Dielectric layer is formed in the initial layer surface.It is formed by the performance improvement of semiconductor structure.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of forming methods of semiconductor structure.
Background technique
In the art of semiconductor manufacturing, with the development of super large-scale integration (ULSI), the feature of semiconductor devices
Size (CD) constantly reduces, and the technique for forming metal interconnection structure is also challenged, and the delay time of metal interconnection structure is
Through close with the device gate delay time.The bring RC (R refers to that resistance, C refer to capacitor) due to the growth of connection length how is overcome to prolong
Increasing late is a urgent problem to be solved.Further, since mutually the effect of parasitic capacitance between metal interconnection structure is got worse, make
At device performance sharp fall, have become the key restriction factors that semi-conductor industry further develops.
In order to reduce parasitic capacitance, reduce RC retardation ratio, various metals interconnection structure is suggested, such as copper interconnection structure substitution
Traditional aluminium interconnection structure, correspondingly, also proposed copper electroplating technology (ECP, the electro- for being used to form copper interconnection structure
coppering plating).Since the resistivity of copper is low, the interconnection resistance of metal interconnection structure can reduce, and then reduce
The delay effect of metal interconnection structure.Moreover, copper has superior deelectric transferred ability, be conducive to improve metal interconnection structure
Reliability.
On the other hand, the capacitor reduced between metal interconnection structure equally can reduce delay, and parasitic capacitance with it is adjacent
The dielectric constant k of dielectric between metal interconnection structure is proportional, therefore, with low k (low k, abbreviation LK) material or surpasses
Low k (ultra low k, abbreviation ULK) the traditional silica material of material substitution is situated between metal interconnection structure as insulation
Material can, reduce metal interconnection structure between parasitic capacitance, delay effect can be reduced with this.
However, the ultralow-k material film that the prior art is formed is second-rate, it still will affect and be formed by semiconductor devices
Performance.
Summary of the invention
Problems solved by the invention is to provide a kind of forming method of semiconductor structure, is formed by the property of semiconductor structure
It can improve.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, comprising: provide substrate；It is serving as a contrast
Bottom surface forms barrier layer, and the barrier layer has and the first surface of substrate joint and opposite with first surface second
The material on surface, the barrier layer first surface is different from the material of second surface；Second surface on the barrier layer is formed
The material of initiation layer, the barrier layer second surface is identical as the material of the initiation layer；It is formed and is situated between in the initial layer surface
Matter layer.
Optionally, the material of the dielectric layer is ultra-low k dielectric material, and the dielectric coefficient of the ultra-low k dielectric material is small
In 2.5.
Optionally, the material of the dielectric layer is porous SiC OH material.
Optionally, the technique for forming the dielectric layer includes chemical vapor deposition process.
Optionally, it includes diethoxymethylsilane, oxygen that the technological parameter for forming the dielectric layer, which includes: technique presoma,
Gas, foaming agent and carrier gas, the foaming agent are alpha- terpinene, and the carrier gas is helium, and temperature is 200 DEG C~350 DEG C, gas
Pressure is 5 supports~10 supports, and the flow of diethoxymethylsilane is 1000 mg minutes~3000 mg minutes, the flow of oxygen
Flow for 200sccm~600sccm, foaming agent is 2000 mg minutes~4000 mg minutes, and the flow of carrier gas is
3000sccm~6000sccm.
Optionally, after forming the dielectric layer, UV treatment technique, the parameter packet of the ultraviolet treatment process are carried out
It includes: ultraviolet ray intensity 20mW/cm2~300mW/cm2, 300 DEG C~400 DEG C of temperature, 2 support of chamber pressure~10 supports, He flow
10000sccm~20000sccm, Ar flow 10000sccm~20000sccm, processing time are 100 seconds~500 seconds.
Optionally, the material of the initiation layer is SiCO；The technique for forming the initiation layer is chemical vapor deposition process.
Optionally, it includes diethoxymethylsilane, oxygen that the technological parameter for forming the initiation layer, which includes: process gas,
And helium, temperature are 200 DEG C~350 DEG C, air pressure is 5 supports~10 supports, and the flow of diethoxymethylsilane is 200 milli Grams Per Minutes
Clock~500 mg minute, the flow of oxygen are 400sccm~700sccm, and the flow of helium is 3000sccm~6000sccm.
Optionally, the material of the barrier layer first surface is SiCN；The material of the barrier layer second surface is SiCO.
Optionally, from the first surface on the barrier layer to second surface, nitrogen atom concentration in the barrier layer reduces,
Concentration of oxygen atoms improves.
Optionally, the barrier layer includes first material layer, the second material layer positioned at first material layer surface, Yi Jiwei
In the third material layer of third material surface.
Optionally, the forming step on the barrier layer includes: to form first material layer using the first depositing operation；Described
After first depositing operation, second material layer is formed using the second depositing operation；After second depositing operation, using
Three depositing operations form third material layer.
Optionally, the material of the first material layer is SiCN.
Optionally, the parameter of first depositing operation include: process gas include trimethyl silane or tetramethylsilane,
The flow of ammonia and nitrogen, trimethyl silane or tetramethylsilane is 200sccm~2000sccm, and the flow of ammonia is
200sccm~1000sccm, the flow of nitrogen are that 200sccm~1000sccm air pressure is 1 support~20 supports, and low frequency RF power is
0 watt~1000 watts, deposition chambers HFRF power is 500 watts~1500 watts, 250 DEG C~350 DEG C of temperature.
Optionally, the material of the second material layer is SiCON.
Optionally, the parameter of second depositing operation include: process gas include trimethyl silane or tetramethylsilane,
The flow of ammonia, nitrogen and oxygen, trimethyl silane or tetramethylsilane is 200sccm~2000sccm, and the flow of ammonia is
200sccm~1000sccm, the flow of nitrogen are 200sccm~1000sccm, and the flow of oxygen is 200sccm~800sccm,
Air pressure is 1 support~20 supports, and low frequency RF power is 0 watt~1000 watts, and HFRF power is 500 watts~1500 watts, temperature 250
DEG C~350 DEG C.
Optionally, in the process gas, the flow of oxygen is improved by zero to preset value, and the flow-reduction of nitrogen is extremely
Zero.
Optionally, the material of the third material layer is SiCO.
Optionally, the parameter of the third depositing operation include: process gas include trimethyl silane or tetramethylsilane,
And oxygen, the flow of trimethyl silane or tetramethylsilane are 200sccm~2000sccm, the flow of oxygen be 200sccm~
800sccm, air pressure are 1 support~20 supports, and low frequency RF power is 0 watt~1000 watts, and HFRF power is 500 watts~1500
Watt, 250 DEG C~350 DEG C of temperature.
Optionally, the electric interconnection structure that the substrate includes, and the surface of the substrate exposes the electric interconnection structure,
The material of the electric interconnection structure includes copper；The barrier layer is located at the electric interconnection structure surface.
Compared with prior art, technical solution of the present invention has the advantage that
In forming method of the invention, barrier layer is formed in substrate surface, forms initiation layer in the barrier layer surface.Institute
Stating initiation layer is the seed layer for being subsequently formed dielectric layer, the initiation layer with to be subsequently formed with the dielectric layer of initial layer surface be low
K dielectric layer.The barrier layer especially makes the surface of the electric interconnection structure in substrate for protecting substrate surface；Moreover, the resistance
Barrier is used to improve the adhesion strength between initiation layer and dielectric layer and substrate；In addition, the barrier layer can also be used to as quarter
Lose the etching stop layer of dielectric layer and initiation layer.The first surface and substrate contact on the barrier layer, the second of the barrier layer
Surface is in contact with initiation layer, and the first surface material on the barrier layer is different from initiation layer, and second surface material and just
Beginning layer is identical, therefore, crystal lattice difference is not present between the material of the barrier layer second surface and the material of initiation layer, so as to
Enough weaken the stress between initiation layer and barrier layer, thus avoids causing to occur between initiation layer and barrier layer in the subsequent process
Layering or peeling, improve the adhesion strength between barrier layer and initiation layer.Therefore, it is formed by the stabilization of semiconductor structure
Property and reliability improve, performance improvement.
Further, the material of the barrier layer first surface is SiCN；The material of the barrier layer second surface is SiCO；
Moreover, from the first surface on the barrier layer to second surface, the nitrogen atom concentration reduction in the barrier layer, concentration of oxygen atoms
It improves；Since the second surface on the barrier layer is identical as the initial layer material being in contact, and the barrier layer second surface
Material is gradually to the material transition of barrier layer first surface, i.e., the described barrier layer is from second surface to first surface, and material is gradually
It is equal to the material of initiation layer, is weakening the stress between barrier layer and initiation layer meanwhile, it is capable to avoid inside the barrier layer
Material lattice gradually change, prevent from generating stress inside barrier layer, so as to prevent from being layered inside barrier layer.
Further, the material of the dielectric layer is ultra-low k dielectric material, and the dielectric coefficient of the ultra-low k dielectric material is small
In 2.5；The material of the initiation layer is SiCO, and the initiation layer is as the seed layer for forming dielectric layer.Due to Jie of dielectric layer
Electric constant is low, can reduce the parasitic capacitance in semiconductor structure, to reduce RC retardation ratio effect, improves the property of semiconductor structure
Energy.
Detailed description of the invention
Fig. 1 is a kind of the schematic diagram of the section structure of semiconductor structure embodiment；
Fig. 2 to Fig. 7 is the schematic diagram of the section structure of the forming process of the semiconductor structure of the embodiment of the present invention.
Specific embodiment
As stated in the background art, it is formed by the second-rate of ultralow-k material film, still will affect and be formed by semiconductor device
The performance of part.
Specifically referring to FIG. 1, Fig. 1 is a kind of the schematic diagram of the section structure of semiconductor structure embodiment, comprising: device layer
100；Copper interconnection structure 101 in device layer 100, the top surface of the copper interconnection structure 101 and 100 surface of device layer
It flushes；Positioned at the barrier layer 102 on 101 surface of the device layer 100 and copper interconnection structure；Positioned at 102 surface of barrier layer, ultralow k is situated between
Matter layer.
Wherein, the material of the ultra-low k dielectric layer is porous SiC OH material, and the material on the barrier layer 102 is N doping
Silicon carbide (NDC).The ultra-low k dielectric layer includes initiation layer 103 and the porous layer 104 positioned at 103 surface of initiation layer.
The barrier layer 102 for protecting the copper interconnection structure 101, and for improve initiation layer 103 and copper interconnection structure 101 it
Between adhesion strength；In addition, the material on the barrier layer 102 is different from the material of initiation layer 103, the material on the barrier layer 102
The etching selection ratio with higher between ultra-low k dielectric layer, the barrier layer 102 can also be in subsequent etching ultra-low k dielectrics
When layer, as etching stop layer.
However, in the back-end process (Back End Of Line, abbreviation BEOL) of manufacture of semiconductor, the barrier layer
Defect is easy to produce between 102 and ultra-low k dielectric layer.For example, the ultra-low k dielectric layer is performed etching or chemical machinery throw
When light (Chemical Mechanical Polishing, abbreviation CMP) technique, it be easy to cause barrier layer 102 and ultra-low k dielectric
Layer and between occur layering or peeling, cause the reliability and decrease in yield of semiconductor devices.
Find after study, cause barrier layer 102 and ultra-low k dielectric layer and between layering occurs or the reason of peeling
It is: since the barrier layer 102 is different from the material of ultra-low k dielectric layer, especially between barrier layer 102 and initiation layer 103
Material it is different, then between the barrier layer 102 and the material of initiation layer 103 there are crystal lattice difference, therefore the barrier layer 102
There are stress between ultra-low k dielectric layer；When the ultra-low k dielectric layer is performed etching or chemically-mechanicapolish polished, outside is applied
The stress that the heat or mechanical force added will lead between barrier layer 102 and initiation layer 103 is released, to cause the barrier layer
Layering or removing occur between 102 and ultra-low k dielectric layer.
To solve the above-mentioned problems, the present invention provides a kind of forming method of semiconductor structure.Wherein, in substrate surface shape
At barrier layer, initiation layer is formed in the barrier layer surface.The initiation layer is the seed layer for being subsequently formed dielectric layer, described first
Beginning layer and be subsequently formed with the dielectric layer of initial layer surface be low-k dielectric layer.The first surface and substrate contact on the barrier layer,
The second surface on the barrier layer is in contact with initiation layer, and the first surface material on the barrier layer is different from initiation layer, and
Second surface material is identical as initiation layer, therefore, does not deposit between the material of the barrier layer second surface and the material of initiation layer
In crystal lattice difference, so as to weaken the stress between initiation layer and barrier layer, thus avoid causing in the subsequent process initial
Layering or peeling occur between layer and barrier layer, improves the adhesion strength between barrier layer and initiation layer.Therefore, it is formed
Semiconductor structure stability and reliability improve, performance improvement.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 2 to Fig. 7 is the schematic diagram of the section structure of the forming process of the semiconductor structure of the embodiment of the present invention.
Referring to FIG. 2, providing substrate 200.
In the present embodiment, the electric interconnection structure 201 that the substrate 200 includes, and the surface of the substrate 200 exposes
The material of the electric interconnection structure 201, the electric interconnection structure 201 includes copper；The barrier layer being subsequently formed is located at the electricity mutually
Link 201 surface of structure.In the present embodiment, the surface of the electric interconnection structure is flushed with 200 surface of substrate.In other embodiments
In, the surface of the electric interconnection structure 201 can be higher than or the first 200 surface of substrate.
In the present embodiment, the substrate 200 include: semiconductor base, positioned at semiconductor substrate surface insulating layer, be located at
The top surface of electric interconnection structure 201 in insulating layer, the electric interconnection structure 201 is flushed with surface of insulating layer.It is subsequently formed
Barrier layer be located at 201 surface of electric interconnection structure, for protecting the electric interconnection structure 201, prevent extraneous impurity and
Steam invades the electric interconnection structure 201.
The semiconductor base include silicon substrate, silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator substrate, on insulator
Germanium substrate, glass substrate or III-V compound substrate (such as gallium nitride substrate or gallium arsenide substrate etc.).
The substrate 200 further includes the device architecture for being formed in the semiconductor substrate surface, and the device architecture includes:
One of the gate structure of transistor, fuse-wires structure, resistance, capacitor, inductance are a variety of.The insulating layer is partly led positioned at described
Body substrate surface, and the device architecture is covered, the material of the insulating layer is silica, silicon nitride, silicon oxynitride, low K
One of dielectric material, ultralow K dielectric material are a variety of.
In one embodiment, the electric interconnection structure 201 can also be located at the semiconductor substrate surface or device architecture
Surface, the electric interconnection structure 201 is electrically interconnected for making to realize between device architecture；The material of the electric interconnection structure 201
Including metal or metallic compound, such as copper, tungsten, aluminium, titanium, pinch, one of titanium nitride and tantalum nitride or multiple combinations.It is described
Electric interconnection structure 201 includes: to be formed in the conductive plunger of semiconductor substrate surface or device architecture surface and be formed in conduction
Conductive layer at the top of plug, the conductive layer realize electrical connection for making between conductive plunger.
In another embodiment, the substrate is semiconductor base, is formed with conductive structure in the semiconductor base, institute
The surface for stating conductive structure is flushed with the surface of semiconductor base.The conductive structure can be conductive layer, the conductive layer energy
It is enough formed in the surface of ion doped region in semiconductor base, the conductive structure being subsequently formed is located at the conductive layer surface, uses
It is biased in the ion doped region.In addition, the conductive structure can also be conductive plunger, the conductive plunger can
For through-silicon via structure (TSV, Through Silicon Via).
In the present embodiment, subsequent to need to form dielectric layer on 200 surface of substrate, the material of the dielectric layer is ultralow k
Dielectric material, the ultra-low k dielectric material inside is porous state, so that extraneous pollution and steam easily propagates through the medium
Layer simultaneously causes to corrode to the electric interconnection structure, therefore, it is necessary to before forming dielectric layer, in 201 table of electric interconnection structure
Face forms barrier layer, and the density on the barrier layer is higher than the density of the dielectric layer, to stop extraneous pollution or steam direct
Contact the electric interconnection structure.
However, the density and material due to the barrier layer are different from the dielectric layer, the barrier material
Lattice constant is different from the lattice constant of dielectric layer, generates so that having between the barrier layer and dielectric layer because of lattice mismatch
Stress；After being subsequently formed dielectric layer, back segment processing is carried out to the dielectric layer surface, such as perform etching to dielectric layer
Or when carrying out CMP process to dielectric layer surface, technological temperature or external apply give the mechanical force of dielectric layer and are easy to make
It is released at the stress between barrier layer and dielectric layer, layering or stripping occurs between barrier layer and dielectric layer to easily cause
From；And after layering or removing occur between the barrier layer and dielectric layer, what the interface of the barrier layer and dielectric layer generated
Defect not only easily causes the variation of electrical insulation capability, is also easy to Accumulating charge, in addition, being also easy to introduce external contamination, to resistance
Barrier and dielectric layer damage；Therefore, it is easy to cause the degradation for being formed by conductive structure.
To solve the above-mentioned problems, in the present embodiment, 200 surface of substrate formed barrier layer, the barrier layer have with
The first surface and the second surface opposite with first surface of 200 joint of substrate, moreover, the barrier layer second surface
Material is identical as the material for the initiation layer being subsequently formed, and the material of the material of the barrier layer first surface and the initiation layer is not
Together, and the density of material of the barrier layer first surface be greater than second surface density of material.
Wherein, the initiation layer is as the seed layer for forming dielectric layer, therefore the initiation layer is formed directly into barrier layer
Surface；Since the material of the barrier layer second surface is identical as the material of initiation layer, the barrier layer and initiation layer it
Between lattice structure difference it is smaller, the stress between the barrier layer and initiation layer is smaller or even is not present, thus, even if after
It is continuous dielectric layer and initiation layer to be performed etching or polishing treatment, it is also difficult to which that stress discharges and causes between barrier layer and initiation layer
It is layered, thus improves the reliability and yield rate for being formed by semiconductor structure.
In the present embodiment, the material of the barrier layer first surface is SiCN；The material of the barrier layer second surface
For SiCO.Since the initial layer material being subsequently formed is SiCO, and the second surface on barrier layer is in contact with initiation layer, by institute
The material for stating initiation layer is identical as barrier material, and the difference of lattice structure is smaller between the barrier layer and initiation layer, can
It prevents that layering or removing occur between the barrier layer and initiation layer.And the first surface and electric interconnection structure on the barrier layer
201 are in contact, and the density of material of the barrier layer first surface is greater than the density of material of second surface, then with electric interconnection structure
201 partial barriers being in contact can be used in that the electric interconnection structure 201 is protected to corrode from external contamination.
Moreover, in the present embodiment, from the first surface on the barrier layer to second surface, the nitrogen in the barrier layer is former
Sub- concentration reduces, concentration of oxygen atoms improves, i.e., from first surface to second surface, material is faded to by SiCN on the described barrier layer
SiCO；Since the material inside barrier layer gradually changes, then can prevent from causing crystalline substance because of material mutation inside the barrier layer
The mutation of lattice structure is then also not easy that layering or peeling occur in the subsequent process inside barrier layer.
In the present embodiment, the barrier layer include first material layer, positioned at first material layer surface second material layer,
And the third material layer positioned at second material layer surface；Wherein, the material of the first material layer is SiCN, the third material
The material of the bed of material be SiCO, and the material of second material layer be SiCON, and inside the second material layer from first material layer extremely
Third material layer nitrogen atom concentration gradually decreases, concentration of oxygen atoms is gradually increased.
The barrier layer forming step to the present embodiment is illustrated below.
Referring to FIG. 3, forming first material layer 202 on 200 surface of substrate using the first depositing operation.
In the present embodiment, the material of the first material layer 202 is SiCN (nitrogen doped silicon carbide, abbreviation NDC)；It is described
First material layer 202 is in contact with substrate 200 and electric interconnection structure 201, and the first material layer 202 and substrate 200 and electricity are mutual
The surface i.e. first surface on barrier layer that connection structure 201 is in contact；The density of the first material layer 202, which is greater than, to be subsequently formed
The density of third material layer, initiation layer or dielectric layer, the first material layer 202 can be effectively prevented foreign matter or steam
It across the dielectric layer being subsequently formed, initiation layer and is directly contacted with electric interconnection structure 201, thus prevents the electric interconnection structure
201 suffer erosion.
Secondly as the material of the first material layer 202 is different from the material of the dielectric layer or initiation layer that are subsequently formed,
The first material layer 202 is relative to the dielectric layer or initiation layer etching selection ratio with higher, the first material layer
202 can be as the etching stop layer of dielectric layer described in subsequent etching and initiation layer.
In the present embodiment, the first material layer 202 with a thickness of 100 angstroms~200 angstroms；The first material layer 202
Material be SiCN, formed the first material layer 202 the first depositing operation be chemical vapor deposition process；Described first is heavy
It includes trimethyl silane or tetramethylsilane, ammonia and nitrogen, trimethyl silane or four that the parameter of product technique, which includes: process gas,
The flow of methyl-monosilane is 200sccm~2000sccm, and the flow of ammonia is 200sccm~1000sccm, and the flow of nitrogen is
200sccm~1000sccm air pressure is 1 support~20 supports, and low frequency RF power is 0 watt~1000 watts, deposition chambers high-frequency radio frequency function
Rate is 500 watts~1500 watts, 250 DEG C~350 DEG C of temperature.
By controlling the flow proportional of process gas, can in the material to first material layer 202 nitrogen-atoms concentration into
Row adjustment.
Referring to FIG. 4, after first depositing operation, using the second depositing operation on 202 surface of first material layer
Form second material layer 203.
In the present embodiment, the third material layer that the second material layer 203 is located at first material layer 202 and is subsequently formed
Between, as the transition between first material layer 202 and third material layer.In the present embodiment, the material of the first material layer
Material is SiCN, and the third material layer being subsequently formed is identical as the initial layer material being subsequently formed, and is SiCO, then second material
The material of the bed of material 203 is SiCON.
In the present embodiment, the second material layer 203 Zi the surface contacted with first material layer 202 to third material
The surface of layer contact, the concentration of the nitrogen-atoms in 203 material of second material layer are gradually decrease to zero, concentration of oxygen atoms from zero gradually
It improves to preset value.
In the present embodiment, the second material layer 203 with a thickness of 100 angstroms~200 angstroms；The second material layer 203
Material is SiCON, and the second depositing operation for forming the second material layer 203 is chemical vapor deposition process, and described second is heavy
It includes trimethyl silane or tetramethylsilane, ammonia, nitrogen and oxygen, trimethyl silicane that the parameter of product technique, which includes: process gas,
The flow of alkane or tetramethylsilane is 200sccm~2000sccm, and the flow of ammonia is 200sccm~1000sccm, nitrogen
Flow is 200sccm~1000sccm, and the flow of oxygen is 200sccm~800sccm, and air pressure is 1 support~20 supports, low frequency radio frequency
Power is 0 watt~1000 watts, and HFRF power is 500 watts~1500 watts, 250 DEG C~350 DEG C of temperature.
In the process gas, the flow of oxygen is improved by zero to preset value, for adjusting in second material layer 203
Oxygen atom content；The changes in flow rate range of the oxygen is 0sccm~800sccm；The flow-reduction of nitrogen is to zero, for adjusting
Nitrogen atom content in second material layer 203；The changes in flow rate range of the nitrogen is 0sccm~1000sccm；The ammonia
Changes in flow rate range be 0sccm~1000sccm.
Referring to FIG. 5, being formed using third depositing operation in second material layer 203 after second depositing operation
Third material layer 204.
In the present embodiment, the third material layer 204 is directly contacted with the initiation layer being subsequently formed, and the third
The material of material layer 204 is identical as the material of the initiation layer, can weaken and answer between the initiation layer and third material layer 204
Difference in lattice structure and the stress generated, so as to prevent in the subsequent process, because between third material layer 204 and initiation layer
Stress is released and layering or peeling occurs, so that the adhesion strength between third material layer 204 and initiation layer improves, from
And improve the reliability for being formed by semiconductor structure.
In the present embodiment, the first material layer 202, second material layer 203 and third material layer 204, which are constituted, is located at lining
The barrier layer on 201 surface of bottom 200 and electric interconnection structure, and the surface of the third material layer 204 is the second of the barrier layer
Surface, it is subsequent to form initiation layer in the third material surface, using the initiation layer as seed layer, form ultra-low k dielectric
The dielectric layer of material.
In the present embodiment, the third material layer 204 with a thickness of 100 angstroms~200 angstroms；The third material layer 204
Material be SiCO, formed the third material layer 204 third depositing operation be chemical vapor deposition process；The third is heavy
It includes trimethyl silane or tetramethylsilane and oxygen that the parameter of product technique, which includes: process gas, trimethyl silane or tetramethyl
The flow of silane is 200sccm~2000sccm, and the flow of oxygen is 200sccm~800sccm, and air pressure is 1 support~20 supports, low
Frequency radio-frequency power is 0 watt~1000 watts, and HFRF power is 500 watts~1500 watts, 250 DEG C~350 DEG C of temperature.
Wherein, by controlling the flow proportional of process gas, can in the material to third material layer 204 oxygen atom it is dense
Degree is adjusted.
Referring to FIG. 6, the second surface on the barrier layer forms initiation layer 205, the material of the barrier layer second surface
Material is identical as the material of the initiation layer 205, and the material of the material of the barrier layer first surface and the initiation layer 205 is not
Together.
The initiation layer 205 is as the seed layer for being subsequently formed dielectric layer.In the present embodiment, the initiation layer 205
Material is SiCO, and the dielectric layer material being subsequently formed is the porous SiC OH material formed based on SiCO material；The initiation layer and
The dielectric layer being subsequently formed is ultra-low k dielectric material layer, for being electrically isolated the electric interconnection structure.
In the present embodiment, the material of the barrier layer second surface is identical as the material of the initiation layer 205, i.e., described
The material of third material layer 204 is identical as the material of initiation layer 205, reduces the stress between barrier layer and initiation layer 205 with this,
It avoids in the subsequent process, layering or peeling occurs between barrier layer and initiation layer 205.
In the present embodiment, the technique for forming the initiation layer 205 is chemical vapor deposition process；Form the initiation layer
205 technological parameter includes: that process gas includes diethoxymethylsilane, oxygen and helium, and temperature is 200 DEG C~350 DEG C,
Air pressure is 5 supports~10 supports, and the flow of diethoxymethylsilane is 200 mg minutes~500 mg minutes, the flow of oxygen
For 400sccm~700sccm, the flow of helium is 3000sccm~6000sccm.
In other embodiments, the technique for forming the initiation layer 205 can also be atom layer deposition process or physics gas
Phase depositing operation.
Wherein, in the technique for forming the initiation layer 205, temperature is lower, can make to be formed by 205 density of initiation layer
Lower, then the initiation layer 205 can provide seed layer to be subsequently formed the dielectric layer of ultra-low k dielectric material, being capable of shape with this
At porous media material.
Referring to FIG. 7, forming dielectric layer 206 on 205 surface of initiation layer.
The material of the dielectric layer 206 is porous media material, and the dielectric layer 206 is ultra-low k dielectric material, described
The dielectric coefficient of ultra-low k dielectric material is less than 2.5.In the present embodiment, the material of the dielectric layer 206 is based on described initial
The porous SiC OH material that layer 205 is formed.In the present embodiment, the initiation layer 205 constitutes ultralow k with the dielectric layer 206 and is situated between
The material bed of material.
The technique for forming the dielectric layer 206 includes chemical vapor deposition process；Form the technique ginseng of the dielectric layer 206
Number includes: that technique presoma includes diethoxymethylsilane, oxygen, foaming agent and carrier gas, and the foaming agent is alpha- pine
Oily alkene, the carrier gas are helium, and temperature is 200 DEG C~350 DEG C, and air pressure is 5 supports~10 supports, the flow of diethoxymethylsilane
It is 1000 mg minutes~3000 mg minutes, the flow of oxygen is 200sccm~600sccm, and the flow of foaming agent is
2000 mg minutes~4000 mg minutes, the flow of carrier gas is 3000sccm~6000sccm.
Wherein, the foaming agent is alpha- terpinene, abbreviation ATRP；The foaming agent is for making to be formed by material
Portion is in cellular, and the dielectric constant for being formed by dielectric layer 206 is reduced with this, forms ultra-low k dielectric material.
To sum up, in the present embodiment, barrier layer is formed in substrate surface, forms initiation layer in the barrier layer surface.It is described
Initiation layer is the seed layer for being subsequently formed dielectric layer, the initiation layer with to be subsequently formed with the dielectric layer of initial layer surface be ultralow
K dielectric layer.The barrier layer especially makes the surface of the electric interconnection structure in substrate for protecting substrate surface；Moreover, the resistance
Barrier is used to improve the adhesion strength between initiation layer and dielectric layer and substrate；In addition, the barrier layer can also be used to as quarter
Lose the etching stop layer of dielectric layer and initiation layer.The first surface and substrate contact on the barrier layer, the second of the barrier layer
Surface is in contact with initiation layer, and the first surface material on the barrier layer is different from initiation layer, and second surface material and just
Beginning layer is identical, therefore, crystal lattice difference is not present between the material of the barrier layer second surface and the material of initiation layer, so as to
Enough weaken the stress between initiation layer and barrier layer, thus avoids causing to occur between initiation layer and barrier layer in the subsequent process
Layering or peeling, improve the adhesion strength between barrier layer and initiation layer.Therefore, it is formed by the stabilization of semiconductor structure
Property and reliability improve, performance improvement.
In addition, the material of the barrier layer first surface is SiCN；The material of the barrier layer second surface is SiCO；And
And from the first surface on the barrier layer to second surface, the nitrogen atom concentration in the barrier layer is reduced, concentration of oxygen atoms mentions
It is high；Since the second surface on the barrier layer is identical as the initial layer material being in contact, and the material of the barrier layer second surface
Material is gradually to the material transition of barrier layer first surface, i.e., from second surface to first surface, material gradually becomes on the described barrier layer
It is same as the material of initiation layer, is weakening the stress between barrier layer and initiation layer meanwhile, it is capable to avoid inside the barrier layer
Material lattice gradually changes, and prevents from generating stress inside barrier layer, so as to prevent from being layered inside barrier layer.
Moreover, the material of the dielectric layer is ultra-low k dielectric material, the dielectric coefficient of the ultra-low k dielectric material is less than
2.5；The material of the initiation layer is SiCO, and the initiation layer is as the seed layer for forming dielectric layer.Due to the dielectric of dielectric layer
Constant is low, can reduce the parasitic capacitance in semiconductor structure, to reduce RC retardation ratio effect, improves the property of semiconductor structure
Energy.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (17)
1. a kind of forming method of semiconductor structure characterized by comprising
Substrate is provided；
Form barrier layer in substrate surface, the barrier layer have with the first surface of substrate joint and with first surface phase
Pair second surface, the material of the barrier layer first surface is SiCN, and the material of the barrier layer second surface is SiCO, from
The first surface on the barrier layer is to second surface, and the nitrogen atom concentration in the barrier layer reduces, concentration of oxygen atoms improves；
Second surface on the barrier layer forms initiation layer, the material of the barrier layer second surface and the material of the initiation layer
Expect identical；
Dielectric layer is formed in the initial layer surface, the material of the dielectric layer is ultra-low k dielectric material, the ultra-low k dielectric
The dielectric coefficient of material is less than 2.5.
2. the forming method of semiconductor structure as described in claim 1, which is characterized in that the material of the dielectric layer is porous
SiCOH material.
3. the forming method of semiconductor structure as claimed in claim 2, which is characterized in that form the technique packet of the dielectric layer
Include chemical vapor deposition process.
4. the forming method of semiconductor structure as claimed in claim 3, which is characterized in that form the technique ginseng of the dielectric layer
Number includes: that technique presoma includes diethoxymethylsilane, oxygen, foaming agent and carrier gas, and the foaming agent is alpha- pine
Oily alkene, the carrier gas are helium, and temperature is 200 DEG C~350 DEG C, and air pressure is 5 supports~10 supports, the flow of diethoxymethylsilane
It is 1000 mg minutes~3000 mg minutes, the flow of oxygen is 200sccm~600sccm, and the flow of foaming agent is
2000 mg minutes~4000 mg minutes, the flow of carrier gas is 3000sccm~6000sccm.
5. the forming method of semiconductor structure as claimed in claim 4, which is characterized in that after forming the dielectric layer, into
Row UV treatment technique, the parameter of the ultraviolet treatment process include: that ultraviolet ray intensity is 20mW/cm2~300mW/cm2, temperature
300 DEG C~400 DEG C of degree, 2 support of chamber pressure~10 supports, He flow 10000sccm~20000sccm, Ar flow 10000sccm~
20000sccm, processing time are 100 seconds~500 seconds.
6. the forming method of semiconductor structure as described in claim 1, which is characterized in that the material of the initiation layer is
SiCO；The technique for forming the initiation layer is chemical vapor deposition process.
7. the forming method of semiconductor structure as claimed in claim 6, which is characterized in that form the technique ginseng of the initiation layer
It includes diethoxymethylsilane, oxygen and helium that number, which includes: process gas, and temperature is 200 DEG C~350 DEG C, air pressure be 5 supports~
10 supports, the flow of diethoxymethylsilane are 200 mg minutes~500 mg minutes, the flow of oxygen be 400sccm~
700sccm, the flow of helium are 3000sccm~6000sccm.
8. the forming method of semiconductor structure as described in claim 1, which is characterized in that the barrier layer includes the first material
Layer, the second material layer positioned at first material layer surface and the third material layer positioned at third material surface.
9. such as the forming method for the semiconductor structure that claim 8 is stated, which is characterized in that the forming step packet on the barrier layer
It includes: first material layer is formed using the first depositing operation；After first depositing operation, formed using the second depositing operation
Second material layer；After second depositing operation, third material layer is formed using third depositing operation.
10. the forming method of semiconductor structure as claimed in claim 9, which is characterized in that the material of the first material layer
For SiCN.
11. the forming method of semiconductor structure as claimed in claim 10, which is characterized in that the ginseng of first depositing operation
It includes trimethyl silane or tetramethylsilane, ammonia and nitrogen that number, which includes: process gas, trimethyl silane or tetramethylsilane
Flow is 200sccm~2000sccm, and the flow of ammonia is 200sccm~1000sccm, the flow of nitrogen be 200sccm~
1000sccm air pressure is 1 support~20 supports, and low frequency RF power is 0 watt~1000 watts, and deposition chambers HFRF power is 500 watts
~1500 watts, 250 DEG C~350 DEG C of temperature.
12. the forming method of semiconductor structure as claimed in claim 9, which is characterized in that the material of the second material layer
For SiCON.
13. the forming method of semiconductor structure as claimed in claim 12, which is characterized in that the ginseng of second depositing operation
It includes trimethyl silane or tetramethylsilane, ammonia, nitrogen and oxygen that number, which includes: process gas, trimethyl silane or tetramethyl
The flow of silane is 200sccm~2000sccm, and the flow of ammonia is 200sccm~1000sccm, and the flow of nitrogen is
200sccm~1000sccm, the flow of oxygen are 200sccm~800sccm, and air pressure is 1 support~20 supports, and low frequency RF power is
0 watt~1000 watts, HFRF power is 500 watts~1500 watts, 250 DEG C~350 DEG C of temperature.
14. the forming method of semiconductor structure as claimed in claim 13, which is characterized in that in the process gas, oxygen
The flow of gas is improved by zero to preset value, the flow-reduction of nitrogen to zero.
15. the forming method of semiconductor structure as claimed in claim 9, which is characterized in that the material of the third material layer
For SiCO.
16. the forming method of semiconductor structure as claimed in claim 15, which is characterized in that the ginseng of the third depositing operation
Number includes: that process gas includes trimethyl silane or tetramethylsilane and oxygen, the flow of trimethyl silane or tetramethylsilane
For 200sccm~2000sccm, the flow of oxygen is 200sccm~800sccm, and air pressure is 1 support~20 supports, low frequency RF power
It is 0 watt~1000 watts, HFRF power is 500 watts~1500 watts, 250 DEG C~350 DEG C of temperature.
17. the forming method of semiconductor structure as described in claim 1, which is characterized in that the electrical interconnection that the substrate includes
Structure, and the surface of the substrate exposes the electric interconnection structure, the material of the electric interconnection structure includes copper；The blocking
Layer is located at the electric interconnection structure surface.
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| CN108933100B (en) * | 2017-05-24 | 2021-04-30 | 中芯国际集成电路制造(上海)有限公司 | Interconnection structure and manufacturing method thereof |
| CN111201602B (en) * | 2019-11-22 | 2021-04-27 | 长江存储科技有限责任公司 | Memory device and hybrid spacer thereof |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6218314B1 (en) * | 1999-04-01 | 2001-04-17 | Taiwan Semiconductor Manufacturing Company | Silicon dioxide-oxynitride continuity film as a passivation film |
| CN1691323A (en) * | 2004-04-19 | 2005-11-02 | 国际商业机器公司 | Structure to improve adhesion between top cvd low-K dielectiric and dielectric capping layer |
| CN1930669A (en) * | 2004-03-15 | 2007-03-14 | 应用材料公司 | Plasma treatment to improve adhesion of low k dielectrics |
| CN101064251A (en) * | 2006-04-24 | 2007-10-31 | 台湾积体电路制造股份有限公司 | Method for forming semiconductor structure and semiconductor structure |
| CN103928391A (en) * | 2013-01-10 | 2014-07-16 | 中芯国际集成电路制造(上海)有限公司 | Forming method of semiconductor structure |
| CN105575886A (en) * | 2014-10-14 | 2016-05-11 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of interconnection dielectric layer, interconnection dielectric layer and manufacturing method of interconnection layer |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US20050087517A1 (en) * | 2003-10-09 | 2005-04-28 | Andrew Ott | Adhesion between carbon doped oxide and etch stop layers |
-
2015
- 2015-04-08 CN CN201510163917.8A patent/CN106158729B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6218314B1 (en) * | 1999-04-01 | 2001-04-17 | Taiwan Semiconductor Manufacturing Company | Silicon dioxide-oxynitride continuity film as a passivation film |
| CN1930669A (en) * | 2004-03-15 | 2007-03-14 | 应用材料公司 | Plasma treatment to improve adhesion of low k dielectrics |
| CN1691323A (en) * | 2004-04-19 | 2005-11-02 | 国际商业机器公司 | Structure to improve adhesion between top cvd low-K dielectiric and dielectric capping layer |
| CN101064251A (en) * | 2006-04-24 | 2007-10-31 | 台湾积体电路制造股份有限公司 | Method for forming semiconductor structure and semiconductor structure |
| CN103928391A (en) * | 2013-01-10 | 2014-07-16 | 中芯国际集成电路制造(上海)有限公司 | Forming method of semiconductor structure |
| CN105575886A (en) * | 2014-10-14 | 2016-05-11 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of interconnection dielectric layer, interconnection dielectric layer and manufacturing method of interconnection layer |
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