CN103165576B - Semiconductor device and manufacture method thereof - Google Patents
Semiconductor device and manufacture method thereof Download PDFInfo
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- CN103165576B CN103165576B CN201110413955.6A CN201110413955A CN103165576B CN 103165576 B CN103165576 B CN 103165576B CN 201110413955 A CN201110413955 A CN 201110413955A CN 103165576 B CN103165576 B CN 103165576B
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Abstract
A kind of semiconductor device and manufacture method thereof.Described semiconductor device comprises: Semiconductor substrate; Be positioned at the etching barrier layer in Semiconductor substrate and ultra-low K dielectric layer successively, the dielectric constant range of described ultra-low K dielectric layer comprises: 2.2 ~ 2.5, and described ultra-low K dielectric layer has fine and close structure; Be positioned in Semiconductor substrate, and successively by ultra-low K dielectric layer and etching barrier layer the metal wiring layer that surrounds or conductive plunger.Described manufacture method comprises: provide Semiconductor substrate; Form etching barrier layer and ultra-low K dielectric layer successively on a semiconductor substrate; Etching ultra-low K dielectric layer and etching barrier layer are to exposing Semiconductor substrate successively, form groove; Fill full metal level in the trench; Planarization is carried out to metal level, the upper surface of metal level and the upper surface flush of ultra-low K dielectric layer.The present invention can improve stability and the reliability of semiconductor device.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of semiconductor device and manufacture method thereof.
Background technology
Along with semiconductor device is constantly to high density, highly integrated and high-performance future development, semiconductor technology is also continuous to profound and subtle rice future development, has higher requirement to manufacturing process and material.
At present in semiconductor fabrication process, forming integrated circuit to connect all parts, usually using the metal material such as copper with relative high conductivity to connect up, namely metal line.And be generally conductive plunger for what connect between metal line.Existing conductive plunger is formed by via process or dual-damascene technics.
In the process of existing formation thin copper film or conductive plunger, form groove or through hole, then filled conductive material in groove or through hole by etch media layer.But, when characteristic size reaches 32 nanometers and following technique time, when making thin copper film or conductive plunger, for reducing parasitic capacitance, the dielectric material of ultralow dielectric (Ultra low K, ULK) must be used as dielectric layer (described ultralow K is that dielectric constant is less than or equal to 2.5).
More technical schemes about ULK can be the U.S. Patent application of US2011/0143533A1 with reference to publication number.
In the back segment manufacturing process of semiconductor device, in making copper metal line process, adopt the technique of ultra-low K dielectric layer as shown in Figures 1 to 4.
As shown in Figure 1, provide Semiconductor substrate 10, described Semiconductor substrate 10 is formed as structures such as transistor, capacitor, conductive plungers; Form etching barrier layer 20 over the semiconductor substrate 10; Etching barrier layer 20 is formed ultra-low K dielectric layer 30, and described ultra-low K dielectric layer 30 is porous material, and its material is specifically as follows SiOCH, and between the atom of described SiOCH, interval is comparatively sparse; Ultra-low K dielectric layer 30 is formed anti-reflecting layer (BARC) 40; Anti-reflecting layer 40 applies photoresist layer 50; Through exposure imaging technique, photoresist layer 50 defines the pattern of opening.
As shown in Figure 2, with photoresist layer 50 for mask, along the pattern etch ultra-low K dielectric layer 30 of opening to exposing Semiconductor substrate 10, form groove 60.
As shown in Figure 3, photoresist layer 50 and anti-reflecting layer 40 is removed; In ultra-low K dielectric layer 30, form copper metal layer 70 with sputtering process, and described copper metal layer 70 fills full groove.
As shown in Figure 4, adopting chemical mechanical milling method (CMP) planarization copper metal layer 70 to exposing ultra-low K dielectric layer 30, forming metal wiring layer 70a.
When but prior art forms metal line or conductive plunger in ultra-low K dielectric layer, the dielectric constant K of ultra-low K dielectric layer can drift about, thus cause ultra-low K dielectric layer capacitance to change (the capacity ratio low K dielectric layer electric capacity as ultra-low K dielectric layer exceeds 40%), make the stability of semiconductor device and reliability produce serious problems.
Summary of the invention
The problem that the present invention solves is to provide a kind of semiconductor device and manufacture method thereof, and prevent when making metal wiring layer or conductive plunger, the dielectric constant K of ultra-low K dielectric layer drifts about, and causes stability and the integrity problem of semiconductor device.
For solving the problem, the invention provides a kind of semiconductor device, comprising:
Semiconductor substrate;
Be positioned at the etching barrier layer in described Semiconductor substrate and ultra-low K dielectric layer successively, the dielectric constant range of described ultra-low K dielectric layer comprises: 2.2 ~ 2.5, and described ultra-low K dielectric layer has fine and close structure;
Be positioned in described Semiconductor substrate, and successively by described ultra-low K dielectric layer and described etching barrier layer the metal wiring layer that surrounds or conductive plunger.
Alternatively, the material of described ultra-low K dielectric layer comprises: boron nitride.
Alternatively, the thickness range of described ultra-low K dielectric layer comprises:
Alternatively, the dielectric constant range of described etching barrier layer comprises: 4.1 ~ 4.3.
Alternatively, the material of described etching barrier layer comprises: boron nitride.
Alternatively, the thickness range of described etching barrier layer comprises:
Alternatively, comprise between described Semiconductor substrate and described etching barrier layer: adhesive layer.
Alternatively, the material of described adhesive layer comprises the nitride of Silicon-rich.
Alternatively, the thickness range of described adhesive layer comprises
Alternatively, comprise between described adhesive layer and described etching barrier layer: adsorption layer.
Alternatively, the material of described adsorption layer comprises silicon.
Alternatively, the thickness range of described adsorption layer comprises
For solving the problem, the invention provides a kind of manufacture method of semiconductor device, comprising step:
Semiconductor substrate is provided;
Form etching barrier layer and ultra-low K dielectric layer successively on the semiconductor substrate, the dielectric constant range of described ultra-low K dielectric layer comprises: 2.2 ~ 2.5, and described ultra-low K dielectric layer has fine and close structure;
Etching described ultra-low K dielectric layer and etching barrier layer successively to exposing described Semiconductor substrate, forming groove;
Fill full metal level in the trench;
Planarization is carried out to described metal level, the upper surface of described metal level and the upper surface flush of ultra-low K dielectric layer.
Alternatively, the manufacture method of described semiconductor device also comprises: before formation groove, described ultra-low K dielectric layer forms insulating barrier, anti-reflecting layer and photoresist layer successively; Patterned process is carried out to described photoresist layer, forms opening figure; With described photoresist layer for mask, etch described anti-reflecting layer and insulating barrier successively to exposing ultra-low K dielectric layer along opening figure;
Remove described photoresist layer and anti-reflecting layer, with described insulating barrier for mask, etching described ultra-low K dielectric layer and etching barrier layer to exposing Semiconductor substrate, forming groove;
When carrying out planarization to described metal level, remove described insulating barrier.
Alternatively, the manufacture method of described semiconductor device also comprises: before the described etching barrier layer of formation, form adhesive layer on the semiconductor substrate.
Alternatively, the manufacture method of described semiconductor device also comprises: formation described adhesive layer after and formation described etching barrier layer before, described adhesive layer forms adsorption layer.
Compared with prior art, the present invention has the following advantages:
1) the present invention is when forming semiconductor device, adopt the ultra-low K dielectric layer of compact texture, because the structure comparison of ultra-low K dielectric layer is fine and close, instead of porous material, therefore ultra-low K dielectric layer is not easy the impact being subject to the techniques such as CMP, etching or PVD, thus can not impact the dielectric constant of ultra-low K dielectric layer, there is the possibility of drift in the dielectric constant avoiding ultra-low K dielectric layer, finally improves stability and the reliability of semiconductor device.
2) in possibility, can form adhesive layer between Semiconductor substrate and etching barrier layer, described adhesive layer can react with metal level, thus improves the adhesion between Semiconductor substrate and metal level.
3) in possibility, adsorption layer can be formed between Semiconductor substrate and adhesive layer, described adsorption layer can absorb PECVD (Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition) ultraviolet light in technique, thus reduce plasma to the damage of etching barrier layer.
Accompanying drawing explanation
Fig. 1 to Fig. 4 is that prior art forms the schematic diagram comprising the metal line of ultra-low K dielectric layer;
Fig. 5 is the manufacture method embodiment schematic flow sheet of semiconductor device of the present invention;
Fig. 6 to Figure 15 is the schematic diagram of an embodiment of the manufacture method of semiconductor device of the present invention.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Set forth a lot of detail in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here to implement, therefore the present invention is not by the restriction of following public specific embodiment.
Technique below deep-submicron, when making metal wiring layer or conductive plunger in last part technology, adopt super low-K dielectric material as in dielectric layer process, inventor finds because ultra-low K dielectric layer is porous material (shown in Fig. 1 to Fig. 4), therefore the CMP after formation ultra-low K dielectric layer, wet etching, in dry etching or physical vapour deposition (PVD) (PVD) technique, ultra-low K dielectric layer is all easily damaged, the dielectric constant K of ultra-low K dielectric layer is caused to offset (as: after usual planarization, K value can be offset to 2.8 by 2.5), and then ultra-low K dielectric layer electric capacity can be caused to change (exceeding 40% than low K dielectric layer electric capacity), thus cause the insulation effect of ultra-low K dielectric layer to be deteriorated, the stability of the semiconductor device of follow-up formation and integrity problem.
Inventor is for above-mentioned technical problem, through the analysis to reason, continuous research finds when manufacturing semiconductor device, the ultra-low K dielectric layer of compact texture can be adopted, because the structure comparison of ultra-low K dielectric layer is fine and close, instead of porous material, therefore ultra-low K dielectric layer is not easy the impact being subject to the techniques such as CMP, etching or PVD, thus can not impact the dielectric constant of ultra-low K dielectric layer, effectively prevent the K value drift of ultra-low K dielectric layer and the significantly change of electric capacity, ensure stability and the reliability of semiconductor device.
Fig. 5 is the manufacture method embodiment schematic flow sheet of semiconductor device of the present invention, and as shown in Figure 5, the manufacture method of described semiconductor device comprises:
Step S1, provides Semiconductor substrate;
Step S2, form etching barrier layer and ultra-low K dielectric layer successively on the semiconductor substrate, the dielectric constant range of described ultra-low K dielectric layer comprises: 2.2 ~ 2.5, and described ultra-low K dielectric layer has fine and close structure;
Step S3, etches described ultra-low K dielectric layer and etching barrier layer successively to exposing described Semiconductor substrate, forms groove;
Step S4, fills full metal level in the trench;
Step S5, carries out planarization to described metal level, the upper surface of described metal level and the upper surface flush of ultra-low K dielectric layer.
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Fig. 6 to Figure 15 is an embodiment schematic diagram of the manufacture method of semiconductor device of the present invention.The present embodiment is to form metal wiring layer, but it does not limit the scope of the invention, as: the present embodiment method can also be adopted to form conductive plunger etc.
As shown in Figure 6, Semiconductor substrate 100 is provided.
Described Semiconductor substrate 100 has been formed as structures such as transistor, capacitor, metal wiring layers through FEOL usually.
As shown in Figure 7, described Semiconductor substrate 100 forms adhesive layer 200.
Described adhesive layer 200 can react with the metal level of follow-up formation, thus improves the adhesion between Semiconductor substrate 100 and metal level.
In the present embodiment, the material of metal level is copper, and the material of described adhesive layer 200 can comprise the nitride of Silicon-rich, and it can be formed by PECVD method, and other technique existing also can be adopted to be formed.Particularly, SiH can be adopted
4and NH
3reaction generates.The nitride of described Silicon-rich refers to the higher silicon nitride of silicone content (Si rich SiN).
Preferably, in order to stop the damage that plasma may cause semiconductor device, the radio-frequency power when forming adhesive layer 200 can be less than or equal to 50W, as: 50W, 40W, 25W or 10W.
The thickness range of described adhesive layer 200 can comprise
as:
or
As shown in Figure 8, described adhesive layer 200 forms adsorption layer 300.
Described adsorption layer 300 can adsorb the ultraviolet light in pecvd process, thus reduces plasma to the damage of semiconductor device.
The material of described adsorption layer 300 can comprise silicon, and its thickness range can comprise
as:
or
described adsorption layer 300 can adopt any one method of prior art to be formed, and it does not limit the scope of the invention.
Particularly, the present embodiment adopts PECVD method to form adhesive layer 200 and adsorption layer 300.As employing SiH
4and NH
3after reaction generates adhesive layer 200, stop supply NH
3, continue to use SiH
4generate adsorption layer 300, thus method is simple, is easy to control.
As shown in Figure 9, described adsorption layer 300 forms etching barrier layer 400.
Described etching barrier layer 400 as etching stop layer, to prevent in etching process etching gas or liquid insults to rete below.
The dielectric constant of etching barrier layer 400 described in the present embodiment can be positioned at 4.1 ~ 4.3, as: 4.1,4.2 or 4.3.
Particularly, the material of described etching barrier layer 400 can be boron nitride, and its thickness can comprise
as:
or
PECVD method can be adopted in the present embodiment to form etching barrier layer 400, and reacting gas can comprise boron-containing compound (as: BCl
3, BBr
3, B
2h
6or BF
3in one or more) and nitrogen-containing compound (as: NH
3or N
2h
4one or more).
Particularly, the temperature range forming etching barrier layer 400 can comprise: 300 DEG C ~ 400 DEG C, air pressure range can comprise: 0.1 holder ~ 0.7 holder, the gas flow scope of boron-containing compound can comprise: 100sccm ~ 1000sccm, the gas flow scope of nitrogen-containing compound can comprise: 100sccm ~ 1000sccm, and radio frequency power range can comprise: 50W ~ 1000W.
As shown in Figure 10, described etching barrier layer 400 forms ultra-low K dielectric layer 500.
The dielectric constant range of described ultra-low K dielectric layer 500 comprises: 2.2 ~ 2.5, and it is less than the dielectric constant of described etching barrier layer 400, as: 2.2,2.3,2.4 or 2.5.
Although the dielectric constant of ultra-low K dielectric layer 500 is very little in the present embodiment, but there is fine and close structure.Particularly, the material of described ultra-low K dielectric layer 500 can be boron nitride.Because boron nitride has network structure, and it has the hole that a small amount of diameter is Nano grade, therefore the structure comparison of boron nitride is fine and close, thus boron nitride is not subject to the impact of the techniques such as CMP, dry etching, wet etching or PVD, finally improve the reliability and stability of semiconductor device, reduce the parasitic capacitance between metal level.Wherein, the thickness range of described ultra-low K dielectric layer 500 can comprise:
as:
or
Although the dielectric constant of ultra-low K dielectric layer 500 and etching barrier layer 400 is different in the present embodiment, its material can be boron nitride, thus adhesiveness between ultra-low K dielectric layer 500 and etching barrier layer 400 is fine.
In the present embodiment, ultra-low K dielectric layer 500 also can adopt pecvd process to be formed, and reacting gas can comprise borine and ammonia.
Particularly, the temperature range forming ultra-low K dielectric layer 500 can comprise: 300 DEG C ~ 400 DEG C, air pressure range can comprise: 0.1 holder ~ 0.7 holder, the gas flow scope of borine can comprise: 100sccm ~ 1000sccm, the gas flow scope of ammonia can comprise: 100sccm ~ 1000sccm, and radio frequency power range can comprise: 200W ~ 1000W.
Finer and close than the structure as the boron nitride of ultra-low K dielectric layer 500 as the boron nitride of etching barrier layer 400 in the present embodiment, namely the content of boron is more, Kong Geng little.Particularly, the present embodiment can adopt pecvd process on adsorption layer 300 successively original position (in situ) deposition form etching barrier layer 400 and ultra-low K dielectric layer 500, after formation dielectric constant is positioned at the etching barrier layer 400 of 4.1 ~ 4.3, the flow reducing boron-containing compound or the flow increasing nitrogen-containing compound can obtain the ultra-low K dielectric layer 500 that dielectric constant is positioned at 2.2 ~ 2.5.
As shown in figure 11, described ultra-low K dielectric layer 500 forms insulating barrier 600, anti-reflecting layer 700 and photoresist layer 800 successively.
Wherein, described insulating barrier 600 can be the oxide layer of one deck densification, as: the silicon dioxide layer prepared for reaction source with TEOS (tetraethoxysilane).
Wherein, the material of described anti-reflecting layer 700 can be titanium nitride, and its effect is mainly: prevent light by reflecting at wafer interface after photoresist, avoids the light reflected can interfere with incident light, makes photoresist energy uniform exposure.
The present invention does not limit the material of photoresist, can be the photoresist of any materials.
As shown in figure 12, patterned process is carried out to described photoresist layer 800, form opening figure, and with described photoresist layer 800 for mask, etch described anti-reflecting layer 700 and insulating barrier 600 successively along opening figure.
As shown in figure 13, removing described photoresist layer 800 and anti-reflecting layer 700, with described insulating barrier 600 for mask, etching described ultra-low K dielectric layer 500, etching barrier layer 400, adsorption layer 300, adhesive layer 200 to exposing Semiconductor substrate 100, form groove.
Wherein, cineration technics can be adopted to remove described photoresist layer 800, adopt wet-etching technology to remove described anti-reflecting layer 700.
Dry etch process can be adopted in the present embodiment to etch described ultra-low K dielectric layer 500, particularly, can Cl be selected
2as etching gas.Described etching gas to the etch rate of ultra-low K dielectric layer 500 much larger than the etch rate of etching gas to insulating barrier 600.
As shown in figure 14, full metal level 900 is filled in the trench.
In the present embodiment, the material of described metal level 800 can be copper.Now, formation metal level 900 before, channel bottom also Applied Physics vapour deposition process form one deck copper seed layer (not shown), make metal level 900 around its growth.
As shown in figure 15, planarization is carried out to described metal level 900, and removes described insulating barrier 600, make the upper surface of metal level 900 and the upper surface flush of ultra-low K dielectric layer 500 after planarization.
Wherein, wet-etching technology can be adopted to remove described insulating barrier 600.
So far, metal wiring layer 900a is formed.
Accordingly, present invention also offers a kind of semiconductor device, comprising:
Semiconductor substrate;
Be positioned at the etching barrier layer in described Semiconductor substrate and ultra-low K dielectric layer successively, the dielectric constant range of described ultra-low K dielectric layer comprises: 2.2 ~ 2.5, described ultra-low K dielectric layer has fine and close structure, and the dielectric constant of described etching barrier layer is greater than the dielectric constant of described ultra-low K dielectric layer;
Be positioned in described Semiconductor substrate, and successively by described ultra-low K dielectric layer and described etching barrier layer the metal wiring layer that surrounds or conductive plunger.
Particularly, the material of described ultra-low K dielectric layer can comprise: boron nitride; The thickness range of described ultra-low K dielectric layer can comprise:
Wherein, the dielectric constant range of described etching barrier layer can comprise: 4.1 ~ 4.3.
Particularly, the material of described etching barrier layer can comprise: boron nitride; The thickness range of described etching barrier layer can comprise:
Wherein, can comprise between described Semiconductor substrate and described etching barrier layer: adhesive layer.
Particularly, the material of described adhesive layer can comprise the nitride of Silicon-rich; The thickness range of described adhesive layer can comprise
Wherein, can comprise between described adhesive layer and described etching barrier layer: adsorption layer.
Particularly, the material of described adsorption layer can comprise silicon; The thickness range of described adsorption layer can comprise
Wherein, the material of described metal wiring layer or conductive plunger can comprise copper.
Although the present invention discloses as above with preferred embodiment, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (7)
1. a manufacture method for semiconductor device, is characterized in that, comprises step:
Semiconductor substrate is provided;
Adopt in-situ deposition method to form etching barrier layer and ultra-low K dielectric layer successively on the semiconductor substrate, reacting gas comprises boron-containing compound and nitrogen-containing compound; The flow forming boron-containing compound during described ultra-low K dielectric layer is less than the flow of boron-containing compound when forming described etching barrier layer, or, the flow forming nitrogen-containing compound during described ultra-low K dielectric layer is greater than the flow of nitrogen-containing compound when forming described etching barrier layer, the dielectric constant range of described ultra-low K dielectric layer comprises: 2.2 ~ 2.5, and described ultra-low K dielectric layer has fine and close structure;
Etching described ultra-low K dielectric layer and etching barrier layer successively to exposing described Semiconductor substrate, forming groove;
Fill full metal level in the trench;
Planarization is carried out to described metal level, the upper surface of described metal level and the upper surface flush of ultra-low K dielectric layer.
2. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, also comprise: before formation groove, described ultra-low K dielectric layer forms insulating barrier, anti-reflecting layer and photoresist layer successively; Patterned process is carried out to described photoresist layer, forms opening figure; With described photoresist layer for mask, etch described anti-reflecting layer and insulating barrier successively to exposing ultra-low K dielectric layer along opening figure;
Remove described photoresist layer and anti-reflecting layer, with described insulating barrier for mask, etching described ultra-low K dielectric layer and etching barrier layer to exposing Semiconductor substrate, forming groove;
When carrying out planarization to described metal level, remove described insulating barrier.
3. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, also comprise: before the described etching barrier layer of formation, form adhesive layer on the semiconductor substrate.
4. the manufacture method of semiconductor device as claimed in claim 3, is characterized in that, also comprise: after the described adhesive layer of formation, before the described etching barrier layer of formation, described adhesive layer forms adsorption layer.
5. the manufacture method of semiconductor device as claimed in claim 1, it is characterized in that, the material of described ultra-low K dielectric layer comprises: boron nitride.
6. the manufacture method of semiconductor device as claimed in claim 5, it is characterized in that, the material of described etching barrier layer comprises: boron nitride.
7. the manufacture method of semiconductor device as claimed in claim 1, it is characterized in that, the gas flow scope forming boron-containing compound during described etching barrier layer comprises: 100sccm ~ 1000sccm, and the gas flow scope of nitrogen-containing compound comprises: 100sccm ~ 1000sccm.
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| CN103594525B (en) * | 2013-11-08 | 2016-03-09 | 溧阳市江大技术转移中心有限公司 | A kind of semiconductor capacitor |
| CN104167353A (en) * | 2014-08-08 | 2014-11-26 | 武汉新芯集成电路制造有限公司 | Method for processing surface of bonding substrate |
| CN112992708A (en) * | 2019-12-16 | 2021-06-18 | 中微半导体设备(上海)股份有限公司 | Manufacturing method of semiconductor device |
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| CN1433062A (en) * | 2002-01-10 | 2003-07-30 | 联华电子股份有限公司 | Method of forming opening in low dielectric constant material |
| CN1645608A (en) * | 2004-01-16 | 2005-07-27 | 国际商业机器公司 | Low k and ultra low k SiCOH dielectric films and methods to form the same |
| CN101449363A (en) * | 2006-03-20 | 2009-06-03 | 应用材料公司 | Organic barc etch process capable of use in the formation of low K dual damascene integrated circuits |
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| KR100745986B1 (en) * | 2004-12-08 | 2007-08-06 | 삼성전자주식회사 | Fabrication method of dual damascene interconnections of microelectronics device using filler having porogen |
| US8993435B2 (en) * | 2010-03-15 | 2015-03-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Low-k Cu barriers in damascene interconnect structures |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1433062A (en) * | 2002-01-10 | 2003-07-30 | 联华电子股份有限公司 | Method of forming opening in low dielectric constant material |
| CN1645608A (en) * | 2004-01-16 | 2005-07-27 | 国际商业机器公司 | Low k and ultra low k SiCOH dielectric films and methods to form the same |
| CN101449363A (en) * | 2006-03-20 | 2009-06-03 | 应用材料公司 | Organic barc etch process capable of use in the formation of low K dual damascene integrated circuits |
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