CN106128957A - 一种GaAs纳米线的制作方法 - Google Patents

一种GaAs纳米线的制作方法 Download PDF

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CN106128957A
CN106128957A CN201610615915.2A CN201610615915A CN106128957A CN 106128957 A CN106128957 A CN 106128957A CN 201610615915 A CN201610615915 A CN 201610615915A CN 106128957 A CN106128957 A CN 106128957A
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nano wire
hydrochloric acid
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gaas
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CN106128957B (zh
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王勇
王瑛
丁超
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Guangdong University of Technology
Dongguan South China Design and Innovation Institute
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Guangdong University of Technology
Dongguan South China Design and Innovation Institute
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604Chemical etching
    • H01L21/30612Etching of AIIIBV compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66446Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66469Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with one- or zero-dimensional channel, e.g. quantum wire field-effect transistors, in-plane gate transistors [IPG], single electron transistors [SET], Coulomb blockade transistors, striped channel transistors

Abstract

本发明公布了一种GaAs纳米线制作方法,该制作方法步骤如下:准备一砷化镓衬底、一InGaP缓冲层和一砷化镓沟道层的材料结构;在砷化镓沟道层中刻蚀出50纳米宽的脊状图形;然后在臭氧去胶机中进行20分钟的处理;采用浓盐酸清洗1分钟,稀盐酸清洗2分钟;在臭氧去胶机中进行20分钟的臭氧处理;采用浓盐酸清洗1分钟,稀盐酸清洗2分钟;在臭氧去胶机中进行20分钟的臭氧处理,再采用稀释的磷酸进行清洗的方法处理5‑10次;最后得到10‑20纳米宽的GaAs纳米线。

Description

一种GaAs纳米线的制作方法
技术领域
本发明涉及半导体集成电路制造技术领域,具体涉及一种砷化镓纳米线的制作方法,应用于高性能III-V族半导体CMOS技术。
背景技术
Ⅲ-Ⅴ化合物半导体材料相对硅材料而言,具有高载流子迁移率、大的禁带宽度等优点,而且在热学、光学和电磁学等方面都有很好的特性。近年来,随着III-V族MOSFET器件研究的不断推进,III-V族MOS界面特性取得了巨大进展,界面态密度已经降低到1-3×1011eV·cm-2;III-V族MOS器件的结构已经从平面器件逐步推进到纳米线MOS器件。最新研究报道表明:硅基半导体器件在10纳米技术节点以后的器件结构可能是FinFET器件或者纳米线器件结构。然而III-V族半导体由于其各晶向的腐蚀异性,造成了制作纳米线的困难。因此,需要一种新的途径在III-V族半导体材料上实现纳米线结构,以满足高性能III-V族半导体纳米线MOS器件技术的要求。
发明内容
(一)要解决的技术问题
本发明的主要目的是提供一种砷化镓纳米线的制作方法,以实现以砷化镓纳米为沟道的CMOS器件,提高器件的栅控性能和良好的沟道表面特性,降低表面粗糙度散射,提高MOS器件的迁移率特性,以满足高性能III-V族半导体CMOS技术的要求。
(二)技术方案
为达到上述目的,本发明提供了一种砷化镓纳米线的制作方法。其制作步骤依次是:
(1)准备一砷化镓衬底上外延有50纳米厚InGaP缓冲层和50纳米厚的砷化镓沟道层的晶圆片;
(2)在砷化镓沟道层中刻蚀出50纳米宽的脊状图形;
(3)在臭氧去胶机中进行20分钟的处理;
(4)采用浓盐酸清洗1分钟,稀盐酸清洗2分钟,腐蚀去掉GaAs纳米线下的InGaP层;
(5)在臭氧去胶机中进行20分钟的臭氧处理;
(6)采用浓盐酸清洗1分钟,稀盐酸清洗2分钟;
(7)在臭氧去胶机中进行20分钟的臭氧处理,再采用稀释的磷酸进行清洗的方法处理5-10次,采用该种方法对GaAs纳米线进行细化;
在上述方案中,臭氧去胶机中,利用臭氧氧化砷化镓材料时,要对去胶机进行预开机,开机5分钟以后,放入样品,以保证氧化速率的一致性。
在上述方案中,稀释的盐酸溶液的配比为盐酸:水=1:10。
在上述方案中,稀释的磷酸溶液的配比为磷酸:水=1:10。
在上述方案中,砷化镓纳米线的宽度从50纳米依据臭氧处理和稀磷酸腐蚀这一循环次数,该种腐蚀方法为数字腐蚀,每次腐蚀的砷化镓厚度为2纳米,腐蚀10次,砷化镓纳米线的宽度可以降低到10纳米左右。
(三)有益效果
从上述技术方案可以看出,本发明具有以下有益效果:本发明提供的一种GaAs纳米线结构的制作方法,利用InGaP材料作为缓冲层和底部牺牲层,采用ICP刻蚀和盐酸腐蚀的方法在半导体基片上初步实现较宽的砷化镓纳米线结构,然后再利用臭氧氧化的方法氧化砷化镓纳米线,用稀释盐酸溶液和稀释磷酸溶液腐蚀被氧化的砷化镓表层,采用这种缓慢的数字腐蚀方法腐蚀细化砷化镓纳米线。以制作满足高性能III-V族半导体CMOS技术对砷化镓纳米线在形状、宽度、表面粗糙度和直径等方面的要求。
附图说明
图1是本发明提供的制作GaAs纳米线的工艺流程示意图;
具体实施方式
为使本发明的目的、技术方案和优点更加清楚明白,以下结合具体实施例,并参照附图,对本发明进一步详细说明。
本实施例提供了一种砷化镓纳米线结构的制作方法。其制作步骤依次是:
(1)准备一砷化镓衬底上外延有50纳米厚In0.49Ga0.51P缓冲层和50纳米厚的砷化镓沟道层的晶圆片,其中InGaP与GaAs的掺杂类型都是N型,掺杂杂质为硅,掺杂浓度为4×1017cm-3
(2)在准备好的生长有InGaP和砷化镓的晶圆片上刻蚀出50纳米宽的脊状图形,刻蚀深度为100纳米,采用的掩膜为SiO2掩膜,刻蚀方法为ICP干法刻蚀,刻蚀气体为Cl2/BCl3,刻蚀完成后,采用HF酸溶液腐蚀掉SiO2掩膜;
(3)将刻蚀完成的晶圆片放入臭氧去胶机中进行20分钟的处理,在处理前,将去胶机预开机20分钟;
(4)采用浓盐酸清洗1分钟,稀盐酸清洗2分钟,腐蚀去掉GaAs纳米线下的InGaP层;
(5)在臭氧去胶机中进行20分钟的臭氧处理,在处理前去胶机要预开机20分钟;
(6)采用浓盐酸清洗1分钟,稀盐酸清洗2分钟,在两次处理之间要将晶圆片放置在去离子水中至少3分钟;
(7)在臭氧去胶机中进行20分钟的臭氧处理,再采用稀释的磷酸进行清洗的方法处理5-10次,采用该种方法对GaAs纳米线进行细化。
在本实施例中,臭氧去胶机中,利用臭氧氧化砷化镓材料时,为了保证整个过程比较清洁,应确保在整个过程中没有其他工艺对该工艺进行打断。
在本实施例中,稀释的盐酸溶液的配比为盐酸:水=1:10。
在本实施例中,稀释的磷酸溶液的配比为磷酸:水=1:10。
在本实施例中,砷化镓纳米线的宽度从50纳米依据臭氧处理和稀磷酸腐蚀这一循环次数,该种腐蚀方法为数字腐蚀,每次腐蚀的砷化镓厚度为2纳米,腐蚀10次,砷化镓纳米线的宽度可以降低到10纳米左右。
在本实施例中,为保证纳米线的良率,所有工序没有采用超声和氮气吹干,采用甩干的方式,将晶圆片甩干即可。
以上所述的具体实施例,对本发明的目的、技术方案和有益效果进行了进一步详细说明,所应理解的是,以上所述仅为本发明的具体实施例而已,并不用于限制本发明,凡在本发明的精神和原则之内,所做的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。

Claims (4)

1.一种GaAs纳米线制作方法,其步骤如下:
(1)准备一砷化镓衬底上外延有50纳米厚InGaP缓冲层和50纳米厚的砷化镓沟道层的晶圆片;
(2)在砷化镓沟道层中刻蚀出50纳米宽的脊状图形;
(3)在臭氧去胶机中进行20分钟的处理;
(4)采用浓盐酸清洗1分钟,稀盐酸清洗2分钟,腐蚀去掉GaAs纳米线下的InGaP层;
(5)在臭氧去胶机中进行20分钟的臭氧处理;
(6)采用浓盐酸清洗1分钟,稀盐酸清洗2分钟;
(7)在臭氧去胶机中进行20分钟的臭氧处理,再采用稀释的磷酸进行清洗的方法处理5-10次,采用该种方法对GaAs纳米线进行细化。
2.根据权利要求1所述的一种GaAs纳米线制作方法,其特征在于所述臭氧处理过程中,对GaAs表面的氧化速率为0.1纳米/分钟。
3.根据权利要求1所述的一种GaAs纳米线制作方法,其特征在于所述稀盐酸溶液的配比为盐酸:水=1:10。
4.根据权利要求1所述的一种GaAs纳米线制作方法,其特征在于所述稀磷酸的配比为磷酸:水=1:10。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001023951A (ja) * 1999-07-12 2001-01-26 Nec Corp 半導体装置の製造方法
CN102017064A (zh) * 2008-03-27 2011-04-13 康宁股份有限公司 半导体掩埋型光栅制造方法
US20150344825A1 (en) * 2012-12-05 2015-12-03 Entegris, Inc. Compositions for cleaning iii-v semiconductor materials and methods of using same
WO2015190637A1 (ko) * 2014-06-11 2015-12-17 한국표준과학연구원 대면적의 수직 정렬된 갈륨비소 반도체 나노선 어레이 제작 공정

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001023951A (ja) * 1999-07-12 2001-01-26 Nec Corp 半導体装置の製造方法
CN102017064A (zh) * 2008-03-27 2011-04-13 康宁股份有限公司 半导体掩埋型光栅制造方法
US20150344825A1 (en) * 2012-12-05 2015-12-03 Entegris, Inc. Compositions for cleaning iii-v semiconductor materials and methods of using same
WO2015190637A1 (ko) * 2014-06-11 2015-12-17 한국표준과학연구원 대면적의 수직 정렬된 갈륨비소 반도체 나노선 어레이 제작 공정

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