CN106128949A - A kind of eliminate the method for wafer surface defects in three dimensional NAND forming process - Google Patents
A kind of eliminate the method for wafer surface defects in three dimensional NAND forming process Download PDFInfo
- Publication number
- CN106128949A CN106128949A CN201610515918.9A CN201610515918A CN106128949A CN 106128949 A CN106128949 A CN 106128949A CN 201610515918 A CN201610515918 A CN 201610515918A CN 106128949 A CN106128949 A CN 106128949A
- Authority
- CN
- China
- Prior art keywords
- film
- oxide layer
- forming process
- wafer surface
- surface defects
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 60
- 230000007547 defect Effects 0.000 title claims abstract description 31
- 230000008569 process Effects 0.000 title claims abstract description 31
- 230000008021 deposition Effects 0.000 claims abstract description 23
- 238000003701 mechanical milling Methods 0.000 claims abstract description 7
- 239000000126 substance Substances 0.000 claims abstract description 7
- 239000010408 film Substances 0.000 claims description 67
- 238000000151 deposition Methods 0.000 claims description 26
- 239000002131 composite material Substances 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 14
- 230000008030 elimination Effects 0.000 claims description 11
- 238000003379 elimination reaction Methods 0.000 claims description 11
- 150000004767 nitrides Chemical class 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 6
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 239000010409 thin film Substances 0.000 claims 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
- 229910052760 oxygen Inorganic materials 0.000 claims 1
- 239000001301 oxygen Substances 0.000 claims 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract description 40
- 229910052757 nitrogen Inorganic materials 0.000 abstract description 20
- 230000003647 oxidation Effects 0.000 abstract description 18
- 238000007254 oxidation reaction Methods 0.000 abstract description 18
- 238000005530 etching Methods 0.000 abstract description 11
- 239000008187 granular material Substances 0.000 abstract description 7
- 238000003860 storage Methods 0.000 abstract description 2
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 238000001259 photo etching Methods 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 238000010891 electric arc Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000008280 blood Substances 0.000 description 2
- 210000004369 blood Anatomy 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000001066 destructive effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 238000000752 ionisation method Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 238000001179 sorption measurement Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- SQVRNKJHWKZAKO-PFQGKNLYSA-N N-acetyl-beta-neuraminic acid Chemical compound CC(=O)N[C@@H]1[C@@H](O)C[C@@](O)(C(O)=O)O[C@H]1[C@H](O)[C@H](O)CO SQVRNKJHWKZAKO-PFQGKNLYSA-N 0.000 description 1
- 238000005299 abrasion Methods 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 239000013039 cover film Substances 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 230000003862 health status Effects 0.000 description 1
- 238000002372 labelling Methods 0.000 description 1
- 238000006396 nitration reaction Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The present invention relates to three-dimensional storage field, particularly relate to a kind of eliminate the method for wafer surface defects in three dimensional NAND forming process, after having deposited high-density plasma oxide layer on multilamellar nitrogen oxidation film, described high-density plasma oxide layer is planarized first with chemical mechanical milling tech, deposition mask layer on high-density plasma oxide layer after described planarization again, so can grind away the granule projection on high-density plasma oxide layer surface, thus avoid causing defect during deposition mask layer, ensure that being smoothed out of further channel hole etching technics.
Description
Technical field
The present invention relates to three-dimensional storage field, particularly relate to crystal column surface in a kind of elimination three dimensional NAND forming process and lack
The method fallen into.
Background technology
Existing 3D NAND(three-dimensional flash memory memorizer) in manufacturing process, owing to high aspect ratio access opening etches requirement, logical
Access opening etching is carried out again after often depositing one layer of thicker hard mask layer in nitrogen oxide layer.Such as it is stacked with 32 layers of nitrogen oxide layer
The 3D NAND of (about 1.92 μm), the hard mask layer of deposition about 1.17 μ m-thick is to ensure the high aspect ratio requirement of access opening etching.
But in hard mask layer deposition process, it has been found that in high density ionization process before, big of surface
The protruding easily adsorption charge of grain produces point discharge phenomenon, thus the highdensity electric arc of guiding high intensity is adsorbed on wafer,
Crystal column surface produces destructive defect (" Arcing " problem), and the most this defect is formed, follow-up access opening etching
Technique just cannot be smoothed out, and affects device effect, causes wafer to be discarded.
Summary of the invention
In view of the above problems, the present invention provides a kind of method eliminating wafer surface defects, to ensure that access opening etches work
Being smoothed out of skill, it is to avoid wafer loss, improves device effect.
The present invention solves the technical scheme that above-mentioned technical problem used:
There is provided a kind of and eliminate the method for wafer surface defects in three dimensional NAND forming process, it is characterised in that including:
Semi-conductive substrate is provided；
Composite film is prepared on described Semiconductor substrate；
After the upper surface of described composite film prepares intermediate oxide layer, remove the projection on described intermediate oxide layer surface；
Deposition mask layer covers the surface of described intermediate oxide layer；
The memory heap stack architecture in described NAND is prepared based on the described composite film being coated with mask layer and intermediate oxide layer.
Preferably, described Semiconductor substrate is a silicon substrate.
Preferably, described composite film includes nitride multilayer film and multilamellar oxide-film.
Preferably, described nitride multilayer film and multilamellar oxide-film are alternately stacked the described composite film of formation.
Preferably, contact with described Semiconductor substrate one layer of described composite film is nitride film；Described composite film with
One layer of the contact of described intermediate oxide layer is oxide-film.
Preferably, described intermediate oxide layer is high-density plasma oxide layer.
Preferably, use chemical vapor deposition method formed described composite film, described intermediate oxide layer and described in cover
Film layer.
Preferably, flatening process is used to remove the projection on described intermediate oxide layer surface.
Preferably, chemical mechanical milling tech is used to remove the projection on described intermediate oxide layer surface.
Preferably, the material of described mask layer includes amorphous carbon.
Technique scheme has the advantage that or beneficial effect: the present invention is by having deposited on multilamellar nitrogen oxidation film
After high-density plasma oxide layer, planarize described high-density plasma oxide layer first with chemical mechanical milling tech,
Deposition mask layer on high-density plasma oxide layer after described planarization again, so can grind away high density etc. from
The granule projection on daughter oxide layer surface, thus avoid causing wafer surface defects during deposition mask layer, it is ensured that further channel
Being smoothed out of hole etching technics, and then protect whole 3D NAND device.
Accompanying drawing explanation
By the detailed description non-limiting example made with reference to the following drawings of reading, the present invention and feature thereof, outward
Shape and advantage will become more apparent.The part that labelling instruction identical in whole accompanying drawings is identical.Not can according to than
Example draws accompanying drawing, it is preferred that emphasis is illustrate the purport of the present invention.
Fig. 1 is the method flow diagram that the present invention eliminates wafer surface defects；
Fig. 2 ~ Fig. 6 is the structure chart of each step in the embodiment of the present invention.
Detailed description of the invention
The method of elimination wafer surface defects disclosed by the invention, applies to the forming process of 3D NAND, its concrete steps
As shown in Figure 1: after having deposited high-density plasma oxide layer on multilamellar nitrogen oxidation film, grind first with chemical machinery
Grinding process planarization high-density plasma oxide layer, protruding to eliminate the granule on this high-density plasma oxide layer surface；
Deposition mask layer on high-density plasma oxide layer the most after planarization, by so first grinding away high-density plasma
The granule projection on body oxide layer surface, the mode of redeposited mask layer, it is to avoid cause defect during deposition mask layer, it is ensured that follow-up
Being smoothed out of access opening etching technics.
The method that the present invention eliminates wafer surface defects is elaborated below in conjunction with specific embodiment and accompanying drawing.
With reference to Fig. 2 and Fig. 3, first provide a substrate 1, on substrate 1 formation of deposits multilamellar nitrogen oxidation film (N-O stack)
2.This multilamellar nitrogen oxidation film 2 actually nitride multilayer film (SiN) and multilamellar oxide-film (SiO2) it is alternately stacked formation.Traditional
Two dimensional memory has only to deposit one layer of nitration case, because the present invention eliminates the approach application of wafer surface defects in 3D
NAND(three-dimensional flash memory memorizer), deposition multilamellar nitrogen oxidation film 2 is to form stereochemical structure the most on substrate 1.Wherein multilamellar nitrogen
Depending on the number of plies of oxide-film is according to concrete process requirements, the number of plies of the nitrogen oxidation film of deposition is the most, and its thickness is the thickest, end form
The memory space of the 3D NAND become is the biggest.Such as deposition 16 layers, its thickness is about 0.96 μm；Depositing 32 layers, its thickness is about
1.92μm；Depositing 64 layers, its thickness is about 3.8 μm；Depositing 128 layers, its thickness is about 7.7 μm.Deposit multilamellar nitrogen oxidation film 2
Afterwards, a floor height density plasma oxide-film (HDP OX) 3 is deposited on its surface.According to process requirements, this deposition highly dense
The thickness of degree plasma oxide film (HDP OX) 3 is the thickest.
Before deposition multilamellar nitrogen oxidation film 2, in actual production, technique before may be formed various short grained scarce
Falling into, after the thickest multilamellar nitrogen oxidation film 2 deposition gets on, little grain defect before will be zoomed into multilamellar nitrogen by jack-up
The bulky grain on oxide-film 2 surface protruding (bulky grain that mark 22 is multilamellar nitrogen oxidation film 2 surface in such as Fig. 2 is protruding)；Real
It is also possible to because during deposition multilamellar nitrogen oxidation film 2, board or reaction cavity may drop little during border produces
Granule, and then covered by follow-up multilamellar nitrogen oxidation film 2 deposition and amplify, this and board or the health status of reaction cavity
Having relation, some parts of the inside have used long it is possible that various abrasion, and byproduct of reaction accumulates in gas piping
In or cavity around.Because of various reasons, after having deposited multilamellar nitrogen oxidation film 2, it is easy to form bulky grain on its surface convex
Play 22.
The technique being conventionally formed 3D NANA i.e. continues deposition high density after having stacked multilamellar nitrogen oxidation film 2 on its surface
Plasma oxide film 3 and mask layer.With reference to Fig. 6, because it is protruding to there is bulky grain, deposit high-density plasma oxide-film
When 3, in high density ionization process, bulky grain protruding easily adsorption charge generation point discharge phenomenon, thus guiding high intensity
Highdensity electric arc is adsorbed on wafer, and arc discharge produces destructive defect (Arcing defect) to crystal column surface.And
This defect is likely to be corrupted in beneath multilamellar nitrogen oxidation film 2 even up to substrate 1 always, badly damaged whole 3D
NAND device.
Therefore, the present invention is after having deposited high-density plasma oxide-film (HDP OX) 3, as shown in Figure 4, and employingization
Learn mechanical milling tech (CMP) planarize this high-density plasma oxide-film 3 so that it is the granule projection on surface be milled away and
Leave smooth surface 31.And owing to the thickness of the high-density plasma oxide-film (HDP OX) 3 of deposition is thicker, pass through
HDP OX can also be ground to suitable thickness by CMP, with follow-up processing step.In CMP by high density
After the bulky grain projection on plasma oxide film (HDP OX) 3 surfaces is ground to the surface 31 of planarization, as it is shown in figure 5, again
Depositing one layer of mask layer 4 and cover on the surface 31 of planarization, so mask layer 4 surface of deposition smooths, and defect will not occur,
Protect 3D NAND device.
As a preferred embodiment, the mask layer 4 herein deposited is a kind of a-C(amorphous Carbon, without fixed
Shape carbon) film layer, this a-C film layer light to photoetching process (the follow-up 3D of preparation NAND needs photoetching process to carry out access opening etching)
Line absorption is very capable, with the silicon oxynitride film of specific materials with the use of to reduce the reflectance of light.This a-C film layer is excellent
It is selected in the crucial photoetching process that live width is less use (below such as 90nm technique), meets the present embodiment and prepare 3D NAND's
Process requirements.Meanwhile, this a-C film layer or the hard mask blocks layer of subsequent etching processes (i.e. mask layer 4), because follow-up preparation
3D NAND needs to etch deep hole, so needing thicker hard mask blocks layer to improve etch process level.
Further, the present embodiment preferably employs Kodiak film as amorphous carbon film layer (i.e. mask layer 4), Kodiak
Film is APF(Advanced Pattern Film) one, the anti-reflecting layer preferably as photoetching process improves photoetching work
Skill.
As a preferred embodiment, the present embodiment uses chemical mechanical milling tech (CMP) make high density etc. from
Daughter oxide-film (HDP OX) 3 surface planarisation, in practice, it is also possible to use other process meanses to carry out planarization behaviour
Make.
After having deposited mask layer 4, more beneath multilamellar nitrogen oxidation film 2 is carried out access opening etching, and leading in etching
Road inner hole deposition amasss dielectric layer, and to continue to make 3D NAND, because these steps are similar with existing technique, the present invention is the most superfluous at this
State.
In sum, a kind of of present invention offer eliminates the method for wafer surface defects in three dimensional NAND forming process, logical
Cross after having deposited high-density plasma oxide layer on multilamellar nitrogen oxidation film, planarize first with chemical mechanical milling tech
Deposition mask on described high-density plasma oxide layer, then the high-density plasma oxide layer after described planarization
Layer, so can grind away the granule projection on high-density plasma oxide layer surface, thus avoid causing during deposition mask layer
Defect, it is ensured that being smoothed out of further channel hole etching technics, thus protect whole 3D NAND device.
It should be appreciated by those skilled in the art that those skilled in the art are combining prior art and above-described embodiment is permissible
Realize described change case, do not repeat at this.Such change case has no effect on the flesh and blood of the present invention, the most superfluous at this
State.
Above presently preferred embodiments of the present invention is described.It is to be appreciated that the invention is not limited in above-mentioned
Particular implementation, the equipment and the structure that do not describe in detail the most to the greatest extent are construed as giving reality with the common mode in this area
Execute；Any those of ordinary skill in the art, without departing under technical solution of the present invention ambit, may utilize the disclosure above
Method and technology contents technical solution of the present invention is made many possible variations and modification, or be revised as equivalent variations etc.
Effect embodiment, this has no effect on the flesh and blood of the present invention.Therefore, every content without departing from technical solution of the present invention, foundation
The technical spirit of the present invention, to any simple modification made for any of the above embodiments, equivalent variations and modification, all still falls within the present invention
In the range of technical scheme protection.
Claims (10)
1. one kind eliminates the method for wafer surface defects in three dimensional NAND forming process, it is characterised in that including:
Semi-conductive substrate is provided；
Composite film is prepared on described Semiconductor substrate；
After the upper surface of described composite film prepares intermediate oxide layer, remove the projection on described intermediate oxide layer surface；
Deposition mask layer covers the surface of described intermediate oxide layer；
The memory heap stack architecture in described NAND is prepared based on the described composite film being coated with mask layer and intermediate oxide layer.
2. the method for wafer surface defects in elimination three dimensional NAND forming process as claimed in claim 1, it is characterised in that institute
Stating Semiconductor substrate is a silicon substrate.
3. the method for wafer surface defects in elimination three dimensional NAND forming process as claimed in claim 1, it is characterised in that institute
State composite film and include nitride multilayer film and multilamellar oxide-film.
4. the method for wafer surface defects in elimination three dimensional NAND forming process as claimed in claim 3, it is characterised in that institute
State nitride multilayer film and multilamellar oxide-film is alternately stacked the described composite film of formation successively.
5. the method for wafer surface defects in elimination three dimensional NAND forming process as claimed in claim 4, it is characterised in that institute
Stating the thin film that composite film contacts with described Semiconductor substrate is described nitride film；Described composite film and described middle oxygen
The thin film changing layer contact is described oxide-film.
6. the method for wafer surface defects in elimination three dimensional NAND forming process as claimed in claim 1, it is characterised in that institute
Stating intermediate oxide layer is high-density plasma oxide layer.
7. the method for wafer surface defects in elimination three dimensional NAND forming process as claimed in claim 1, it is characterised in that adopt
Described composite film, described intermediate oxide layer and described mask layer is formed by chemical vapor deposition method.
8. the method for wafer surface defects in elimination three dimensional NAND forming process as claimed in claim 1, it is characterised in that adopt
The projection on described intermediate oxide layer surface is removed with flatening process.
9. the method for wafer surface defects in elimination three dimensional NAND forming process as claimed in claim 8, it is characterised in that institute
Stating flatening process is chemical mechanical milling tech.
10. the method for wafer surface defects in elimination three dimensional NAND forming process as claimed in claim 1, it is characterised in that
The material of described mask layer includes amorphous carbon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610515918.9A CN106128949A (en) | 2016-07-04 | 2016-07-04 | A kind of eliminate the method for wafer surface defects in three dimensional NAND forming process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610515918.9A CN106128949A (en) | 2016-07-04 | 2016-07-04 | A kind of eliminate the method for wafer surface defects in three dimensional NAND forming process |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106128949A true CN106128949A (en) | 2016-11-16 |
Family
ID=57469197
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610515918.9A Pending CN106128949A (en) | 2016-07-04 | 2016-07-04 | A kind of eliminate the method for wafer surface defects in three dimensional NAND forming process |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106128949A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107993922A (en) * | 2017-11-30 | 2018-05-04 | 上海华力微电子有限公司 | Avoiding control gate from forming middle etching and do over again causes the method for amorphous carbon film peeling |
| CN110514461A (en) * | 2019-08-29 | 2019-11-29 | 上海华力微电子有限公司 | A kind of work-table of chemicomechanical grinding mill defect inspection method |
| CN111261513A (en) * | 2020-02-03 | 2020-06-09 | 长江存储科技有限责任公司 | Semiconductor structure and preparation method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20090042462A (en) * | 2007-10-26 | 2009-04-30 | 주식회사 하이닉스반도체 | Method for planarization inter dielectric layer in semicondutor device |
| CN101714525A (en) * | 2008-09-29 | 2010-05-26 | 株式会社瑞萨科技 | Semiconductor integrated circuit device and a method for manufacturing a semiconductor integrated circuit device |
| US8741394B2 (en) * | 2010-03-25 | 2014-06-03 | Novellus Systems, Inc. | In-situ deposition of film stacks |
-
2016
- 2016-07-04 CN CN201610515918.9A patent/CN106128949A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20090042462A (en) * | 2007-10-26 | 2009-04-30 | 주식회사 하이닉스반도체 | Method for planarization inter dielectric layer in semicondutor device |
| CN101714525A (en) * | 2008-09-29 | 2010-05-26 | 株式会社瑞萨科技 | Semiconductor integrated circuit device and a method for manufacturing a semiconductor integrated circuit device |
| US8741394B2 (en) * | 2010-03-25 | 2014-06-03 | Novellus Systems, Inc. | In-situ deposition of film stacks |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107993922A (en) * | 2017-11-30 | 2018-05-04 | 上海华力微电子有限公司 | Avoiding control gate from forming middle etching and do over again causes the method for amorphous carbon film peeling |
| CN107993922B (en) * | 2017-11-30 | 2020-12-01 | 上海华力微电子有限公司 | Method for preventing amorphous carbon film from peeling off caused by etching rework in control gate formation |
| CN110514461A (en) * | 2019-08-29 | 2019-11-29 | 上海华力微电子有限公司 | A kind of work-table of chemicomechanical grinding mill defect inspection method |
| CN111261513A (en) * | 2020-02-03 | 2020-06-09 | 长江存储科技有限责任公司 | Semiconductor structure and preparation method thereof |
| CN111261513B (en) * | 2020-02-03 | 2021-07-06 | 长江存储科技有限责任公司 | Semiconductor structure and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10276381B2 (en) | Semiconductor methods and devices | |
| TWI619144B (en) | Image reversal with ahm gap fill for multiple patterning | |
| JP5356516B2 (en) | Concave and convex pattern forming method | |
| TWI302635B (en) | Partially formed integrated circuit and method of integrated circuit fabrication and forming an integrated circuit | |
| CN108206131B (en) | Semiconductor structure and method for forming semiconductor structure | |
| CN106128949A (en) | A kind of eliminate the method for wafer surface defects in three dimensional NAND forming process | |
| CN108831886A (en) | Three-dimensional storage | |
| CN101459218B (en) | Annular semiconductor device and producing method thereof | |
| CN107564916B (en) | A kind of flattening method of 3D nand memory part | |
| US11877519B2 (en) | Semiconductor device manufacturing method | |
| CN109065547A (en) | The production method of three-dimensional storage | |
| CN109148258A (en) | The method for forming oxide layer | |
| CN107833892B (en) | A kind of oxide fill method of top layer selection grid tangent line | |
| TW201943109A (en) | Method for etching a magnetic tunneling junction structure | |
| CN106409769A (en) | Method for forming storage stack with trapezoidal structures | |
| TW201515093A (en) | Dry etching method for metallization pattern profiling | |
| CN107731834A (en) | A kind of core space layer insulation oxide layer CMP method for 3D NAND | |
| JP2009016446A (en) | Semiconductor device manufacturing method and storage medium | |
| US20150037978A1 (en) | Hard mask removal method | |
| CN107579001A (en) | The forming method of semiconductor devices | |
| CN106098694B (en) | A kind of Nonvolatile memory structure and preparation method thereof | |
| CN102041508A (en) | Groove etching method | |
| CN104078346A (en) | Planarization method for semi-conductor device | |
| TWI774311B (en) | A passivation layer for a semiconductor device and method for manufacturing the same | |
| TW201822298A (en) | Semiconductor structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20161116 |
|
| RJ01 | Rejection of invention patent application after publication |